JPH0944399A - Arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption by incorporating a small-scale memory, where a linear prediction coefficient or the like is frequently held, in a chip besides a data memory. SOLUTION: With respect to voice encoding/decoding, data which is not accessed many time is held in a data memory 1. Data like the linear prediction coefficient which is accessed many time is held in a small-scale data memory 4. As the result, an operation part 5 accesses the small-scale data memory 4 when accessing the linear prediction coefficient at the time or operation, thus reducing the power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit having data storage means, and more particularly to an arithmetic unit such as a digital signal processor for performing voice code decoding processing.

[0002]

2. Description of the Related Art In an arithmetic unit such as a microprocessor or a digital signal processor, an arithmetic unit including an ALU, a multiplier, a register and the like and a data memory holding data are connected by a bus to exchange data.

A conventional arithmetic unit will be described below with reference to FIG. In FIG. 5, 101 is a data memory, which holds data. Reference numeral 102 denotes an A bus, which connects the data memory 101 and a calculation unit 104 described later. 10
Reference numeral 3 is a B bus, which connects the data memory 101 and the arithmetic unit 104 described later. Reference numeral 104 denotes an arithmetic unit, which is an A bus 1
02 and the data of the B bus 103 are operated.

The arithmetic unit configured as described above operates as follows. One or two data is read from the data memory 101. The read data is processed by the arithmetic unit 1 via the A bus 102 and the B bus 103.
04. The calculation result in the calculation unit 104 is transferred to the data memory 101 via the A bus 102 or the B bus 103.
Stored in.

[0005]

However, in the above conventional arithmetic unit, since the same data memory is accessed for any data, the power consumption is the same regardless of which data is accessed. There is a problem that power consumption cannot be reduced. On the other hand, in order to reduce the power consumption, there is a method in which the data memory is divided into small blocks and only the blocks to be accessed are operated.
In this case, since the number of decoding stages is increased by dividing the block into small units, there is a problem that the chip area is increased by the decoding circuit and the cost of the chip is increased. Further, the increase in the number of decoding stages causes a problem that it is difficult to improve the access speed (operation speed).

An object of the present invention is to solve the above-mentioned conventional problems, and to provide an arithmetic unit which consumes low power and is inexpensive and capable of high-speed operation.

[0007]

In order to achieve the above object, the arithmetic unit of the present invention has a small data memory for holding a frequently accessed variable, in addition to the conventional data memory, and frequently accessed. A variable, for example, a linear prediction coefficient in a voice coding / decoding process, is held in a small-scale data memory.

[0008]

According to the present invention, by virtue of the above-described configuration, a variable that frequently accesses a small-scale memory with low power consumption is accessed instead of a normal memory with high power consumption. By holding a linear prediction coefficient that is accessed a very large number of times in the encoding / decoding process in a small-scale memory, it is possible to reduce the number of times the normal memory operates and reduce power consumption.

Further, since a small-scale memory can be arranged in a dead space on the layout generated by the building block design, the chip area is not increased so much and the arithmetic unit can be realized at low cost.

Further, as compared with the method of dividing a normal memory into a small-scale data memory, an increase in the number of decoding stages can be suppressed, so that it is possible to provide an arithmetic unit capable of operating at high speed.

Therefore, according to the present invention, it is possible to provide a low power consumption, low cost, and high speed operation device.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the following description is solely for the purpose of explaining the present invention and does not limit the content of the present invention.

FIG. 1 is a schematic block diagram showing an arithmetic unit in one embodiment of the present invention. In FIG. 1, reference numeral 1 is a data memory, which holds data. Reference numeral 2 denotes an A bus, which connects the data memory 1 and the arithmetic unit 5 described later. 3
Is a B bus, which connects the data memory 1 and the arithmetic unit 5 described later. Reference numeral 4 is a small-scale data memory, which holds frequently accessed data. Reference numeral 5 denotes an arithmetic unit, which performs arithmetic operations on the data on the A bus 2 and the B bus 3.

A method of calculating data in the calculation device configured as described above will be described. Data that is not frequently accessed is held in the data memory 1. For example,
When it is necessary to read out two data that are accessed only a few times, each data is supplied from the data memory 1 to the arithmetic unit 5 via the A bus 2 and the B bus 3. The calculation unit 5 performs the calculation.

Variables that are frequently accessed are stored in the small-scale data memory 4 according to the instructions of the program. The calculation to the variable stored in the small-scale data memory 4 is read from the small-scale data memory 4 via the B bus 3 and stored in the calculation unit 5. When only the access to the small-scale data memory 4 occurs, the operation of the data memory 1 is stopped.

Next, an example of the voice encoding process will be described.
In recent digital mobile communications, the CELP coding method is often used. The CELP encoding process is performed according to the following procedure. Performs linear predictive analysis on input speech. The linear prediction coefficient calculated by the linear prediction analysis is stored in the small-scale data memory 4. Speech is synthesized from the linear prediction coefficient stored in the small-scale data memory 4 and the sound source codebook information stored in the data memory 1. The codebook information that minimizes the error between the synthesized voice and the input voice is selected. The linear prediction coefficient and information indicating which codebook is selected are transmitted as a code.

Among the above procedures (1) to (5), the data read from the sound source codebook is changed many times, and therefore the number of operations is very large. Further, in these steps, the linear prediction coefficient stored in the small-scale data memory 4 is commonly accessed when reading out any codebook data, so the number of accesses to the small-scale data memory 4 is extremely large. Will increase. That is, it is possible to reduce the frequency of access to the data memory 1 that consumes a large amount of current, and as a result, the number of operations of the data memory 1 is reduced and the current consumption is reduced.

Further, in the above embodiment, the embodiment of the voice encoding process is described. However, if there is a variable to be accessed many times other than the voice encoding process, it is held in the small-scale data memory 4. This has the effect of reducing power consumption. When this arithmetic unit is applied to an embedded application, the program to be executed is determined at the time of incorporation, and variables that are accessed many times are often known algorithmically.

Conventionally, as such a small scale memory,
There is a cache memory (Translated by Shinji Tomita et al., "Computer Architecture", Nikkei BP, Chapter 8, etc.). The cache memory does not explicitly control which data is held by the program, but manages which data is held using hardware. Therefore, it is necessary to have a storage means for holding information about the address of the main storage means. Therefore, the circuit scale is increased, and a copy of the same data as the main memory is held in the cache memory, so that the same data is held in two places. That is, the storage means is wasted.

On the other hand, in the present embodiment, since the data is arranged in the small-scale data memory by the program, it is not necessary to have the information of the address of the main memory. Therefore, the problem that the circuit scale increases does not occur. In addition, there is no waste due to having the same data in two places.

On the other hand, there is a register as a small-scale data memory in which data is arranged by a program. However, the number of registers is defined by the instruction set architecture. Increasing the number of registers has a problem that the bit length required to instruct the registers in the instruction set increases and the instruction word length increases. For example, when the number of registers is four, the number of bits required to instruct the register is two, but when the number of registers is eight, three bits are required to instruct the register.

In this embodiment, the small-scale data memory is treated as a memory because of the instruction set architecture. Therefore, there is no need to change the instruction set architecture, and the problem of an increase in instruction word length due to an increase in the number of registers does not occur. On the other hand, if it is handled as a memory in the instruction set architecture, there is a problem that the addressing ability is lowered. However, since small-scale data memory is often accessed as a continuous array, post-increment and post-decrement modifications work well even if addressing by pointers is performed, resulting in a decrease in computing capacity due to insufficient addressing capacity. Does not occur.

Next, the layout design of this embodiment will be described. A large-scale LSI is often designed by a building block method. The building block method is a method of designing by building blocks of different shapes (supervised by Takuo Sugano, ULSI design technology,
IEICE etc.). In general, each block is designed to have a rectangular shape, and the VLSI chip outer shape also has a rectangular shape. Therefore, in the design of the building block method, a dead space may occur due to the shape of each functional block. This is because the aspect ratio may be determined by the basic operation length of data in the memory section, the data path section, and the like.

In addition to the above-mentioned memory section and data path section, a building block may be designed by using a layout-designed processor core or functional block as one block. At this time as well, since it is not possible to change the aspect ratio of the block as described above, a dead space may occur.

FIG. 2 is a layout diagram on the chip of the digital signal processor. It is composed of a data memory 1, an instruction memory 5a, and an instruction decoder / operation unit 5b, and a small-scale data memory 4 is arranged in the upper right dead space. By mounting a small-scale memory 4 in such a dead space, it is possible to prevent an increase in chip area.

Next, a second embodiment of the present invention will be described. FIG. 3 is a schematic block diagram showing an arithmetic unit according to the second embodiment of the present invention. The same parts as those used in the description of the first embodiment described above are designated by the same reference numerals.
In FIG. 3, reference numeral 1 is a data memory, which holds data. Reference numeral 2 denotes an A bus, which connects the data memory 1 and the arithmetic unit 5 described later. 3 is a B bus, and data memory 1
And a calculation unit 5 described later are connected. A small data memory 4 holds data. Reference numeral 5 denotes an arithmetic unit, which performs arithmetic operations on the data on the A bus 2 and the B bus 3. A C bus 6 connects the small-scale data memory 4 and the arithmetic unit 5. A switch 7 separates or connects the B bus 3 and the C bus 6.

A method for calculating data in the arithmetic unit configured as described above will be described. When reading two pieces of data from the data memory 1, it operates as follows. One of the data is read out via the A bus 2.
The other data is supplied to the arithmetic unit 5 via the B bus 3, the switch 7 and the C bus 6. At this time, the switch 7 is connected. In the calculation unit 5, for each data,
Perform the operation.

Variables that are frequently accessed are stored in the small data memory 4. The variables stored in the small-scale data memory 4 are read from the small-scale data memory 4 via the C bus 6. When accessing the small-scale data memory 4, the switch 7 is separated. As a result, the capacity of the bus when connecting the small-scale data memory 4 to the arithmetic unit 5 is reduced.

The power consumption of the CMOS circuit is proportional to the capacity. Therefore, in the present embodiment, the bus capacity is reduced when the small-scale data memory 4 is connected to the arithmetic unit 5, so that the power consumption can be reduced.

The switch 7 has a pass transistor structure (a) as shown in FIG. 4 or a buffer structure (b).
However, it is not particularly limited.

[0031]

As described above, according to the present invention,
Since frequently accessed data such as a linear prediction coefficient is stored in a small-scale memory, it is possible to provide an arithmetic unit with low power consumption. Also, adding a small memory,
This method is suitable for high-speed operation because it requires less increase in the number of decoding stages than the method of reducing the current consumption by reducing the operation block of the large-scale data memory. Further, by arranging in a dead space on the layout of the VLSI chip, it is possible to prevent the increase of the chip area, so that it is possible to prevent the cost increase.

As described above, according to the present invention, it is possible to provide a low power consumption, high speed operation, and low cost arithmetic unit.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an arithmetic unit according to a first embodiment of the present invention.

FIG. 2 is a plan view showing the layout of the arithmetic unit according to the first embodiment of the present invention.

FIG. 3 is a schematic block diagram showing an arithmetic unit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a switch structure according to a second embodiment of the present invention.

FIG. 5 is a schematic block diagram showing a conventional arithmetic unit.

[Explanation of symbols]

 1 data memory 2 A bus 3 B bus 4 small-scale data memory 5 arithmetic unit 6 C bus 7 switch

Claims (6)

[Claims] 1. An arithmetic unit in which a data storage means and an arithmetic means are connected by a bus, and a storage means having a capacity smaller than that of the data storage means is connected to the bus and mounted on the same chip as the data storage means. Arithmetic unit. 2. The small-capacity storage means holds frequently accessed data in an architectural memory space under the control of a program.
The arithmetic unit according to the above. 3. The arithmetic unit according to claim 1, wherein a linear prediction coefficient that is frequently accessed in the voice codec processing is held in a storage means having a small capacity. 4. The arithmetic unit according to claim 1, wherein a switch is provided between the data storage means and the storage means having a small capacity so that the storage means having a small capacity and the data storage means can be separated from each other. 5. A storage means having a small capacity, wherein frequently accessed data is architecturally held in a memory space under the control of a program.
The arithmetic unit according to the above. 6. The arithmetic unit according to claim 4, wherein a linear prediction coefficient that is frequently accessed in the voice codec processing is held in a storage means having a small capacity.