JPH0944140A - Method and device for dot pattern conversion, and memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a superposing processing, etc., as to a document editing device. SOLUTION: The device is provided with a line pitch change information output means 2 which outputs line pitch change information for a change to the line pitch of character lines, a dot pattern generating means 4 which converts the line pitch into the character dot pattern of line pitch corresponding to the line pitch change information as a character dot pattern of size of each character in response to the line pitch change information and generates storage reference position specification information on the converted character dot pattern, a storage means 6 which stores a plurality of lines of the character dot pattern, and a writing means 8 which writes character dot patterns generated by the dot pattern generating means in storage locations of a storage means 6 specified with the storage reference position specification information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot-pattern conversion method and device, and a memory device capable of performing required processing on a dot pattern that has been edited before being encoded after being edited. Regarding In an information processing system, a document editing apparatus that is connected to a host device, converts a code of a document or the like transferred from the host device into a dot pattern, encodes the dot pattern into code data, and returns the code data. Is used as one component for constructing an information processing system. Even in such a document editing apparatus, improvement and enhancement of its performance are required.

[0002]

2. Description of the Related Art FIG. 9 shows a conceptual diagram for explaining technical matters that are problematic in the context of the present invention regarding a conventional document editing apparatus. In the conventional document editing apparatus, the communication control interface unit 20 is transferred from the host apparatus 200.
One transfer unit (block = 4080 bytes) of a monochrome binary still image received in the character code buffer 204 via 2 is, for example, the code of each character forming a document is the line editing device 20.
In step 6, one line of the document is used as one editing unit and each character in the editing unit is converted into a character dot pattern and written in the line buffer 210.

After writing the character dot pattern for one line to the line buffer 210, an encoding process for the character dot pattern for one line, for example, MH encoding process, M ²
The R coding process is performed by the coding circuit 212, and the code is written in the code code buffer 214. In this writing, control is performed so as to give a line spacing as shown in FIG.

The conversion process and the encoding process for the code for one line are performed for each line, and the code data amount written in the code code buffer 214 is, for example, 4080.
When the number of bytes is reached, the 4080 bytes are transferred to the higher-level device 200 as one block transfer unit.

[0005]

As described above, the conventional document editing apparatus sequentially encodes the character dot patterns in the line buffer 210 after the conversion from the data code to the character dot pattern is completed. , Processing control cannot be returned to an arbitrary editing position.

As a result, after editing, that is, conversion processing from the code to the character dot pattern, another character dot pattern or another dot pattern is superposed, and a character dot pattern having a size extending over a plurality of lines is generated. Processing and editing processing of the document in the sub-scanning direction cannot be performed. The present invention was created in view of the above technical problems, and includes overlay processing, generation processing of character dot patterns of various sizes, editing processing in the sub-scanning direction, memory clear processing by hardware, and testing. It is an object of the present invention to provide a dot-pattern conversion method and device capable of performing processing and the like, and a memory device.

[0007]

FIG. 1 shows a block diagram of the principle of the present invention. FIG. 2 shows a principle block diagram of the invention according to claims 5 to 7. FIG. 3 shows a principle block diagram of the invention according to claims 8 to 10. According to the first aspect of the present invention, the conversion rate of the code into the dot pattern is determined, the code is converted into the dot pattern having the determined conversion rate, and the dot pattern sequence stored in advance is not overlapped. It is characterized in that the storage reference positions of the dot patterns converted into are aligned and stored.

According to the first aspect of the present invention, when the code is converted into the dot pattern, the conversion rate is determined, and the code is converted into a dot pattern having a size determined by the conversion rate. Then, the storage reference positions of the converted dot patterns are aligned and stored so that the converted dot patterns do not overlap the previously stored dot pattern rows. Therefore,
It is possible to generate rows of dot patterns having different row pitches.

According to a second aspect of the present invention, the first code is converted into the first dot pattern and stored, and the stored first code is stored.
Read out and hold the above dot pattern, convert the second code into the second dot pattern, and logically combine the held first dot pattern and the converted second dot pattern. , And stores the synthesized dot pattern.

According to the second aspect of the invention, the first dot pattern stored in advance is read and held. After this holding, the second code is converted into the second dot pattern, and the converted dot pattern and the held dot pattern are logically combined and stored. Therefore, it is possible to superimpose dot patterns.

According to a third aspect of the present invention, a character code in the sub-scanning direction is sequentially converted into a dot pattern, and the operation of storing the character dot pattern by rotating the character dot pattern by 90 ° in the clockwise direction is performed for each character in the sub-scanning direction. It is characterized in that it is repeated for each character code of the code string, and the stored dot pattern is read out in the main scanning direction and encoded. According to the third aspect of the invention, the character code in the sub-scanning direction is sequentially converted into a character dot pattern. For each converted character dot pattern, the character dot pattern is rotated by 90 ° in the clockwise direction and stored. The rows of the stored dot pattern are read out in the main scanning direction and encoded.

Therefore, it is possible to edit characters in the sub-scanning direction. In a document editing apparatus for receiving a code and converting it into a dot pattern as shown in FIG. 1, when the character line of the received character code includes large and small characters, a line pitch for a large character is obtained. A line pitch change information output means 2 for outputting line pitch change information for changing to the line pitch of the character line, and a character dot pattern of the size of the character for each character in response to the line pitch change information. And a dot pattern generating means 4 for converting the line pitch into a character dot pattern having a line pitch corresponding to the line pitch change information and for generating storage reference position designation information of the converted character dot pattern, and a character dot pattern. Of the character dot patterns generated by the dot pattern generating means 4 are stored in the storage reference position specifying information. Characterized in that a writing means 8 to be written into storage locations of said storage means designated in.

According to the invention described in claim 4, as in the invention described in claim 1, dot patterns having different row pitches can be generated. The means is a row pitch change information output means 2, a dot pattern generation means 4, a storage means 6,
And writing means 8. According to a fifth aspect of the present invention, as shown in FIG. 2, in a document editing apparatus that receives a code and converts it into a dot pattern, a first dot pattern having a predetermined line pitch and storage reference position designation information are input. Input means 5, storage means 6 for storing a plurality of lines of character dot patterns, and storage of the storage means 6 in which each of the character dot patterns input from the input means 5 is designated by the storage reference position designation information. It is connected to the writing means 8 for writing in the position, the reading means 10 for reading the second dot pattern to be superposed from the storage means, the computing means 14 having the holding means 12, the input means 5 and the reading means 10. , Arbitration means 16 for arbitrating access competition to the storage means 6 by the input means 5 and the reading means 10, and the arbitration means After the dot pattern arbitrated by 16 and read from the storage unit 6 is held in the holding unit 12, the dot pattern arbitrated by the arbitration unit 16 and input to the arithmetic unit 14 and the holding unit 12 are held. It is characterized in that the dot pattern held in the above is combined and the combined dot pattern is stored in the storage means 6 by the writing means 8.

According to the fifth aspect of the invention, the second dot pattern stored in the storage means 8 is read by the reading means 10 and held in the holding means 12. After that, the dot pattern input by the input unit 5 and the held dot pattern are combined and stored in the storage unit 6 by the writing unit 8. Therefore, the dot patterns can be combined.

According to a sixth aspect of the present invention, as shown in FIG. 2, in the document editing apparatus according to the fifth aspect, the first dot pattern is a first character dot pattern or a first image dot pattern. And the second dot pattern is a second character dot pattern or a second image dot pattern.

According to a sixth aspect of the invention, in the fifth aspect of the invention, the first dot pattern is the first character dot pattern or the first image dot pattern, and the second dot pattern is the second. The character dot pattern or the second image dot pattern is used. According to the invention described in claim 7, as shown in FIG. 2, in the document editing apparatus according to claim 6, when the input means 5 includes large and small characters in the character line of the received code, a line pitch is set for a large character. A line pitch change information output means for outputting line pitch change information for changing the line pitch of the character line, and a character dot pattern of the size of the character for each character in response to the line pitch change information, And the line pitch is converted into a character dot pattern of the line pitch according to the line pitch change information,
And dot pattern generating means for generating storage reference position designation information of the converted character dot pattern.

According to a seventh aspect of the present invention, in the sixth aspect of the invention, character dot patterns having different line pitches are generated. The invention according to claim 8 is, as shown in FIG. 3, a logical operation including a memory 20, an access signal conversion circuit 22 for converting an input access signal into an access signal for the memory 20, and a holding circuit 23. The circuit 24 and first input means 26 for inputting an access signal to the access signal conversion circuit 22 while inputting the first dot pattern to the logical operation circuit 24.
And a second input means 28 for inputting a second dot pattern to the logical operation circuit 24 and an access signal to the access signal conversion circuit 22, and a read operation for reading the dot pattern stored in the memory 20. Circuit 29, input of the first dot pattern and access signal to the first input means 26, input of the second dot pattern and access signal to the second input means 28, and reading An arbitration circuit 30 for arbitrating access competition with the circuit 29 is provided.

The eighth aspect of the present invention is an invention relating to a memory device used in a document editing device. That is, it is a memory device used for superimposing a character dot pattern and a character dot pattern, synthesizing them, synthesizing a character dot pattern and an image dot pattern, and the like. According to a ninth aspect of the invention, as shown in FIG. 3, in the memory device according to the eighth aspect, a clear circuit for clearing the memory 20 is provided in the memory device.

According to a ninth aspect of the invention, in the eighth aspect of the invention, the memory device is provided with a clear circuit for clearing the memory. According to a tenth aspect of the present invention, in the memory device according to the eighth or ninth aspect, a test circuit for testing the memory is provided in the memory device. According to a tenth aspect of the present invention, in the ninth or tenth aspect of the invention, the memory device is provided with a test circuit.

[0020]

DETAILED DESCRIPTION OF THE INVENTION FIG.
An embodiment of the described invention is shown. As shown in FIG. 4, the document editing apparatus of this embodiment has a host interface unit 50, a main memory 52, and a processor 5 connected to a host device.
4, a character editing unit (KPG) 56, and a decoding / encoding unit 58. KPG is an abbreviation for Kangi Pattern Generator.

As shown in FIG. 5, the higher-level interface section 50 comprises a GPIF interface section 60, a buffer memory 62, an MPU 64, and a dual port RAM 66. The MPU 64 sends the GPIF control signal to the GP.
For example, the code of one document (hereinafter referred to as code data) is given to the IF interface unit 60 from the host device via the GPIF interface unit 60 by the DAM transfer method of the transfer unit, and is received by the buffer memory 62 for one transfer. The MPU 64 detects start information indicating the start of the unit.

The MPU 64 fetches the code data of one transfer unit of the buffer memory 62 into the receiving buffer 68 of the main memory 52, and the code data is a character code or a code from the header of the fetched code data. The command / control information for executing the determination processing is transferred to the processor 54. Here, the command causes the discrimination of the code type of the code data transferred from the buffer memory 62 to the reception buffer 68 and the generation of the character string information. The control information includes reset, test, etc.

The upper interface unit 50 also receives end information from the processor 54 as described later, transfers the end information in the transfer format from the MPU 64 to the buffer memory 62 to the upper device, and sends it to the transmission buffer of the main memory 52. A predetermined amount of code data written in 70, for example, 4080 bytes of code data is read from the transmission buffer 70 and D
After writing to the buffer memory 62 in the AM transfer format,
The predetermined amount of code data is transferred to the GPIF interface unit 6
It is transmitted to the upper device through 0.

In the processor 54, when the command / control information analysis unit 76 receives the command / control information from the upper interface unit 50, the command / control information analysis unit 76 analyzes the command / control information. Whether it is a code or code data, the processor 54 uses the reception buffer 68 as a code information buffer 72 when it is a character code, and uses the reception buffer 68 when it is a code code.
The reception processing control used as is passed to the buffer management unit 78. Further, the processor 54 passes control to the code analysis / character string editing unit 80 to generate character string information for each line of character code in the code information buffer 72 after the processing in the buffer management unit 78 is completed. The character string information includes a character code, a character type, a size, presence / absence of modification, etc. for each character. Under the control of the code analysis / character string editing unit 80, the character string information generated from the character code of each line in the code information buffer 72 is written in the character string information buffer 86.

Further, in response to the completion of generation of the character string information from the code analysis / character string editing unit 80 under task management, the processor 54 instructs the character editing unit 56 to execute the KPG control information and the character string information buffer. There is an input / output control unit 82 that gives control information to the character editing unit 56 to notify the DMA transfer unit from 86 to the character string information buffer 88. The input / output control unit 82 also sets the calculation mode for the decoding / encoding unit 58. The error / end information creation unit 84 receives the notification that the code data of one transfer unit has been transferred from the buffer memory 62 to the higher-level device, as described later.
4 sends the end signal to the error / end information creating unit 84 of the processor 54 via the dual port RAM 66,
The error / end information creating unit 84 sends the end information to the MPU 64 via the dual port RAM 66 when there is no error in the character editing unit 56, the decoding / encoding unit 58 and the like. MPU6
Reference numeral 4 creates end information in a format that can be transferred to the upper device, and informs the upper device of normal end via the buffer memory 62 and the upper interface unit 50. When there is an error, the error information is sent to the host device through the same process.

The processor 54 includes a higher-level interface unit 50, a main memory 52, a character editing unit 56, and a decoding / decoding unit.
The operation required to perform processing with the encoding unit 58 is
Although it is performed by a program, the ROM storing the program is not shown. The character editing unit 56 has a character string information buffer 88 that receives the character string information generated in the character string information buffer 86 of the main memory 52 via the driver / receiver 102.
8 is used to generate a character dot pattern corresponding to the character information in each character information in 8 and to pass the character dot pattern to the decoding / encoding unit 58, a Kanji ROM 92, an external character RAM (dual port RAM) 94, and pattern reading / scaling. It has a circuit 96 (see FIG. 6). Gaiji RAM9
Reference numeral 4 receives the external character dot pattern via the character string information generation path and stores the external character pattern. MPU90
In response to the character string information, the character code, the output position information of the character pattern, the character type, the size, and other information are transferred to the pattern reading / reducing circuit 96, and the memory request signal and the character dot pattern are decoded / encoded. An address and a control signal for writing to the binary still image memory (page memory) 110 of the unit 58 are supplied to the decoding / encoding unit 58 via the pattern read / enlargement circuit 96. The pattern read expansion / contraction circuit 96 transfers the character dot pattern corresponding to the character code to the decoding / encoding unit 58 in response to the information such as the character code, the output position information of the character pattern, the character type, and the size received from the MPU 90. (Figure 4, Figure 6,
(See FIG. 7). The ROM 98 shown in FIG. 4 stores a program for generating the character dot pattern corresponding to the character string information and the control information for writing the generated character dot pattern in the binary still image editing memory. .

The decoding / encoding unit 58 includes a binary still image memory (page memory) 110 and a decoding / encoding circuit 11.
There are two. The details of the binary still image memory 110 will be described below, but the decoding / encoding circuit 112
The dot pattern is encoded and the code code from the image information buffer 74 is decoded into a binary still image, which is a known technique per se.

As shown in FIG. 7, the binary still image memory 110 includes a DRAM 120, an arbitration circuit 122, a DRAM controller 124, a bus driver / receiver 126, and a bus driver / receiver 128, and the arbitration circuit 12
2 arbitrates contention between the character editing unit 56, the decoding / encoding circuit 112, and the DRAM 120 on the use of the bus. The bus driver / receiver 126 is connected between the decoding / encoding unit 58 and the DRAM controller 124. The bus driver / receiver 128 is connected between the character editing unit 56 and the DRAM controller 124. When the SRAM is used for the DRAM 120, the refresh controller 130 is unnecessary.

The arbitration circuit 122 is provided between the refresh process of the DRAM 120, the write request from the character editing unit 56, the write request to the decoding / encoding circuit 112, and the read request from the decoding / encoding circuit 112. The contention is arbitrated, and the memory ACK signal is returned to the access request source that is arbitrated and is permitted to access the DRAM 120.

The DRAM controller 124 includes the refresh controller 130 and the access signal conversion circuit 13.
2, a logical operation unit 134, and a setting / testing unit 136.

The refresh controller 130 has a DR
It is a publicly known device that controls the refresh operation of the AM 120, and is configured to have an address counter, a refresh counter, and a control signal generation circuit. The access signal conversion circuit 132 performs address conversion and control signal conversion. The address conversion converts address information into row signals and column signals. The control signal conversion is performed by converting the write signal and the read signal into RAS signals for rows and CA for columns.
Convert to S signal.

The logical operation unit 134 is a normal character editing unit 5
When writing the dot pattern of the character from 6 or the decoded dot pattern from the decoding / encoding circuit 112, the dot pattern to be written is passed through as it is, and the DRAM 1 at the time of read-modify-write.
A calculation is performed to transfer the logical sum of the dot pattern read from the memory 20 and latched in the latch circuit 140 and the dot pattern input from the character editing unit 56 via the bus driver / receiver 128 to the DRAM 120. Also, DRA
The rotation process for the dot pattern of the character written in M120 is also performed. The control signal at the time of read-modify-write and the control signal at the time of rotation processing control are also displayed in the character editing unit 5.
6 through the bus driver / receiver 128, but is shown as a write / control signal in FIG. 6 for simplification of the drawing. The dot pattern resulting from the editing process in the DRAM 120 is stored in the DRAM at the time of encoding.
The dot pattern at that time is read from 120 and transferred to the decoding / encoding circuit 112.
After being latched by 40, the decoding / encoding circuit 11 is passed through the driver 142 and the bus driver / receiver 126.
2 is transferred.

The setting / testing unit 136 clears the binary still image memory 110 to 0 and checks the binary still image memory 110 for errors.
4, control signal generation circuit 146, data generation circuit 148,
And a data comparison circuit 150. The 0 clear is a DR in which the data generation circuit 148 generates 0-bit bus width data and is in a write state in response to a write control signal generated from the control signal generation circuit 146.
The AM 120 is performed by sequentially writing to the writing position of the DRAM 120 designated by the address generated by the address generating circuit 144. The error check is performed on the DRAM 120 which is in a write state in response to a write control signal (RAS signal, CAS signal) generated by the data generation circuit 148 and generated by the control signal generation circuit 146. DRAM1 designated by an address generated from the circuit 144
It is performed by writing the test data at the write position of 20, reading the written test data from the DRAM 120, and comparing the read data with the data at the time of writing by the data comparison circuit 150.

The decoding / encoding circuit 112 encodes the dot pattern written in the binary still image memory 110 into encoded data according to a predetermined encoding method and transfers the encoded data to the image information buffer 74, or the image information buffer 74. It is used for decoding the coded data written in and transferring it to the binary still image memory 110. 4 to 7, the MPU
90 corresponds to the line pitch change information output means 2 of FIG.
The pattern read expansion / contraction circuit 96 corresponds to the dot pattern generation means 4 in FIG. The DRAM 120 corresponds to the storage unit 6 of FIGS. 1 and 2, and has the access signal conversion circuit 13
2 and the logical operation unit 134 correspond to the writing unit 8 in FIGS. 1 and 2. The MPU 90 and the pattern read expansion / contraction circuit 96 correspond to the input unit 5 of FIG. 2, and the pattern read expansion / compression circuit 96, the access signal conversion circuit 132, and the logical operation unit 134 correspond to the read unit 10. The latch circuit 140 corresponds to the holding means 12 in FIG. 2, and the arbitration circuit 122 corresponds to the arbitration means 16 in FIG. DRA
M120 corresponds to the memory 20 of FIG. The access signal conversion circuit 132 is the access signal conversion circuit 22 of FIG.
Corresponding to, the logical operation unit 134 is the logical operation circuit 2 of FIG.
Corresponds to 4. The latch circuit 140 is the holding circuit 2 of FIG.
Corresponds to 3. The bus driver / receiver 128 is shown in FIG.
Of the bus driver / receiver 126 corresponds to the second input means 28 of FIG. The arbitration circuit 122 corresponds to the arbitration circuit 30 in FIG. Bus driver / receiver 128, access signal conversion circuit 13
2 corresponds to the read circuit 29 of FIG.

The operation of the document editing apparatus of the present invention configured as described above will be described below with reference to FIGS. 4, 5, 6 and 7. Conversion target information such as character code data or code code data, for example, a document is transferred from a higher-level device when the code data is converted into a dot pattern.

It is assumed that the object to be converted is a document and the character string lines of the document do not include characters of different sizes (see (A) of FIG. 8). Further, it is assumed that the document can be transferred in one transfer unit in order to simplify the explanation. The control information necessary for performing the conversion for each character is also added and transferred. The code data forming the document is transmitted from the MPU 64 to the GPI 64 after the transmission / reception protocol procedure is taken between the host device and the host interface unit 50 in the same manner as in the conventional case, and the state becomes receivable.
It is received by sending a GPIB control signal to the F interface unit 60. Code data received via the GPIF interface unit 60 of the upper interface unit 50 under the control of the MPU 64 is written in the buffer memory 62 by the DAM transfer method. When the start information of the code written in the buffer memory 62 is recognized by the MPU 64,
A command for fetching the document into the main memory 52 is issued from the MPU 64 and the dual port RAM 6
6, transferred to the processor 54 via the bus 55 (see FIG. 4).

DMA transfer is started from the MPU 64 to the DMA transfer unit (not shown) which performs DMA transfer between the buffer memory 62 and the reception buffer 68 in response to the accumulation of the code data for the transfer unit in the buffer memory 62. Give a signal. Upon receiving the command, the command / control information analysis unit 76 passes control to the buffer management unit 78 to determine whether the code data in the reception buffer 68 is a character code or a code code, and sends the control to the character string information buffer 88. A process of converting control of each character code in the written character string information into a character dot pattern to the character editing unit 56 via the input / output control unit 82 is performed.

The buffer management unit 78, to which the control is passed as described above, receives the code data from the buffer memory 62 into the reception buffer 68 and determines whether the received code data is a character code or a code code. To do. When it is a character code, the reception buffer 68 is used as the code information buffer 72, and when it is a code code, the reception buffer 68 is used as the image information buffer 74. Since the code data received as described above is an example of a character code, the reception buffer 68 corresponds to the case of being used as the code information buffer 72.

Therefore, in this case, the buffer management unit 7
Reference numeral 8 is a code analysis / character control for the processing of analyzing the character code and control information written in the code information buffer 72 to the code analysis / character string editing unit 80 and passing the character string information to the character editing unit 56. It is given to the column editing unit 80. Code analysis / character string editing unit 80 under the control
Is a character string information buffer 86 for each character code written in the code information buffer 72 in response to the control information such as the character code, the output position (storage reference position designation information), the character type, the size, and the presence / absence of modification. Set to.

After this setting is completed, the character editing unit 56 uses the task management program (not shown) that also manages the command / control information analyzing unit 76 of the processor 54 to perform the character string analysis by the code analyzing / character string editing unit 80. When the end of the information generation process is recognized, the character dot pattern generation control (KPG control) is received via the input / output control unit 82 and the character string information about each character written in the character string information buffer 86 is responded to. To generate a character dot pattern. When the KPG control is given, DMA transfer between the character string information buffer 86 and the character string information buffer 88 is also started. The generation of the character dot pattern is performed as follows.

The MPU 90 of the character editing unit 56, to which the KPG control is applied, reads out various kinds of setting information for one character from the character string information buffer 88 and reads out the pattern read / enlarge circuit 96.
Set to. When the size of each character in one line is the same and the scaling of the character converted to the character dot pattern is not set, the character dot pattern corresponding to the character code is the Kanji ROM 92 or the external character RAM 94. The memory request from the pattern reading / expansion / reduction circuit 96 of the character editing unit 56 is arbitrated by the arbitration circuit 122 of the decoding / encoding unit 58, and the ACK signal is sent to the character editing unit 56.
The character dot pattern read when it is returned to the pattern reading / expansion / reduction circuit 96 of FIG.
The value is transferred to the still image memory 110. The transfer unit is a data bus width, for example, 2 bytes (1 word). In addition, the dot data is stored in the binary still image memory 110.
The address and the write control signal to be written in the DRAM 120 are transferred from the pattern read expansion / contraction circuit 96 to the access signal conversion circuit 132 of the binary still image memory 110,
It is supplied to the RAM 120. Binary still image memory 110
The dot data transferred to is sequentially written so as to form a character dot pattern in the DRAM 120 according to the supplied address. For example, if the size of the character dot pattern is 24 × 24 dots,
Assuming that the data bus width is 1 word, the transfer and writing of the character dot pattern are performed by first transferring the first 1 word of the first row of 24 × 24 and writing the word to the DRAM 120. The address is transferred from the pattern read / enlargement / reduction circuit 96, and the word is written to the storage location specified by the address in the DRAM 120. DRA following this written storage location
The next 1 word in the first row is similarly written in the next 1 word position in the same bit row direction of M120.

The second half of the second word is set as a blank dot. The first word of the next character dot pattern is written from the position of the blank (1 byte). As a result, the dot pattern of the first row forming the character dot pattern is developed as a dot pattern in the DRAM 120. Then, each character in the arbitrary line is similarly dot-developed. As a result, the arbitrary row is dot-developed in the DRAM 120.

In the expansion processing as described above, dot expansion is similarly performed for each of the second and subsequent rows. By performing such dot expansion for each line of the document, the document is dot expanded in the DRAM 120. or,
During such dot development, refresh controller 1
30, the refresh process of the DRAM 120 is performed while avoiding the conflict between the character editing unit 56 and the decoding / encoding unit 58. This refresh process itself is
This is a conventionally known technique.

As described above, the reading start for the entire document dot pattern expanded in the DRAM 120 is activated from the input / output control unit 82. Also in this reading, arbitration is performed by the arbitration circuit 122. That is,
When the memory request by the decoding / encoding circuit 112 is accepted by the arbitration circuit 122, the access right is given to the reading from the DRAM 120 by the decoding / encoding circuit 112.

In this manner, the reading of each dot line forming the document dot pattern is performed, and the decoding / decoding is performed.
The encoding circuit 112 performs an encoding process using, for example, the MH encoding method. Such an encoding process itself is a known technique. The code is stored in the driver / receiver 10 of the decoding / encoding unit 58 under the control of the input / output control unit 82.
3 is written in the image information buffer 74, and when a predetermined transfer unit, for example, 4028 bytes is accumulated, the fact is transmitted to the MPU 64 of the upper interface unit 50, and the image information buffer 74 is used as the transmission buffer. DMA transfer from 70 to the buffer memory 62 is performed. When the transfer from the buffer memory 62 to the host device via the GPIF interface unit 60 is completed, the signal is transmitted to the MPU 64.

The MPU 64 is a dual port RAM
The transfer end is transmitted to the error / end information creating unit 84 via 66. If there is no error in the character editing unit 56, the decoding / encoding unit 58, etc., the error / end information creating unit 84 creates the end information, writes it in the dual port RAM 66, and then transfers it to the MPU 64. In response to the end information, the MPU 64 converts it into a transmittable code and writes it in the buffer memory 62. The code code of the buffer memory 62 is transferred to the host device via the GPIF interface unit 60 under the control of the MPU 64.

Next, a case will be described in which the character codes of the document given from the host device include character codes of different sizes. The processing in this case is performed by the character editing unit 56.
The process until the character string information is written in the character string information buffer 88 is the same as that when the size of the character represented by the character code is the same.

For convenience of explanation, the character string information buffer 8 will now be described.
It is assumed that the types of characters written in 8 are large and small, as shown in FIG. For the sake of explanation, it is assumed that the size relationship between the two characters is twice as large as that in small characters. Character spacing is assumed to be the same regardless of the size of the characters. The process itself of converting a character code into a character dot pattern is the same as when the character size is the same. For a character dot pattern in which a character converted into a character dot pattern is a small character, the pattern read enlargement / reduction circuit 96 adds a white dot row sufficient to fill the line pitch of a large character to increase the row pitch. Aligned to the line pitch of the letters,
Similarly to the case where the size of the character represented by the character code is the same, the data is transferred to the binary still image memory 110 and written in the binary still image memory 110. For characters with a large line pitch, the Kanji ROM 92 or Gaiji RAM
The character dot pattern read from 94 is enlarged in response to the character size information provided to the pattern read / reduce circuit 96 to a size designated by the size information. The bits from the uppermost dot line to the lowermost dot line of this enlarged character dot pattern are 2 bits of the decoding / encoding unit 58 in the same manner as in the case where the character size is the same as described above. The value is transferred to the still image memory 110. The transfer of a large character dot pattern requires four times the transfer amount as compared with the case where the size of characters in a character line is the same.

The DRAM 1 of the binary still image memory 110 of the character converted into the character dot pattern as described above.
Writing to 20 is the same except that the number of times of writing increases. Then, each line of the document is written in the same manner, and the entire document is dot-developed in the DRAM 120. The document dot-developed in the DRAM 120 is converted into a code code in the decoding / encoding circuit 112, and the encoding process is the same as when the character size is the same. The transfer to the higher-level device is also the same.

Next, the process of superposing the character dot pattern and the character dot pattern will be described. In this case, one character dot pattern to be superimposed is stored in the DRAM 120 in advance, and one character dot pattern to be superimposed has the same character size as the character editing unit 56. To the binary still image memory 110 of the decoding / encoding unit 58.

Prior to this transfer, arbitration by the same arbitration circuit 122 as described above is performed. By the arbitration, when the character editing unit 56 is given an access right to the DRAM 120, the transfer is performed. The control signal supplied to the pattern read / expansion / reduction circuit 96 is the same as that when the size of the character is the same, but the access signal conversion is performed from the pattern read / expansion / reduction circuit 96 of the character editing unit 56 via the bus driver / receiver 128. The control signal supplied to the circuit 132 becomes a read-modify-write control signal. With this control signal, first, the DRAM 120
The address of the character dot pattern to be superimposed and written to the access signal conversion circuit 132 is given, and the dot information of the read width (for example, one word width as described above) designated by the address is written. DRAM
After being read from 120 and latched by the latch circuit 140, one word that has been latched and one word from the pattern read expansion / contraction circuit 96 corresponding to this are logically summed by the logical operation circuit 134 and combined. , The synthesized one
The word is transferred to the DRAM 120 and latched by the latch circuit 14.
The 1 word latched at 0 is written to the 1-word storage location where it was stored. Such read-composition-
The write operation is performed for all bytes to be combined. As a result, the character dot pattern and the character dot pattern can be combined. For example, a and o can be combined to create a composite character having a in a o.

By performing the read-modify-write control as described above, the read operation and the write operation are performed in one cycle, so that the cycle becomes the same as a normal access cycle. Therefore, the read-modify-write operation is performed. The access cycle is reduced to half or less as compared with the case where the above operation is not used. Further, by changing the content of the logical operation, various various special processing such as blank characters and 90 ° rotation of the characters can be performed.

Furthermore, not only the above-described combination of character dot patterns and character dot patterns (including combination of Kanji dot patterns and Kanji dot patterns), but also combination of character dot patterns and image dot patterns, and image It is also possible to combine dot patterns. In the case of combining the character dot pattern and the image dot pattern, either one of them is previously written in the DRAM 120 in advance, as described above. The image dot pattern previously written in the DRAM 120 is transferred by a code code from the upper device and is written in the GPIF interface unit 60, the buffer memory 62, and the reception buffer 68 of the upper interface unit 50. While the reception buffer 68 is used as the image information buffer 74, it is decoded into an image dot pattern by the decoding / encoding circuit 112. The write address for each word of the decoded image dot pattern to the DRAM 120 is transferred from the upper device to the upper interface unit 50, and the buffer memory 62 outputs the MPU.
It is taken in by 64 and is transferred to the processor 54 along with the command. If the write address is fixed,
The command is transferred by the MPU 64 to the processor 54. Write control information is also set in the command.

Prior to the transfer of the image dot pattern decoded by the decoding / encoding circuit 112 to the binary still image memory 110, the same arbitration circuit 122 performs arbitration. When the decoding / encoding circuit 112 is given an access right to the DRAM 120, the decoding / encoding circuit 11
The image dot pattern decoded in 2 is transmitted from the decoding / encoding circuit 112 to the DRAM 12 of the binary still image memory 110.
Data is sequentially transferred to the binary still image memory 110 with a bus width of 0 (for example, 1 word). In addition, the command / control information analyzing unit 76 of the processor 54 is connected to the upper interface unit 5
The address and write control information of the command sequentially transferred from the MPU 64 of 0 access signal is passed through the command / control information analysis unit 76, the input / output control unit 82, and the bus driver / receiver 126 of the binary still image memory 110. By being supplied to the conversion circuit 132, subjected to address conversion and control information conversion and supplied to the DRAM 120, each one word of the image dot pattern of the bus width is stored in the DRAM 120 at the storage position specified by the address. Written in.

In this way, the character dot pattern is superimposed on the image dot pattern written in the DRAM 120 in the same reading operation as in the case of the character dot pattern and the character dot pattern described above.
This is achieved by producing a combining operation and a writing operation (read-modify-write processing operation).

The superposition of the image dot patterns and the image dot patterns is almost the same. That is, one image dot pattern has the DRAM 120 in advance in the same manner as described above.
, And then the other image dot pattern is written into the binary still image memory 1 of the decoding / encoding unit 58 in the same manner as described above.
Transferred to 10. Any of the binary still image memory 1
Also in the case of writing data to the DRAM 120 of 10, the writing is performed when the arbitration circuit 122 arbitrates and the write access is permitted. At the time of writing by the latter person, the logical operation unit 134 takes the logical sum in the processing operation of the read-modify-write, so that the image dot pattern and the image dot pattern are superposed, and the result is obtained. It is written in the DRAM 120. The writing is the same as the writing in the superposition of the character dot pattern and the character dot pattern.

Next, the character editing process in the sub-scanning direction of the document will be described. When the pattern read expansion / contraction circuit 96 of the character editing unit 56 tries to write a character dot pattern into the DRAM 120 via the logical operation unit 134 of the binary still image memory 110, the pattern read expansion / contraction circuit 96 outputs the data in the column direction of the document. A character dot pattern is generated for each character code, and the character dot pattern thus generated is decoded / encoded by the decoding / encoding unit 5 in the same manner as described above.
8 to the logical operation unit 134. At this time, a control instruction for causing the character dot pattern to rotate 90 ° in the clockwise direction is sent to the pattern reading / expansion / contraction circuit 96.

As a result, each character dot pattern is given 90 ° rotation in the clockwise direction and sequentially developed in the row in the same order as the column direction. Such an expansion occurs for each row. The dot pattern document encoded in the DRAM 120 is edited laterally with respect to the paper because each character dot pattern is given a 90 ° rotation in the clockwise direction. The same as above.

Finally, the clear processing and test processing of the DRAM 120 by the DRAM controller 124 will be described. The clearing process of the DRAM 120 is performed by the data generating circuit 148 of the setting / testing unit 136, for example, 1 of all 0.
Generates word clear data and D
By generating an address for writing in the 1-word write position of the RAM 120 from the address generating circuit 144 and generating a write control signal for the DRAM 120 from the control signal generating circuit 146, the DRAM 120
For example, 0 clear can be performed. In this case, the character editing unit 56 and the decoding / encoding unit 58 are operated by the DRAM 120.
Access to be suspended.

Since this clearing process can be performed by hardware, the initialization time can be shortened. Further, test data is generated from the data generation circuit 148, an address for writing the test data in the entire area of the DRAM 120 or a predetermined area is generated from the address generation circuit 144, and a write control signal to the DRAM 120 is generated as a control signal. The test data generated from the circuit 146 is written in the storage location of the DRAM 120 designated by the address.
After that, an address for reading the written data is generated from the address generation circuit 144, the data is read, the read data and the test data are compared by the data comparison circuit 150, and the storage position of one word is stored. Perform the test. The DRAM 120 can be tested by performing such a test for each one-word storage position. In this case, the character editing unit 56 and the decoding / encoding unit 5
In No. 8, access to the DRAM 120 is stopped.

Since this test processing can be performed by hardware, the memory check time can be shortened.

[0062]

As described above, according to the present invention, an arbitrary line pitch can be set. Therefore, even if characters of different sizes are included in the same line of a document, the lines within that line can be set. Each character of can be expanded to a character dot pattern. Further, since the characters in which dots are expanded can be read out after that, the character dot pattern and the character dot pattern can be combined. The same applies between the image dot patterns, and the character dot pattern and the image dot pattern can be combined. By developing the character dot pattern in the column direction in the row direction, editing processing in the sub-scanning direction of the document becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the invention according to claim 4;

FIG. 2 is a principle block diagram of the invention according to claims 5 to 7.

FIG. 3 is a principle block diagram of the invention described in claims 8 to 10.

FIG. 4 is a diagram showing an embodiment of the invention described in claims 1 to 10.

5 is a diagram showing a part of the processing flow of the embodiment shown in FIG. 4;

FIG. 6 is a diagram showing the rest of the processing flow of the embodiment shown in FIG.

FIG. 7 is a diagram showing a configuration of a binary still image editing memory.

FIG. 8 is a diagram showing an edited result according to the embodiment shown in FIG.

FIG. 9 is a conceptual diagram of a conventional document editing apparatus.

10 is a diagram showing an editing result by the document editing apparatus shown in FIG.

[Explanation of symbols]

 2 Row pitch change information output means 4 Dot pattern generation means 5 Input means 6 Storage means 8 Writing means 10 Reading means 12 Holding means 14 Arithmetic means 20 Memory 22 Access signal conversion circuit 23 Holding circuit 24 Logical operation circuit 26 First input means 28 second input means 30 arbitration circuit 90 MPU 96 pattern reading expansion / contraction circuit 120 DRAM 122 arbitration circuit 126 bus driver / receiver 128 bus driver / receiver 132 access signal conversion circuit 134 logical operation unit 140 latch circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 5/24 640 9377-5H G09G 5/24 640

Claims (10)

[Claims] 1. A conversion rate of a code into a dot pattern is determined, a code is converted into a dot pattern having a determined conversion rate, and conversion is performed so as not to overlap a previously stored dot pattern sequence. A dot-pattern conversion method, characterized in that the storage reference positions of the dot patterns are aligned and stored. 2. The first code is converted into a first dot pattern and stored, the stored first dot pattern is read out and held, and the second code is converted into a second dot pattern, A dot-pattern conversion method comprising logically combining the held first dot pattern and the converted second dot pattern and storing the combined dot pattern. 3. An operation of sequentially converting a character code in the sub-scanning direction into a dot pattern and rotating the character dot pattern by 90 ° in the clockwise direction and storing the operation is performed for each character code of each character code string in the sub-scanning direction. The dot-pattern conversion method is characterized in that the stored dot pattern is read out in the main scanning direction and encoded. 4. A document editing device for receiving a code and converting it into a dot pattern, when the character line of the received character code includes large and small characters, the line pitch of the large character is changed to the line pitch of the character line. Line pitch change information output means for outputting line pitch change information; and a character dot pattern of the size of the character for each character in response to the line pitch change information, and the line pitch is the line pitch change information. A dot pattern generating means for converting into a character dot pattern having a line pitch corresponding to, and generating storage reference position designation information of the converted character dot pattern; a storage means for storing a plurality of lines of the character dot pattern; Storage of the storage means in which each of the character dot patterns generated by the pattern generation means is designated by the storage reference position designation information Document editing apparatus characterized in that a writing means for writing the location. 5. A document editing apparatus for receiving a code and converting it into a dot pattern, an input means for inputting a first dot pattern having a predetermined line pitch and storage reference position designation information, and a line for a character dot pattern. Storage means for storing a plurality of characters, writing means for writing each of the character dot patterns input from the input means to a storage position of the storage means designated by the storage reference position designation information, and an overlay target from the storage means. Read-out means for reading the second dot pattern, arithmetic means having a holding means, and arbitration connected to the input means and the read-out means to arbitrate access competition to the storage means by the input means and the read-out means. Means for arbitrating the dot pattern read out from the storage means by the arbitration means. After holding the serial holding means,
The dot pattern arbitrated by the arbitration unit and input to the arithmetic unit and the dot pattern held by the holding unit are combined, and the combined dot pattern is stored in the storage unit by the writing unit. Characteristic document editing device. 6. The document editing apparatus according to claim 5, wherein the first dot pattern is a first character dot pattern or a first image dot pattern, and the second dot pattern is a second character dot pattern. Character dot pattern, or second
A document editing device having the image dot pattern of. 7. The document editing apparatus according to claim 6, wherein the input means changes a line pitch of a large character to a line pitch of the character line when the character line of the received code includes large and small characters. Line pitch change information output means for outputting change information, and a character dot pattern of the size of the character for each character in response to the line pitch change information, and a line pitch according to the line pitch change information And a dot pattern generating means for generating storage reference position designation information of the converted character dot pattern, and a document editing apparatus. 8. A memory, an access signal conversion circuit for converting an input access signal into an access signal for the memory, a logical operation circuit having a holding circuit, and a first dot pattern to the logical operation circuit. A first input means for inputting and inputting an access signal to the access signal conversion circuit; and a second input pattern for inputting a second dot pattern to the logical operation circuit and inputting an access signal to the access signal conversion circuit. Input means, a read circuit for reading out the dot pattern stored in the memory, input of the first dot pattern and access signal to the first input means, and the second input means to the second input means. An arbitration circuit for arbitrating access competition between the dot pattern and the access signal of 2 and the read circuit is provided. A memory device characterized by the above. 9. The memory device according to claim 8, wherein a clear circuit for clearing the memory is provided in the memory device. 10. The memory device according to claim 8 or 9, wherein a test circuit for testing the memory is provided in the memory device.