JPH0939296A - Led head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct the variation in an LED head and exactly perform gradation printing with a simple circuit by controlling light-emitting current in accordance with each variation correction data every light-emitting body and block, and also controlling light-emitting time in accordance with the gradation printing data. SOLUTION: The vibration correction data for every light-emitting body 2 is stored in a shift register 8, correction data for every block is in a shift register 10, and gradation printing data is stored in a shift register 12. The variation correction data is extracted at AND gates A1-A5, and current of a standard current generation circuit 32 is varied by switches S1-S5, thereby controlling light-emitting current from a mirror constant current circuit 20. In the same manner, by extracting variation data for every block at AND gates A16-A20, light-emitting current from the mirror constant current circuit 20 in controlled. In use of a shift register 28 and AND gates A6-A10, gradation printing is carried out by turning on an OR gate 16 with the pulse width corresponding to the weight of each bit of the gradation copying data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LED head, and more particularly to an LED head which corrects variations in units of light emitters and in units of blocks of light emitters and further performs gradation printing.

[0002]

2. Description of the Related Art Japanese Patent Publication No. 6-30891 discloses a thermal head in which a counter is provided for each dot to preset gradation printing data in the counter, and the counter is subtracted by one bit with an enable clock. It proposes to print until it reaches 0. However, this method cannot be applied to the LED head in which the variation of the light emitter is remarkable. In the LED head, there is a considerable variation in each block of the light emitters including a plurality of light emitters, for example, the LED array, and it is necessary to correct this. In addition, the variation among individual light emitters within the block is remarkable. Therefore, if all of these are to be processed by controlling the light emission time, the variation correction data in units of blocks, the variation correction data for each light emission body, and the gradation printing data are added before driving the light emission body to obtain the light emission time. Need to ask. Such processing requires a large amount of calculation, makes the LED head expensive, and hinders high-speed printing.

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to accurately correct variations in an LED head and print a gradation with a simple circuit.

[0004]

According to the present invention, a first memory for storing variation correction data for each light emitting body of an LED head and variation correction data for each block composed of a plurality of light emitting bodies in the LED head are stored. A second memory for storing the gradation print data for each light emitter of the LED head, a reading means for reading each data from each memory, and each light emitter. An output variable current source for supplying a light emission current, a light emission current control means for controlling the output variable current source according to the read data of the first and second memories, and changing the light emission current; And a light emission time control means for controlling the duration of the light emission current from the output variable current source according to the data of the third memory.

Preferably, each of the first to third memories is configured to store each of the data in a BCD code, and the reading means reads each of the data by time division in each memory. And the read-out first variable current source is configured to change its light emission current with a weight corresponding to each bit of the BCD code, and read the first variable current source.
And in synchronization with each bit of the second memory, the light emission current control means changes the light emission current from the output variable current source, and further, the light emission time control means, for each bit of the read third memory, The pulse generation circuit is configured to generate a pulse having a width corresponding to the weight, and the output variable current source generates a substantially constant light emission current during each pulse width.

[0006]

According to the invention of claim 1, the first memory stores the variation correction data for each light emitter, the second memory stores the variation correction data for each block, and the third memory stores the gradation printing data. Let Then, the output variable current source is controlled according to the variation correction data for each light emitter and the variation correction data for each block to control the light emission current. The light emission time is controlled according to the gradation print data. Therefore, the variation correction and the gradation printing can be performed separately, and the block variation correction and the variation correction for each light emitter can also be performed separately, and a synthetic calculation of the variation correction data and the gradation printing data is not required. .

According to the second aspect of the present invention, the variation correction for each light emitter, the variation correction for each block, and the gradation printing are performed in a time-divided manner, literally separately. The variation is corrected by changing the light emission current according to the weight of each bit in the BCD code of the variation correction data, and the gradation printing is performed according to the weight of each bit in the BCD code of the gradation printing data. The pulse width is controlled by controlling the light emission time.

[0008]

Embodiments FIGS. 1 to 4 show an embodiment and its modification. In FIG. 1, 2 is an individual light emitter, and the light emitter 2 is, for example, 6
An LED array is configured in units of 4 to 128, and each LED array is called one block, and for example, 40 blocks are used. In the LED head, the output variation for each block and each light emitting body 2 is remarkable, and it is necessary to correct these variations for gradation control. The LED head may be a static drive or a dynamic drive, but the present invention is suitable for a dynamic drive because the variation in units of blocks and the variation in units of light emitters 2 are processed separately. Four
Is a cathode drive transistor, 1 LED array
The blocks are sequentially driven. 6 is a cathode drive IC,
The plurality of cathode drive transistors 4 are sequentially turned on one by one. The cathode drive IC 6 counts the clock CLOCK from the printer main body, detects a block change from the count value of the clock, and controls the transistor 4.

Reference numeral 8 is a first memory composed of a shift register, which stores the variation correction data DATA1 for each light-emitting body 2 in B
It is CD-coded and stored in 32 steps of 5 bits in length, for example. 10 is a second memory including a shift register,
The variation correction data DATA2 for each block is BCD
It is encoded and stored in 32 steps of 5 bits, for example. Since the block variation correction data is unchanged, it may be stored in a non-volatile memory such as an EPROM instead of the shift register 10. Reference numeral 12 denotes a third memory including a shift register, which similarly BCD-codes the gradation print data DATA3 for each light-emitting body 2 and stores it in 5 bits and 32 gradations, for example. A latch circuit 14 receives data from the shift registers 8 and 12, A1 to A10 are AND gates for each light emitter 2, 16 is an OR gate, and 20 is a mirror constant current circuit for each light emitter 2.

Reference numerals 22, 24, 26, and 28 are, for example, 5-bit shift registers, and the shift registers 22 and 24 are driven by a strobe signal SCLK1. With this signal, output data bits are sequentially shifted one bit at a time, and the output bits are shifted. The duration is common. Further, the shift register 26 is driven by the strobe signal SCLK2, the data bit is shifted by one bit by this signal, and the duration of the output bit is common. The shift register 28 is composed of a frequency dividing circuit using a DFF and a gate. The difference from the normal frequency dividing circuit is that when there is data in the upper bit, the output of the lower bit is blocked. If the upper bits are shown on the left side, for example, if the internal output of the frequency divider is (0, 1,
In the case of (1, 1, 1), since there is data of 1 in the second bit from the top, the external output is (0, 1, 0, 0, 0). The shift register 28 is driven by the strobe signal SCLK3, and when the output time from the least significant bit is 1,
The output time for each bit changes in 5 steps of 1: 2: 4: 8: 16, and has an output time according to the bit weight. The shift register 28 corresponds to the pulse generation circuit.

S1 to S5 are switches, 30 is an OR gate, and 32 is a reference current generating circuit. The switches S1 to S5 switch the value of a built-in reference resistor to switch the reference current. The reference current values are, for example, 1 mA, 2 mA, and 4 mA. , 8m
There are 5 levels of A and 16mA. This corresponds to the weight of the BCD coded data in the shift registers 8 and 10. The mirror constant current circuit 20 includes a reference current generation circuit 32.
A light emitting current having a value equal to the reference current from is applied to each light emitting body 2, and its on / off is controlled by the OR gate 16.

AND gates A11 to A15 are connected to the shift register 10, and there are five AND gates A11 to A15 for each block. AND gate A11-A
A signal 15 from the drive IC 6 operates for each block, and reads out block variation correction data corresponding to the currently driven block from the shift register 10. OR1-OR
5 is an OR gate, OR gate OR1 is AND gate A
The lowest signal of each block from 11 is combined, and similarly, the OR gate OR2 combines the signal of the second place from the bottom,
The signals are combined in the following order. AND gates A16 to A20 synchronize the signals of the OR gates OR1 to OR5 with the signal from the shift register 26 by AND operation. Reference numeral 32 is an OR gate, which performs an OR operation on the outputs of the AND gates A16 to A20, and during the correction of the block variation, the OR gate 16
Turn on.

The LED head of FIG. 1 can be modified as shown in FIG. 2, and FIG. 2 shows only the modified part. 40 is parallel in
A serial-out shift register, OR6 is an OR gate, 42 is an AND gate, and a shift clock SCLK1
The output signal of the shift register 28 is used to sequentially shift the data in the shift register 40 to the left one bit at a time, and the lowest data is read. In this way, the shift register 40 is used without using the AND gates A1 to A10, and the variation correction data for each light emitter of the shift register 8 and the gradation printing data of the shift register 12 are sliced bit by bit. Can be read out.

Similarly, the shift register 10 is a cyclic shift register that shifts to the left by 1 bit by the shift clock SCLK2, and if only the least significant bit is read,
AND gates A11 to A15 and OR gates OR1 to OR
5 becomes unnecessary. In this case, AND gates A16 to A2
For example, the lowest signal of the shift register 10 is all input to 0, and the signal of the shift register 26 and the AND gate A are input.
The signal for each bit may be taken out in synchronization with 16 to A20.

FIG. 3 shows the operation of the embodiment. Variation correction data for each light emitter 2 is input to the shift register 8,
Grayscale print data is input to the shift register 12.
Further, the shift register 10 is supplied with correction data for variations in each block. All of these data are BC
D-coded and input. One block of data is input to the shift registers 8 and 12 and transferred to the latch circuit 14 by a latch signal (not shown).

FIG. 3 shows operation waveforms for one block. First, the shift clock SCLK1 is input to the shift register 22,
5 clocks are sent to 24. In the first one clock, the AND gate A1 and the switch S1 are turned on, the reference current generating circuit 32 operates according to the least significant bit of the variation correction data for each light emitter, and the reference current becomes 1 mA. Each mirror constant current circuit 20 is turned on / off by the OR gate 16 according to the value of the least significant bit of the variation correction data for each light emitter, and when it is on, the light emission current is 1 mA. At the next clock, the reference current becomes 2 mA, and the mirror constant current circuit 20 is turned on / off according to the value of the second bit from the bottom of the variation correction data for each light emitter, and when it is on, the light emission current is 2 mA. In the following, the reference current changes to 4 mA, 8 mA, and 16 mA, and in synchronization with this, the OR gate 16 is turned on / off according to the value of each bit in the variation correction data for each light emitter. In this way, the shift register 24 and the switches S1 to S1
The reference current value of the reference current generating circuit 32 is changed using S5, and in synchronization with this, the AND gates A1 to A5 and the shift register 22 are used to slice the variation correction data for each light emitter one bit at a time. The OR gate 16 is turned on / off in synchronization with the reading and the change of the reference current.

Next, the shift clock SCLK2 is sent to the shift register 26 for 5 clocks to correct the block variation. The block variation correction data for the block being driven is read using the AND gates A11 to A15, and is taken out via the OR gates OR1 to OR5. The fetched signal is synchronized with the output of the shift register 26 by the AND gates A16 to A20 and sent to the switches S1 to S5. Thus, the shift register 26 and the AND gate A1
6 to A20, etc. to set the data in the shift register 10 to 1
The data is sliced and read bit by bit, and the reference current of the reference current generation circuit 32 changes accordingly. And Gate A
The outputs of 16 to A20 are ORed by the OR gate 34, the OR gate 16 is turned on by the output F, and the mirror constant current circuit 20 is operated at the current value determined by the reference current generation circuit 32.

When the variation correction for each light emitter and the variation correction for each block are completed, gradation printing is performed. For this purpose, the shift clock SCLK3 is used for 5 clocks to output the output pulse having the pulse width of 1: 2: 4: 8: 16 from the shift register 28. With this pulse, AND gate A6
.About.A10 are operated, and the OR gate 16 is turned on for a time corresponding to the gradation print data from the shift register 12.
The emission current during driving with gradation print data is constant,
Although it may be 6 mA, it is 16 mA here.

FIG. 4 shows the principle of correction of variations and gradation printing in the embodiment. In the LED head, the output variation of each light emitter 2 with respect to the average light emission output of the block is, for example, ± 30.
%, There is even greater variation between blocks,
For example, about ± 100% exists. Therefore, the light emission current is changed by Δi1 so as to correct the variation between the blocks, and the light emission current is changed by Δi2 so as to correct the variation for each light emitter 2, and the variation is corrected. Therefore, the reference current of the reference current generating circuit 32 is set to 1 mA to 16 mA.
Change to 1
The data is taken out bit by bit, and the mirror constant current circuit 20 is turned on / off according to the variation correction data. The gradation control is performed by pulse width control using the shift register 28, and the light emission current is kept constant during the pulse width control.

The effects of the embodiment are shown. Since the correction of variations and the gradation printing are processed separately, the amount of calculation is small, a simple drive circuit can be used, and it is suitable for high-speed printing. Since the variation correction is divided into the variation for each light emitter and the variation for each block, the variation correction data for each block does not change, and the data transfer and processing become simpler. Since the control of the light emission current uses the reference current generation circuit 32 and the mirror constant current circuit 20, it is sufficient to change the reference current. Gradation printing is performed by pulse width control and can be performed separately from variation correction. Further, data can be taken out easily by AND gates A1 to A20, etc., and it is not necessary to provide a counter for each bit.

[0021]

According to the present invention, the variation correction and the gradation printing in the LED head can be accurately performed by a simple circuit. In particular, the variation correction for each light emitter, the variation correction for each block, and the gradation printing can be processed separately.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a main part of an LED head according to an embodiment.

FIG. 2 is a circuit diagram of a main part of a modified LED head.

FIG. 3 is an operation waveform diagram of the embodiment.

FIG. 4 is a characteristic diagram showing a principle of correction of gradation printing, light emitter variation, and block variation in the embodiment.

[Explanation of symbols]

 2 light emitter 4 cathode drive transistor 6 cathode drive IC 8 to 12 shift register 14 latch circuit A1 to A20 AND gate OR1 to OR6 OR gate 20 mirror constant current circuit 22 to 28 shift register S1 to S5 switch 30 OR gate 32 reference current generation circuit 40 Shift register 42 AND gate

Claims (2)

[Claims] 1. A first memory for storing variation correction data for each light emitter of the LED head, and a first memory for storing variation correction data for each block of a plurality of light emitters in the LED head. And a third memory for storing gradation printing data for each light emitter of the LED head.
Memory, a reading means for reading the respective data from the respective memories, an output variable current source for supplying a light emitting current to the respective light emitters, and a read data of the first and second memories. Light emission current control means for controlling the output variable current source to change the light emission current, and light emission time for controlling the duration of the light emission current from the output variable current source according to the read data of the third memory. An LED head provided with a control means and. 2. The first to third memories are configured to store the respective data in a BCD code, and the reading means reads the respective data by time division for each memory. The output variable current source is configured so that its light emission current changes with a weight corresponding to each bit of the BCD code, and is synchronized with each bit of the read first and second memories,
The light emission current control means changes the light emission current from the variable output current source, and the light emission time control means generates a pulse having a width corresponding to the weight of each bit of the read third memory. 2. The LED head according to claim 1, wherein the LED head is constituted by a circuit, and a substantially constant light emitting current is generated from the variable output current source during each pulse width.