JPH0936867A - Data transmission method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To process video audio data received by a receiver side in real time by generating the video audio data earlier in advance by a transmission delay time so as to compensate a transmission delay in a communication channel. SOLUTION: The data transmission system 1 is configured by data transmitters 3a-3f connecting to VTRs 14a-14f respectively interconnected by an ATM communication channels 2. The data transmitters 3a-3f calculate each transmission delay time and control VTRs 14a-14f based on the transmission delay time to generate data earlier than the actual time. Thus, the data transmitters 3a-3f at the transmitter side send PUD packets while compensating the transmission delay received at the ATM communication channel 2 in advance thereby allowing the data transmitters 3a-3f at a receiver side to process the received transmission data in real time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission method and apparatus for transmitting audio / video data or the like obtained from a D2 type VTR device through an ATM communication line using a predetermined transmission packet. .

[0002]

2. Description of the Related Art Conventionally, SMPTE (SoP) has been used as an infrastructure for transmitting digital audio / video data in a television broadcasting station or the like.
serial Digital Interface (SDI; Serial Digital I) defined as SMPTE-259M in the Society of Motion and Television Engineering
nterface) type transmission device is used. further,
A serial digital data interface (SDDI; Serial Digital Data Interface) that improves the SDI system while maintaining compatibility and enables variable length data and multiple types of data to be transmitted in one transmission packet.
rface) method is also proposed. In addition, recently, an asynchronous transmission mode (AT
The M) method has been put to practical use.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention Between a television broadcasting station and the like, an SDI system or an SD system is used via an ATM communication line.
There is a request to send and receive DI audio / video data. However, the transmission packet of the above-mentioned SDI system has a 1-word 10-bit structure, and as it is, it is not suitable for an ATM communication line for transmission using an ATM cell having a 1-word 8-bit structure. When a predetermined data pattern, for example, FFh, 00h, 00h is used as a flag or the like in a transmission packet used for transmitting user data, FFh, 00h is added to the data transmitted via the ATM communication line. , 00h data pattern must not occur.

In a television broadcasting station, etc.,
There are cases where it is desired to broadcast the transmitted audio / video data in real time (real time), and in this case, the transmission delay time that occurs in the communication line becomes a problem. That is, if the transmitted audio / video data is broadcast as it is by using the synchronization signal on the receiving side, a problem occurs such that the video is interrupted at the boundary of the video. In addition, there is a request to transmit the video / audio data together with the control data used for editing the video / audio data, or to make a voice communication between the user on the sending side and the user on the receiving side. is there.

The present invention has been made in view of the above-mentioned problems of the prior art, and for example, a data transmission method capable of performing data transmission between an SDI type transmission device and an ATM type transmission device, and The purpose is to provide the device. In addition, the present invention converts the data having a word width of 10 bits in the SDI system into the AT without causing a data pattern prohibited in the ATM communication line.
It is an object of the present invention to provide a data transmission method and device capable of converting into M type data having a word width of 8 bits.

Further, according to the present invention, the audio / video data is generated earlier by the transmission delay time in advance, the transmission delay in the communication line is compensated, and the video / audio data received by the receiving side is processed in real time. An object of the present invention is to provide a data transmission method and an apparatus therefor capable of performing the data transmission. Further, the present invention is to transmit, together with video / audio data, control data used for editing video / audio data, or audio data for communication between a user on the transmitting side and a user on the receiving side. It is an object of the present invention to provide a data transmission method and device capable of performing the above.

[0007]

In order to achieve the above object, a data transmission method according to the present invention uses D2 audio data and / or video data as transmission data to be transmitted, and sets the predetermined data. Asynchronous transfer mode (AT
M) A data transmission method for transmitting data through a predetermined communication line such as a communication line, wherein the transmission data is shuffled and operation timing of the transmission side with respect to a line clock supplied by the communication line is indicated. Synchronous data used to match the operation timing with the operation timing of the transmission side, identification data used to identify the transmission data, and data amount data indicating the data amount of the transmission data included in the same transmission packet. Shuffling data indicating a shuffling method for the transmission data, predetermined control data transmitted between the transmitting side and the receiving side, and transmission delay occurring between the transmitting side and the receiving side. Measurement data used for measuring time, and call data used for a call between the transmission side and the reception side And said transmission data shuffling are multiplexed and transmitted in the predetermined transmission packet.

Preferably, in the case where the communication line has a prohibition code for prohibiting transmission, each of the data included in the transmission packet and the data that may generate the prohibition code is combined with these data. Additional data that does not generate the prohibition code is added.

Preferably, a time at which the transmission data is processed is set on the receiving side, and the transmission data included in the transmission packet is transmitted by the transmitting side until it reaches the receiving side. It is generated earlier than the actual time by the delay time.

[0010] Preferably, the identification data includes delay time data indicating a time at which the transmission time is generated earlier than an actual time at the transmission side.

Preferably, the receiving side receives the transmission packet from the communication line, and from the received transmission packet, the transmission data, the synchronization data, the identification data, and the data amount data. Separating the shuffling data, the control data, the measurement data, and the call data, deshuffling the transmission data separated based on the shuffling data, and deshuffling the transmission data. Convert to original word width.

Further, the data transmission apparatus according to the present invention is an object of transmission from the first data transmission apparatus via a predetermined communication line such as an ATM communication line, and the time of processing in the second data transmission apparatus. Is a data transmission device that transmits the transmission data such that predetermined transmission data such as audio / video data that has been determined reaches the processing time of the second data transmission device, and at least the first transmission data. And a transmission data generating means for generating the transmission data that is earlier than the actual time by the transmission delay time that occurs between the first data transmission device and the second data transmission device. Shuffling means for shuffling the generated transmission data, the shuffled transmission data, and first data transmission for a line clock supplied by the communication line. Synchronization data used to match the operation timing of the second data transmission device with the operation timing of the first data transmission device, and identification data used to identify the transmission data. Data amount data indicating a data amount of the transmission data included in the same transmission packet, shuffling data indicating a shuffling method for the transmission data, the first data transmission device, and the second data transmission device. Predetermined control data transmitted between the first data transmission device and the second data transmission device, and measurement data used for measuring a transmission delay time generated between the first data transmission device and the second data transmission device; And the call data used for a call between the second data transmission device and the second data transmission device are multiplexed to generate a predetermined transmission packet. To a multiplexing means, and transmission means for transmitting the transmission packet generated in the second data transmission device via the communication line.

Preferably, the second data transmission device is
Receiving means for receiving the transmission packet from the communication line, the transmission data, the synchronization data, the identification data, the data amount data, the shuffling data, and the control from the received transmission packet. Separation means for separating data, the measurement data, and the call data, deshuffling means for deshuffling the transmission data separated based on the shuffling data, and deshuffling shifter The transmission data is the original word. And a word width reverse conversion means for converting the width.

[0014]

In the data transmission method according to the present invention, the audio data and the video data of the D2 system are targeted for transmission (transmission data) and are multiplexed with other predetermined data into a predetermined transmission packet so that an ATM communication line or the like is transmitted. To transmit through. For example, the data transmission method according to the present invention is the SDI method (S
MPTE-259M) and other transmission systems suitable for transmission of 1 word and 10 bits in width into 1 word and 8 bits in width suitable for ATM communication lines to easily correct data errors occurring on the communication lines. Shuffle to do.

The synchronous data indicates the operation timing on the transmitting side as an integer ratio of the frequency of the line clock supplied by the ATM communication line and the frequency of the internal block signal on the transmitting side. This synchronous data is used on the receiving side to generate an internal clock on the receiving side that is synchronized with the internal clock on the transmitting side from the line clock. Based on this internal clock, the operation timing on the receiving side is determined and Match the operation timing.

The identification data indicates which transmission data included in the same transmission packet is data of which line of which field. The data amount data indicates the data amount of the transmission data included in the same transmission packet. The shuffling data is the transmission data after shuffling.
It is used to restore the original order and shows a shuffling method for transmission data on the transmission side.

The control data is transmitted between data terminals such as personal computers connected to the transmitting side and the receiving side, and is used, for example, to control a VTR device or an editing device connected to the receiving side. The measurement data is used to measure the transmission delay time that occurs between the transmission side and the reception side. The call data is, for example, 15.
It is PCM audio data of 75/2 KHz × 8 bits and is used for a call between the transmitting side and the receiving side. These data and shuffled transmission data are multiplexed into a transmission packet and transmitted from the transmission side to the reception side.

[0018]

First Embodiment A first embodiment of the present invention will be described below.
FIG. 1 is a diagram showing a configuration of a data transmission system 1 according to the present invention. As shown in FIG. 1, the data transmission system 1
Is constituted by connecting the data transmission devices 3a to 3f to which the VTR devices 14a to 14f are connected, respectively, via the ATM communication line 2. Data transmission devices 3a-3
f mutually transmits predetermined transmission data, for example, audio / video data for a program or relay, via the ATM communication line 2.

The 155.52 MHz supplied from the ATM communication line 2 to the data transmission devices 3a to 3f, respectively.
Line clock NC used when processing the ATM cell as 8-bit parallel data by dividing the clock of
The frequency of LK is 19.44 MHz (155.52 / 8)
It is. On the other hand, an internal clock 4f _sc used in the data transmission devices 3a to 3f when transmitting by the SDI system
Is about 14.3 MHz. If each is correct,
The frequency of these clocks is an integer ratio (NCLK: 4f _sc
= 1188: 875).

The VTRs 14a to 14f use the internal clock 4
SD2 method which is an improved SDI method or SDDI method by recording / reproducing D2 standard digital audio / video data in synchronization with f _sc (hereinafter simply referred to as SDI method)
Data transmission device 3 in 143 Mbps serial format
Output to each of a to 3f.

FIG. 2 shows the data transmission device 3a shown in FIG.
3 f are transmission packets (SSCU-PDU packets, hereinafter referred to as “PDU”, which are mutually transmitted via the ATM communication line 2.
FIG. 3 is a diagram showing a configuration of “packet”). In addition,
The number attached to the left of the PDU packet indicates the byte length of each data, and the table attached to the right of the PDU packet indicates the content of each corresponding data.

In the PDU packet, the data TRS has FFh, 00h, and 00h as contents, and indicates the head position of the PDU packet. The data TRS, ancillary data (ANC; ANCillary) area and video data (VID)
It is prohibited that the data included in the PDU packet has a value of 00h or FFh, except for data inserted every 5 bytes in the (EO) area.

Each of the data RTS1 and RTS2 contains synchronous data RTS which has a 6-bit value obtained by subtracting 832 from the count value of the internal clock 4f _sc during the 1188 cycles of the external clock NCLK. However, since the transmission packet is transmitted at the time of 910 cycles of the internal clock 4f _sc , two count values may appear during the transmission of one transmission packet. Data RTS1, RTS2
The above two areas are secured to cope with such a case.

The data RTS1 and RTS2 correspond to the data transmission device 3 on the receiving side (hereinafter, if any of the data transmission devices 3a to 3f is not specified, the data transmission device 3 is referred to as the data transmission device 3).
Etc.) is used to establish network synchronization. A valid bit V (Varid) is entered in the sixth bit of the data RTS1 and RTS2, and the content of the valid bit V is, for example, a logical value 1 when these data are valid and when they are not valid. Has a logical value of 0. Further, in order to prevent the data value from becoming 00h and FFh, the logically inverted value of the valid bit V is added as the seventh bit.

The data LNID (Line Number ID) is used to identify the audio / video data of the transmission data contained in the ancillary data area and the video data area in the same PDU packet, and the 0th to 2nd bits. Indicates a field number (FN; Field Number) indicating a field including audio / video data, and third to seventh bits having a value of 0 to 31 indicate a line number (LN) indicating a line including audio / video data. ; Line Number).

The data LN1 takes a value in the range of 1 to 525 and is used together with the data LNID1 for identifying the audio / video data within the range of 2 fields. The 1st byte and the 2nd byte of the data LN1 have the 0th to 4th bits and the 5th bit of the numerical value, respectively.
9th bit is entered, and the 5th bit of each contains the logically inverted value of the 4th bit for the same reason as the valid bit V of the data RTS1 and RTS2.

The data LNID2 and LN2 are, for example, when the time at which the data transmission device 3 on the receiving side processes the transmission data transmitted is determined, for example, the received transmission data is converted into a program being broadcast in real time. When used, the data transmission device 3 on the transmission side is used when compensating for a transmission delay time occurring in transmission data (transmission packet) in the ATM communication line 2 or the like. That is, the data LNID2, L
N2 is for the audio / video data included in the same PDU packet, the VTR device 14 advances the transmission data by several lines to compensate the transmission delay time in the television broadcasting station on the transmission side, Indicates whether the data transmission device 3 has transmitted this transmission data. The data LNID
The details of the contents of 2 and LN2 are the same as those of the above-mentioned data LNID1 and LN1.

By referring to the data LNID2 and LN2, the transmission device 3 on the receiving side can identify the shuffling method or the like from the audio / video data included in the ancillary data area and the video data area.
That is, of the audio / video data, a shuffling block (every 23 lines, etc.) of a video data portion is discriminated from the data LNID2 and LN2, and deshuffling is performed for each shuffling block.

The data Flag has packet table (PT) data indicating the data amount of the ancillary data portion and the video data portion in the 0th to 3rd bits. The fourth to seventh bits include bits sb0 to sb3. These bits sb0 to sb3 are used to convey the shuffling method on the encoder side.

Data RS422-ch1, RS422-
The ch2 is used, for example, for transmission of control data or the like using the RS422 between computers (not shown) respectively connected to the data transmission devices 3 on the transmission side and the reception side. Data RS422-ch1, RS422-ch
In the 0th to 3rd bits of 2, either the upper 4 bits or the lower 4 bits of the data to be transmitted are entered,
The fourth bit contains a bit UL (Upper / Lower) that becomes 1 when the data contained in the 0th to 3rd bits is the upper 4 bits and becomes 0 when the data is the lower 4 bits. For the same reason as the valid bit V of the data RTS1 and RTS2, the logical inversion value of the fourth bit is entered in the fifth bit. Further, in the 6th bit, the data RS422-ch
1, a valid bit V indicating whether or not RS422-ch2 is valid is added.

The data VOICE contains voice data used for communication and the like. For example, the audio data can be sampled at a sampling frequency substantially equal to the sampling frequency of a PCM encoding device used for general telephone communication, and the horizontal synchronization signal ( 15.75K
Hz) 8 bits are generated, one for every two cycles. Therefore, one audio data is 1 for each cycle of the horizontal sync signal.
It will be transmitted over two generated PDU packets. In the case shown in FIG. 2, the high-order 4 bits or low-order 4 bits of the audio data are put in the 0th to 3rd bits of the data VOICE.

Further, in the fourth bit, the data RS42
Similarly to 2-ch1 and RS422-ch2, the 0th to 3rd
A bit UL indicating whether the bit data is the upper 4 bits or the lower 4 bits is inserted, and the fifth bit is
For the same reason as the valid bit V of the data RTS1 and RTS2, the logical inversion value of the fourth bit is inserted, and further, the valid bit V indicating whether or not the audio data is valid is added.

Further, the sixth and seventh bits are bits 8F1 and 8F2 (8F is a bit used for measuring the delay time given to the PDU packet by the internal circuit of the data transmission device 3 and the ATM communication line 2). (Abbreviation of 8 Frame)
Goes in. The data put in the data LNID2 and LN2 is calculated based on the delay time measured using these bits 8F1 and 8F2.

The spare data is an area reserved as a spare in case another use occurs.
Similarly to 1 and RTS2, the logic inversion value of the 6th bit is put in the 7th bit so that the value is neither 00h nor FFh. Data CRCC1, CRCC2, C
The error correction code of the preceding data area is put in each RCC3. Similar to the data RTS1 and RTS2, the logic inversion value of the sixth bit is put in the seventh bit so that the value is neither 00h nor FFh.

The word length of the ancillary data area is, for example, 69 words, and the word width is converted by the word width conversion section 410 of the word width conversion circuit 44 described above.
S / EBU data is entered. For example, the word width conversion circuit 44 converts 55 words of AES / EBU data into 8
When converted into bits, the 8-bit parallel data obtained as a result of the conversion has 68 bits and 6 bits. In such a case, in order to prevent the prohibition code (00h, FFh) from being generated, the 2-bit value 01 or 10 is put in the remaining 2 bits. Entered 01
Or 10 is the PD in the data transmission device 3 on the receiving side
It is discarded when the U packet is reproduced. In this area, the AES / EBU data is in the order of the lower word in front of the PDU packet and the upper word in back.

In the video data area, mainly video-related data is stored in the video data of 8 bits of 1 word adapted to the ATM communication line 2 from the word width of 10 bits of 1 word adapted to the SDI system. The video data is in the order of the lower byte in front of the PDU packet and the upper byte in the rear.

The ancillary data area and the video data area of the PDU packet have variable lengths, and these areas may not include valid data. In addition, the data RS422-ch1, VOICE, etc., are valid bits V
Therefore, for example, when only the valid data V of the data VIOCE is 1 and the valid data V of the other data is 0, only the data VOICE is valid and all the other data are invalid. means.

The relationship between the transmission data multiplexed in the ancillary data area and the video data area of the PDU packet and the D2 audio / video data input to or output from the VTR device 14 will be described below. FIG. 3 is a diagram for explaining the structure of D2 audio / video data. 52
The data amount of the header data of the D2 system corresponding to a system of 5 lines and 29.97 frames / sec is 16 words x 8 bits for each horizontal synchronization period (1 line), so the data rate is as shown in the following formula. It becomes 2 Mbps.

[0039]

## EQU1 ## 16 × 8 bits × 525 lines × 29.97 frames = 2 Mbps (1)

In a system of 525 lines and 29.97 frames / sec, since the number of pixels included in one line is 910 and the data per pixel is 10 bits, the data rate is as shown in the following equation. To 143 Mbp
s.

[0041]

## EQU00002 ## 910 pixels.times.10 bits.times.525 lines.times.29.97 frames = 143 Mbps (2)

However, as shown in FIG. 3, there is an unnecessary portion in the audio / video data of the D2 system, and the ancillary data (audio data), the video data (video data) and the header data shown by the diagonal lines in FIG. Only is needed for audio and video playback on the receiving side. FIG.
The data rates of the ancillary data, the video data, and the header data shown in (1) are as follows.

[0043]

## EQU00003 ## Data amount per second of ancillary data part a 21.times.10 bits.times.12 lines.times.29.97 frames.times.2 = 0.15 Mbps (3)

[0044]

## EQU00004 ## Data amount per second of ancillary data part b 376 × 10 bits × 6 lines × 29.97 frames × 2 = 1.3 Mbps (4)

[0045]

## EQU00005 ## Data amount per second of ancillary data part c 55.times.10 bits.times.254 lines.times.29.97 frames.times.2 = 8.4 Mbps (5)

[0046]

## EQU00006 ## Data amount per second of video data part d 768 × 8 bits × (254 + 253) lines × 29.97 frames = 93.3 Mbps (6)

[0047]

[Equation 7] 1 of video data section and ancillary data section
Total data amount per second e a + b + c + d = 0.15 + 1.3 + 8.4 + 93.3 = 103.2 Mbps (7)

Further, when header data is added, the data rate of the ancillary data, video data and header data becomes 105.2 Mbps as shown in the following equation.

[0049]

2 + 103.2 = 105.2 Mbps (8)

As described above, in the ancillary area of the PDU packet and the video data, an unnecessary portion is removed from the D2 audio / video data (total 143 Mbps).
Since data of 55.2 Mbps is multiplexed and an unnecessary portion is removed, there is a margin in transmission data, and it is possible to transmit voice / video data of the D2 system via an ATM communication line.

By transmitting the transmission data by multiplexing the transmission data and other data such as RTS data in the PDU packet described above, not only the transmission data is transmitted but also the transmission data of the receiving side is transmitted. Data useful for processing can also be transmitted. Further, the internal clock on the transmitting side and the internal clock on the receiving side can be synchronized via the ATM communication line 2.

Further, the data transmission device 3 on the transmission side can compensate for the transmission delay that the PDU packet receives in the ATM communication line 2 in advance, and the data transmission device 3 on the reception side can transmit the transmitted data. The data can be processed in real time. In addition to the first embodiment, the data transmission system 1 according to the present invention is configured to increase or decrease the number of data transmission devices 3 or further increase the types of data to be multiplexed in the PDU packet. Etc., various configurations can be adopted.

[0053]

[Embodiment 2] As a second embodiment of the present invention, the VTR device 14 on the transmission side compensates the transmission delay time given to the PDU packet by the ATM communication line 2 and the data transmission device 3 on the transmission and reception sides. I will explain how to do. In the second embodiment, the data transmission between the data transmission devices 3a and 3b will be described as an example. However, the data transmission devices 3a to 3a will be described.
The same applies to the processing when data transmission is performed between any of f.

FIG. 4 shows the data transmission device 3 shown in FIG.
It is a figure which shows the communication sequence between a and 3b. FIG. 5 shows the data transmission device 3 in the range a shown in FIG.
It is a figure which shows the process of a, 3b. 6 shows a bit 8F2 (bit B) transmitted from the data transmission device 3a shown in FIG. 1 and a bit 8F2 folded by the data transmission device 3a.
It is a figure which shows the time difference with (bit B). FIG. 7 shows FIG.
It is a figure explaining compensation (advance control) of the transmission delay time between the data transmission devices 3a and 3b shown in FIG.

First, the data transmission device 3a measures the transmission delay time Td. As shown in a range a of FIG. 4, PDU packets are mutually transmitted between the data transmission devices 3a and 3b. The PDU packet has bit 8F as described above.
1, 8F2 (FIG. 2) are included, and the data transmission device 3
a puts the bit B generated by the data transmission device 3a itself into the bit 8F2, multiplexes it into a PDU packet, and
The data is transmitted to the data transmission device 3b via the communication line 2.

The data transmission device 3b is connected to the ATM communication line 2
The PDU packet from the data transmission device 3a is received via the, and the PDU packet is separated into transmission data (audio / video data) and other data. Further, the data transmission device 3b uses the data 8F separated from the transmission data, other data, and the transmission data from the data transmission device 3a.
2 (bit B) is multiplexed into 8F1, bit A ′ generated by the data transmission device 3b itself is multiplexed into bit 8F2 to generate a PDU packet, and the received bit 8F2 is added to the data transmission device 3a as a new bit 8F1. It folds back to the other (flag bit processing shown in FIG. 5).

As shown in FIG. 6, the data transmission device 3a
Is the bit 8F1 folded back by the data transmission device 3b.
And the bit 8F2 transmitted to the data transmission device 3b
The time difference Td + Td 'is detected. This time difference Td + T
d'is a transmission delay time Td when the PDU packet is transmitted from the data transmission device 3a to the data transmission device 3b.
(Fig. 4) and the transmission delay time Td '(Fig. 4) when transmitting in the opposite direction. Normally, since Td = Td', time difference (Td + Td ') / 2 = transmission delay time. Td
Can be considered. The data transmission device 3 calculates the time difference (Td + Td ′) / 2 as the transmission delay time Td, controls the VTR device 14a based on the transmission delay time Td, and controls the data LNID2 and LN2 from the actual time.
(FIG. 2) is generated (delay time measurement process shown in FIG. 6).

As shown in FIG. 4, when the preceding reproduction request signal is transmitted from the data transmission device 3b to the data transmission device 3a via the ATM communication line 2, the data transmission device 3a is shown in FIG. As described above, the VTR device 14a is controlled so that the audio / video data to be processed at the time t in the data transmission device 3b is reproduced at the time t-Td, and the other data such as the generated data LNID2 and LN2 are reproduced. PD
It is multiplexed into a U packet and transmitted to the data transmission device 3b. Hereinafter, the data transmission device 3a transmits data by the advance control until the reproduction time T _VD elapses.

This advance control is performed by the data transmission device 3
This is convenient when b is connected to the sub-adjustment device of the television broadcasting station instead of the VTR device 14b and the transmission data transmitted from the data transmission device 3a in real time is used as a material for a program or editing. Advance control
In addition to audio / video data, it can be applied to transmission of various data whose processing time is fixed on the receiving side.
In addition to using the bits 8F1 and 8F2, for example, the transmission delay time Td between the data transmission devices 3a and 3b may be measured in advance, and the advance control may be performed based on the delay time Td. .

[0060]

Third Embodiment As the third embodiment of the present invention, the configuration of the data transmission devices 3a to 3f will be described below. 8 is shown in FIG.
It is a figure which shows the structure of the data transmission apparatuses 3a-3f shown in FIG. As shown in FIG. 8, each of the data transmission devices 3a to 3f is composed of a transmission unit 5 and a reception unit 6. From the reception unit 6 to the VTR devices 14a to 14f, the reception unit 6 receives the PDU packet. The separated transmission data (reception data) RVD of the D2 system is input to the VTR device 14
a to 14f are reproduced according to the control of the transmission unit 5 via the control signal VC, and are output to the transmission unit 5 as transmission data (transmission data) PVD of the D2 method. In addition, the receiving unit 6
From the transmitter 8 to the bit 8F1, which is received by the receiver 6.
8F2 is supplied.

FIG. 9 is a diagram showing the structure of the transmission unit 5 shown in FIG. As shown in FIG. 9, the transmitter 5 includes a clock generator 12, a digital video tape recorder (VT).
R) 14, RTS generation device 16, transmission device (TX) 18
And a delay processing circuit 22.

The clock generator 12 is a 14.3 MH used in the transmitter 5 using, for example, a crystal oscillator.
The internal clock 4f _{sc of} z and a sync signal SYNC corresponding to a vertical sync signal of the video signal are generated, and the VTR 14,
It is supplied to the RTS generation device 16 and the transmission device 18. V
The TR 14 records / reproduces digital audio / video data of D2 standard in synchronization with the internal clock 4f _sc , and SDI system or SDDI system (hereinafter, simply referred to as SDI system).
Output to the transmission device 18 in a 143 Mbps serial format.

The RTS generator 16 uses the ATM communication line 2
It shows the actual integer ratio of the frequency of the internal clock 4f _{sc to} the frequency of the line clock NCLK supplied from the device, and generates synchronization data RTS (Residual Time Stamp) used for establishing synchronization with the transmission units 5 and 30. The delay processing circuit 22 includes the bits 8F1, 8 input from the receiving unit 6.
The delay time measurement process shown in FIG. 5 is performed based on F2.

FIG. 10 is a diagram showing the structure of the transmission device 18 shown in FIG. As shown in FIG.
Is composed of a first block 180 which operates in synchronization with the internal clock 4f _sc and a second block 210 which operates in synchronization with the line clock NCLK.

The first block 180 includes a serial / parallel conversion circuit (S / P circuit) 182, a first switch circuit (SW1) 184, and a second switch circuit (SW2) 1.
86, rounding circuit 188, shuffling circuit 1
90, a first FIFO circuit 192, a word width conversion circuit (10 → 8) 194, a second FIFO circuit 196, a timing generation circuit a200, a timing generation circuit b20.
2, control circuit 204 and reference signal generation circuit 2
It is composed of 06. The second block 210 includes a multiplexing circuit (MUX) 212, a third FIFO circuit 214, a control circuit 216, and a timing generation circuit c21.
8.

In the first block 180, the timing generation circuit a200 determines that the other data transmission devices 3a to 3f.
When the data is not transmitted from (default), the video data (black burst data) corresponding to the black burst is generated at the operation timing based on the data RTS having the value. The reference signal generation circuit 206 is a circuit outside the first block 180, generates black burst data similarly to the timing generation circuit a200, and outputs it to the terminal a of the switch circuit 184.

The S / P circuit 182 converts the 1-bit serial format SDI transmission data input from the VTR device 14 into a 10-bit parallel format and outputs it to the terminal b of the switch circuit 184. Switch circuit 18
Reference numeral 4 denotes a reference signal generation circuit 206 which selects the terminal b side to output the output data of the S / P circuit 182 when the transmitting unit 5 transmits data, and selects the terminal a side otherwise. Switch circuit 1 to output black burst data
Output to 86.

The switch circuit 186 is the switch circuit 18
4 selects the video data portion of the output data (transmission data) of the S / P circuit 182 selected from the S / P circuit 182 of the audio / video data of the D2 system shown in FIG.
It outputs to 88, selects an ancillary data part, and outputs to the word width conversion circuit 194. The rounding circuit 188 converts the data (video data) corresponding to the video data portion shown in FIG. 3 into 8-bit parallel format data (rounds) and sends the data to the shuffling circuit 190. Output. The control circuit 204 handles the header data shown in FIG.

The shuffling circuit 190 receives the 8-bit parallel signal input from the rounding circuit 188,
When a data error occurs in the ATM communication line 2, the data is rearranged in an order that facilitates interpolation and is output to the FIFO circuit 192. The word width conversion circuit 194 converts the data (voice data) corresponding to the ancillary data portion input from the switch circuit 186 shown in FIG. 3 into an 8-bit parallel format, and outputs it to the FIFO circuit 196.

The FIFO circuits 192 and 194 respectively read the data in synchronization with the internal clock 4f _sc and sequentially output the data in synchronization with the line clock 4f _sc .
The data is transferred from the block 180 to the second block 210. The control circuits 204 and 216 monitor the addresses to which data is written and the addresses from which data is read in the FIFO circuits 192 and 194, respectively, and control these addresses. Furthermore, the first block 1
80 is data L based on bits 8F1, 8F2, etc.
N1, LNID1, LN2, LNID2 and data F
lag (FIG. 2) is generated and output to the second block 210.

In the second block 210, the timing generation circuit c218 controls the operation timing of the block 210 based on the line clock NCLK. Data R from the inspection signal applying circuit 16 is sent to the multiplexing circuit 212.
TS is input, and data data LN1, LNID1, LN2, LNID2, Flag are input from the first block 180.
Is entered. The multiplexing circuit 212 multiplexes these data with the audio data and the video data input from the FIFO circuits 192 and 194, and the FIFO circuit 21.
4 is output.

The CRCC addition circuit 213 is for each data CR
The CC is calculated, added, and output to the FIFO circuit 214. The FIFO circuit 214 buffers the output data of the multiplexing circuit 212 and outputs it as transmission data TXD to the ATM communication line 2. As shown in the figure, bits 8F1 and 8F2 from the delay processing circuit 22 are further added to the output data of the FIFO circuit 214 to form the transmission data TXD.

FIG. 11 shows the delay processing circuit 22 shown in FIG.
It is a figure which shows the structure of. As shown in FIG. 11, the delay processing circuit 22 includes a measurement bit generation circuit 220 and a time difference detection circuit. Measurement bit generation circuit 220
Generates the bit 8F2 shown in FIG. 2 and returns the bit 8F2 received by the receiving unit 6 to the bit 8F1. As shown in FIG. 6, the time difference detection circuit 222 detects the time difference between the bit 8F1 received by the receiver 6 and the bit 8F2 generated by the measurement bit generation circuit 220, and calculates the transmission delay time Td, VTR device 14 via control signal VC
To perform advance control.

FIG. 12 is a diagram showing the structure of the receiving unit 6 shown in FIG. As shown in FIG. 12, the receiver 6 includes a receiver (RX) 32, a VTR 34, and a clock controller 36.
And a clock generator 38, which receives the PDU packet transmitted from the data transmission device 3 on the transmission side, and based on the synchronous data RTS and the line clock NCLK, the internal clock 4 of the data transmission device 3 on the transmission side.
reproduces the internal clock 4f _sc synchronized with f _sc, and records the separated audio and video data (transmission data) from the PDU packet.

FIG. 13 is a diagram showing the structure of the receiving device 32 shown in FIG. As shown in FIG. 13, the receiving device 3
2 comprises a first block 320 that operates in synchronization with the line clock NCLK and a second block 350 that operates in synchronization with the internal clock 4f _sc , and is a PDU packet received as reception data RXD from the ATM communication line 2. To separate each data and the transmission data, and the transmission data among the separated data is V as the reception data RVD.
It outputs to the TR device 14, and outputs bits 8F1 and 8F2 to the delay processing circuit 22.

The first block 320 includes an input data control circuit 322, a first register circuit 324, a CRCC calculation circuit 326, adder circuits 328a and 328b, a first memory circuit 330, a second memory circuit 332 and a second block. Register circuit 334, third register circuit 336, control circuit 338, and timing generating circuit d340.

The second block 350 includes an output data control circuit 352, a fourth register 354, a first reference signal generation circuit 356, a deshuffling circuit 358, a concealment circuit 360, a first error correction circuit 362 and a FIFO circuit 364. , A second error correction circuit 366, a switch circuit 368, a timing generation circuit e370, a second reference signal generation circuit 372, a switch circuit 374, a parallel / serial conversion circuit (P / S circuit) 376, and a control circuit 378. It

The PDU packet received by the receiving device 32 from the ATM communication line 2 includes the input data control circuit 322, the first register circuit 324 and the CRCC calculation circuit 326.
Is input to The first register circuit 324 converts the received 8-bit parallel format PDU packet into a 64-bit parallel format. The CRCC calculation circuit 326 is
The calculation processing relating to each data CRCC (FIG. 2) included in the PDU packet is performed, and the calculation result is output to the addition circuit 328a. The CRCC calculation circuit 326 converts the transmission data ^Xn + ^Xn-1 + ^Xn-2 + ... + X + 1 into G (X).
= X ¹⁴ + X ² + X + 1, an error is detected when the remainder is other than 0, and the calculation result is set to the logical value 1 and output.

The input data control circuit 322 determines, based on each data included in the input PDU packet, write flag data (a; 8-bit parallel data in which all bits are logical values 0, and each bit is a PDU packet). (Corresponding to 1 byte of) is generated and output to the addition circuit 328b. The adder circuit 328b is the first register circuit 3
Write flag data is added to the output data of 24
Output in bit width.

Further, the input data control circuit 322 generates read flag data (b) of 9 bits × 8 words. After reading the read flag data, the input data control circuit 322 sets only the parity bit to the logical value 1 and all the other bits to the logical value 0, and sets the number of lines (525) ×
The PDU packet is written into the memory circuit 332 having an address space of packet length × 9 bits. The reason why the input data control circuit 322 performs the bit operation of the read flag data in this way is to judge that the necessary data has not arrived when the read flag data of the read data has the logical value 1. Note that the read flag data has a logical value of 0 if it has been written before reading.

The register circuit 334 collects a total of 8 pieces of 9-bit data, that is, the received data 8 bits and the flag data 1 bit corresponding to the received data, as 72-bit data in synchronization with the line clock NCLK from the memory circuit 332. The data is read and output to the register 354 in synchronization with the internal clock 4f _sc .

The input data control circuit 322 also outputs write flag data to the adder circuit 328a (c).
The adder circuit 328 a adds write flag data to the calculation result of the CRCC calculation circuit 326 and returns it to the input data control circuit 322. The input data control circuit 322 outputs the calculation result with the write flag data added to the memory circuit 330.
(D).

The register circuit 336 is the memory circuit 332.
The addition result of the addition circuit 328a stored in the internal clock 4 is read in synchronization with the line clock NCLK.
Output in synchronization with f _sc . Control circuit 338, 3
78 is a control circuit 204, 21 of the transmitter 18.
6 manages the write address and the read address of the register circuits 334 and 336 as in the case of FIG.

In the second block 350, the timing generation circuit e370 controls the operation timing of each part of the second block 350 based on the internal clock 4f _sc . The reference signal generation circuit 372 generates and outputs a reference signal. The reference signal generation circuit 356 generates a reference signal and outputs it to the terminal a of the switch circuit 374. The reference signal generated by the reference signal generation circuits 372 and 356 is a signal that does not contain video data and ancillary data and that makes the screen black after reproduction.

The data output from the register circuit 334 is input to the register 354. On the other hand, the data output from the register circuit 336 is the output data control circuit 35.
2 is input. The register circuit 354 transfers each word of the data corresponding to the ancillary data section shown in FIG. 3 (voice data multiplexed in the ancillary area shown in FIG. 2) to the lower 2 bits and its parity bit (a), It is decomposed into the upper 8 bits (b) and its parity bit and output to the input data control circuit 322.

The output data control circuit 352 sends to the deshuffling circuit 358 data corresponding to the video data section shown in FIG. 3 (video data multiplexed in the video data area shown in FIG. 2) and its parity. The error correction circuit 36 outputs (c) the data corresponding to the ancillary data section shown in FIG. 3 (voice data multiplexed in the ancillary data area shown in FIG. 2) and its parity.
2 is output (d) to the data RS42 shown in FIG.
2-ch1, RS422-ch2, VOICE, RTS
Error correction circuit 36
It outputs to 6 (e). That is, the output data control circuit 352 also serves as a separation circuit that separates the audio data and the video data from the PDU packet and the data RS422-ch1 and the like.

By this processing, the output data control circuit 352 a: 8-bit data (1) + flag data (2), b: 2-bit (3) + flag data (4), output of register 2 = CRCC 1 bit Of each data of the + flag data (6), (2), (4), (5),
When any one of (6) has a logical value of 1, a logical value of 1 is newly output as flag data. That is, the output data control circuit 352 performs conversion with a flag of 2 words width of a; (reception data 8 bits + flag data 1 bit) into (ancillary data 10 bits + flag data 1 bit).

The deshuffling circuit 358 performs a process corresponding to the shuffling circuit 190 shown in FIG. 10 based on the data LNID2 and LN2 included in the input data, restores the original order, and sends it to the concealment circuit 360. Output. The concealment circuit 360 interpolates the data of the pixel in which the data error has occurred, for example, with the surrounding pixels by a method such as interpolation, and the switch circuit 37
4 to terminal b.

The error correction circuit 362 receives the input error correction circuit 362, performs error correction on the input audio data, and outputs it to the FIFO circuit 364. The FIFO circuit 364 outputs the video data output from the concealment circuit 360 and the error correction circuit 362 output from the error correction circuit 362 to the terminal c of the switch circuit 374 at the same timing.

The switch circuit 374 has terminals a to a, respectively.
The reference signal from the reference signal generation circuit 356, the output data of the concealment circuit 360, and the FIFO
One of the output signals of the circuit 364 is selected in an order suitable for the audio / video data of the D2 system in the SDI system, and is output to the P / S circuit 376. P / S circuit 3
Reference numeral 76 converts the data input from the switch circuit 374 into serial format data, and outputs the data to the VTR device 14 in synchronization with the internal clock 4f _sc .

The error correction circuit 366 performs error correction on the inputted data such as RS422-ch1 and outputs it to the switch circuit 368. The switch circuit 368 separates the error-corrected data and outputs the data RS422-ch1, RS422-ch2, respectively.
Output as VOICE, RTS and preliminary data.

VTR device 14 (FIG. 12) Internal clock 4
The audio / video data RVD input from the P / S conversion circuit 330 is recorded in synchronization with f _sc . The clock generation device 38 is, for example, a voltage controlled oscillation circuit having a crystal oscillation circuit, generates the internal clock 4f _sc having a frequency according to the control of the clock control device 36 via the clock control signal CC, and transmits the internal clock 4f _sc . Supply to each component. The clock control device 36 generates a clock control signal CC based on the synchronization data RTS input from the reception device 32,
The clock generator 3 is supplied via this clock control signal CC.
8 controls the frequency of the internal clock 4f _sc for generating the internal clock 4f _sc of the transmission device 30 is synchronized with the internal clock 4f _sc of the transmission apparatus 10, further, a synchronization signal SYNC, such as horizontal and vertical synchronization signals Occurring and VTR
It is supplied to the device 14 or the like.

Hereinafter, referring again to FIG. 1, the data transmission will be performed by taking the case of transmitting data between the data transmission devices 3a and 3b using the transmission unit 5 and the reception unit 6 shown in the third embodiment as an example. The operation of the transmission system 1 will be described. In the data transmission device 3a, the VTR device 14a of the transmission unit 5 is
Plays D2 audio and video data, 143Mbps
Transmitter 18 as serial audio / video data PVD
Output to

On the other hand, the RTS generator 16 has the internal clock 4f _sc generated by the clock generator 12 and A
Based on the line clock NCLK supplied by the TM communication line 2, synchronization data RT indicating how many cycles the internal clock 4f _sc enters during the 1188 periods of the line clock NCLK.
S is generated and sequentially output to the transmission device 18.

The transmission device 18 multiplexes the transmission data PVD and the synchronization data RTS into the PDU packet shown in FIG. 2, and transmits the data transmission device 3b via the ATM communication line 2.
Send to Further, the transmission device 18 performs the advance control shown in FIG. 7 on the VTR device 14a as necessary. The ATM communication line 2 is a data transmission device 3
The ATM cell transmitted from a is transmitted to the data transmission device 3b, and the line clock NCLK is supplied to the data transmission device 3b.

In the data transmission device 3b, the PDU packet transmitted from the data transmission device 3a is received by the reception device 32 of the reception unit 6. The receiving device 32 is
The reception data RVD corresponding to the transmission data PVD of the reception unit 6 of the data transmission device 3a is output to the VTR 14b, and the VTR 14b records this.

The clock controller 36 controls the synchronization data RT
S, the frequency of the internal clock 4f _sc generated by the clock generator 38 based on the internal clock 4f _sc supplied from the clock generator 38 and the line clock NCLK supplied from the ATM communication line 2 The clock control signal CC that is synchronized with the internal clock 4f _sc in the receiving unit 6 of 3b is generated and output to the clock generator 38. The clock generator 38 uses the internal clock signal 4 at a frequency according to the clock control signal CC.
f _sc is generated and supplied to each part of the reception unit 6 of the data transmission device 3b.

As described above, according to the data transmission system 1 of the present invention, the SDI system which is widely used as the infrastructure in the television broadcasting station can be used as the interface of the VTR 14, so that the existing system can be used. The equipment can be easily connected to the ATM communication line.

The circuit configurations and the like of the transmitting unit 5 and the receiving unit 6 shown in the above embodiments are merely examples, and can be replaced with circuits or the like capable of realizing equivalent functions. Further, although the VTR device has been illustrated as the device connected to the transmission part 5 and the reception part 6, the invention is not limited to this, and for example, an editing device for inputting / outputting data by the SDI system, a relay device or a transmission facility is connected You may.

Also, the PDU packet shown in FIG. 2 is an example, and the present invention can be applied to a transmission method using a transmission packet of another format. Further, the data transmission system 1, the transmitter 5 and the receiver 6 according to the present invention are
In addition to video data, it can be applied to any of these data, or data for information processing.

[0101]

Fourth Embodiment A fourth embodiment will be described below. Second embodiment (FIGS. 4 to 7) and third embodiment (FIGS. 8 to 1)
In 3), the bit 8F2 transmitted from the data transmission device 3a on the transmission side is returned by the data transmission device 3b on the reception side as the bit 8F1 so that the ATM communication line 2
And so on. However, according to this method, the transmission delay time Td from the data transmission device 3a to the data transmission device 3b (FIG. 4).
If the transmission delay time Td 'in the opposite direction is different from that in the opposite direction, accurate advance control cannot be performed.

In the data transmission system 1 shown in the second and third embodiments, the data transmission device 3a only transmits the bit 8F2, that is, operates as a master side, and the data transmission device 3b is operated. The data transmission device 3a, 3 operates because the bit 8F2 received by is simply folded back as the bit 8F1 and so to speak as a slave side.
The processing contents of b are not the same.

In the fourth embodiment, the delay processing circuit 2
2 and the operation of the VTR device 14 and the like are changed, and even when the transmission delay time is Td ≠ Td ′, accurate advance control is possible, and moreover, the data transmission devices 3a and 3b.
The data transmission system 1 which has the same processing contents regarding the transmission delay time measurement and whose transmission delay time is easily measured will be described by way of an example in which the transmission data is transmitted from the data transmission device 3b to the data transmission device 3a. To do.

FIG. 14 is a diagram showing the configuration of the VTR device 14b (FIG. 1) in the fourth embodiment. In addition, VTR
The devices 14a and 14c to 14f have the same configuration. FIG.
As shown in FIG. 5, the VTR device 14a includes a selection circuit (SEL) 140, a control circuit 142, and a recording / reproducing device 144, respectively.

The delay processing circuit 24 is used for the data transmission device 3b.
Of the VTR device 1 which is used in place of the delay processing circuit 22 shown in FIG.
4 is output. The control circuit 142 uses, for example, the data RS422-ch1 and RS422-ch2 shown in FIG.
Alternatively, based on the operation data input from the operation terminal device 146, the recording / reproducing device 144 and the control circuit 142.
Control.

Specifically, the control circuit 142 controls the data R
When S422-ch1 or the like is for reproducing audio / video data based on the reference signal (bit 8F2) transmitted from the data transmission device 3a, the selection circuit 140 selects the terminal a. , The reference signal input from the delay processing circuit 24 is controlled to be supplied to the recording / reproducing device 144. In other cases, the terminal b is selected to record / reproduce the synchronization signal SYNC generated by the clock generating device 38. The device 144 is controlled to input.

FIG. 15 shows the VTR device 14 shown in FIG.
It is a figure which shows the communication sequence between the data transmission apparatuses 3a and 3b (FIG. 1) which applied a-14f. FIG.
The delay processing circuit 24 and the VTR device 14 shown in FIG.
FIG. 9A is a timing chart showing transmission delays that occur in each signal when a to 14f are used, in which (A) shows a reference signal b corresponding to a vertical synchronization signal or the like used inside the data transmission device 3b, and (B) ) Indicates the reference signal b ″ ′ (FIG. 15) transmitted from the data transmission device 3b to the data transmission device 3a as the bit 8F2 shown in FIG. 2, and (C) indicates the reference signal b received by the data transmission device 3b. Indicates "(D)
Indicates the phase of the transmission data TXDb output from the VTR device 14b to the data transmission device 3b, and (E) indicates the reception data RXDa output from the data transmission device 3a to the VTR device 14a.

As shown in FIG. 15, the data transmission device 3a.
First, bit 8F2 of the PDU packet shown in FIG.
For example, the reference signal a in the data transmission device 3a is
Are multiplexed and output to the data transmission device 3b via the ATM communication line 2. The data transmission device 3b is a PDU
Extract bit 8F2 from the packet and
The reference signal generated by the data transmission device 3b itself is transmitted to the data transmission device 3a as a new bit 8F2.

As described above, the received bit 8F2 is returned as the bit 8F1, and the reference signal generated by itself is transmitted to the other side as the new bit 8F2, whereby the processing relating to the bits 8F1 and 8F1 of the data transmission devices 3a and 3b is performed. Will be the same. If data transmission / reception has already been performed before this, the first data transmission / reception in FIG. 15 is unnecessary.

As shown in FIG. 6, the delay processing circuit 22 of the transmission section 5 of the data transmission device 3a, based on the bit 8F1 folded back from the data transmission device 3b and the generated reference signal (bit 8F2), as shown in FIG. Time difference Td + T
Detect d '. Delay processing circuit 2 of data transmission device 3a
2 generates the reference signal b ″ ′ shown in FIG. 16B at a timing that is temporally ahead of the reference signal inside the data transmission device 3a by the time difference Td + Td ′ (= T _ad ; FIG. 16). Furthermore, the delay processing circuit 22 outputs the received bit 8F2 to the bit 8F1 of the new PDU packet and the reference signal b ″ ′ as the data to be multiplexed with the bit 8F2 of the PDU packet to the transmission unit 5.

The transmission section 5 of the data transmission device 3a receives the reference signal b "'(bit 8F) input from the delay processing circuit 22.
2) and transmission data are multiplexed into a PDU packet and output to the data transmission device 3b. Data transmission device 3b
Reference signal b "'transmitted as bit 8F2 to
Receives the transmission delay T _d1 by the ATM communication line 2 and
6 (C) is received by the transmitter 5 of the data transmission device 3b at the timing of the reference signal b ″.

The transmission unit 5 of the data transmission device 3b uses the PDU
The reference signal (bit 8F2) is separated from the packet and output to the delay processing circuit 24. The delay processing circuit 24 is
The reference signal (bit 8F2) supplied from the receiver 6 is supplied to the VTR device 14b as the control signal VC. Also,
The delay processing circuit 24 performs the bit operation related to the bits 8F1 and 8F2 described above. The VTR device 14b reproduces the audio / video data at the timing indicated by the reference signal (bit 8F2) input from the delay processing circuit 24, and supplies it as the transmission data PVD to the transmission unit 5 of the data transmission device 3b.

The transmission data PVD is multiplexed into a PDU packet, and as shown in FIG. 16D, the transmission data is further received by the transmission delay T _d2 inside the transmission unit 5 to become the transmission data TXDb.
The data is transmitted to the data transmission device 3a via the ATM communication line 2. The transmission delay T _d2 is mainly due to the shuffling process and the like. Data transmission device 3b to ATM communication line 2
The PDU packet sent to the receiver is subjected to the transmission delay T _d3 as shown in FIG. 16 (E), and is received by the receiving unit 6 of the data transmission device 3a as the reception data RXDa. FIG.
As can be seen by comparing (A) and (E), the reference signal b inside the data transmission device 3a and the reception data RXDa are synchronized.

In this way, the delay processing circuit 24 and the VT
By configuring the R device 14b, the transmission data processed at the time t in the data transmission device 3a is transmitted by the data transmission device 3b by the data transmission device 3b in the same manner as in the second and third embodiments. It is possible to compensate for the delay time, transmit the data, and reach the data transmission device 3 at time t. Further, even when the transmission delay in the direction from the data transmission device 3a to the data transmission device 3b and the transmission delay in the opposite direction are different, the received data R can be accurately received at the processing timing of the data transmission device 3a.
XDa can be synchronized. In the fourth embodiment, the data transmission between the data transmission devices 3a and 3b has been described, but the same advance control can be performed between any two of the data transmission devices 3a to 3f.

[0115]

[Fifth Embodiment] A fifth embodiment of the present invention will be described below.
FIG. 17 is a diagram showing the configuration of the data transmission system 7 according to the present invention in the fifth embodiment. As shown in FIG. 17, the data transmission system 7 includes data transmission devices 3a to 3a.
c is connected in a daisy chain form so as to transmit data to only one other data transmission device 3 via the ATM communication line 2, and bit c is used for advance control. In addition to 8F1 and 8F2, bit 0 of the spare data of the PDU packet shown in FIG. 2 (hereinafter referred to as spare 0) is used.

In the fifth embodiment, each of the data transmission devices 3a and 3b uses the bits 8F1 and 8F2 and the spare 0 to transmit the reference data and the transmission delay, as in the case of the fourth embodiment. Take time measurements. FIG.
As shown in FIG. 3, the data transmission device 3a generates a reference signal A synchronized with the internal synchronization signal and operates as a master, and the data transmission devices 3b and 3c are multiplexed in the bit 8F1 of the received PDU packet. Reference signal C ',
In synchronization with A ′, independent reference signals B and C are generated.

The data transmission devices 3a to 3c receive the reference signals generated by the data transmission devices 3a to 3c themselves from the PDs.
Received PDU multiplexed into bit 8F1 of U packet
Reference signals from other data transmission devices 3 included in bits 8F1 and 8F2 of the packet are shifted to bit 8F2 and spare 0, respectively. In this way, in the data transmission system 7, the data transmission devices 3a to 3c all perform the same bit processing to perform the reference signal folding processing.

The data transmission device 3a receives the generated reference signal A and the reference signal A "'from the returned data transmission device 3b.
Based on the above, the transmission delay time between the data transmission device 3a and the data transmission device 3b via the data transmission device 3c can be measured, and the transmission delay time between the data transmission device 3a and the data transmission device 3c can be measured. Time can be measured.

Similarly, the data transmission device 3b passes the data transmission device 3c between the data transmission device 3a and the data transmission device 3b based on the generated reference signal B and the returned reference signal B "'. It is possible to measure the transmission delay time, and similarly, the data transmission device 3c determines between the data transmission device 3a and the data transmission device 3c based on the generated reference signal C and the returned reference signal C "'. The transmission delay time via the data transmission device 3b can be measured.

Incidentally, FIG. 17 shows the data transmission system 7
Although the case where the number of the data transmission devices 3 configuring the above is three is illustrated, the data transmission system 7 can be configured by further increasing the number of the data transmission devices 3 as long as the data transmission devices 3 are connected in the daisy chain format. However, when the number of units is increased, it is necessary to increase the number of data bits used for advance control according to the number of units. In addition, the data transmission devices 3a to
Any of 3c may be the master.

Further, in the data transmission system 7 in the fifth embodiment, the data transmission device 3a is used as a master, but the master in the fifth embodiment uses the reference as to the generation of the reference signal of the data transmission devices 3a to 3c. The bit operation itself in each of the data transmission devices 3a to 3c is the same.

[0122]

As described above, according to the data transmission method and apparatus of the present invention, it is possible to perform data transmission between, for example, an SDI type transmission apparatus and an ATM type transmission apparatus. . Further, according to the data transmission method and the device thereof according to the present invention, the AT is used as a flag in the transmission packet used by the user.
It is possible to convert 10-bit word width data of the SDI system to 8-bit word width data of the ATM system without generating a data pattern that is prohibited from being transmitted on the M communication line.

Further, according to the data transmission method and the apparatus therefor of the present invention, the audio / video data is generated earlier by the transmission delay time in advance, the transmission delay in the communication line is compensated, and the video received by the receiving side is compensated.・ Voice data can be processed in real time. Further, according to the data transmission method and the apparatus therefor of the present invention, together with the video / audio data, the control data used for editing the video / audio data, or between the user on the transmitting side and the user on the receiving side is used. It is possible to transmit communication voice data and the like.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data transmission system according to the present invention in a first embodiment.

FIG. 2 is a diagram showing a configuration of a transmission packet (PDU packet) mutually transmitted by the data transmission device shown in FIG. 1 through an ATM communication line.

FIG. 3 is a diagram illustrating a configuration of audio / video data of D2 system.

FIG. 4 is a diagram showing a communication sequence between the data transmission devices shown in FIG. 1 in the second embodiment.

5 is a diagram showing a process of the data transmission device in a range a shown in FIG.

6 is a diagram showing a time difference between a bit 8F2 transmitted from the data transmission device (3a) shown in FIG. 1 and a bit 8F2 returned by the data transmission device (3b).

7 is a diagram illustrating compensation (advance control) of a transmission delay time between the data transmission devices illustrated in FIG.

FIG. 8 is a diagram showing a configuration of the data transmission device shown in FIG. 1 in a third embodiment.

9 is a diagram showing a configuration of a transmission unit shown in FIG.

FIG. 10 is a diagram showing a configuration of the transmission device shown in FIG. 9.

11 is a diagram showing a configuration of a delay processing circuit shown in FIG.

12 is a diagram showing a configuration of a receiving unit shown in FIG.

FIG. 13 is a diagram showing a configuration of the receiving device shown in FIG.

FIG. 14 is a diagram showing a configuration of a VTR device (FIG. 1) in a fourth embodiment.

15 is a diagram showing a communication sequence between data transmission devices to which the VTR device shown in FIG. 14 is applied.

16 is a timing chart showing a transmission delay that occurs in each signal when the delay processing circuit and the VTR device shown in FIG. 14 are used.

FIG. 17 is a diagram showing the configuration of a data transmission system according to the present invention in a fifth embodiment.

[Explanation of symbols]

1 ... Data transmission system, 2 ... ATM communication line, 3, 3
a to 3f ... Data transmission devices 3, 14, 14a to 14f ...
VTR device, 140 ... Selection circuit, 142 ... Recording / reproducing device, 144 ... Recording / reproducing device, 5 ... Transmitting unit, 12 ... Clock generating device, 16 ... RTS generating device, 18 ... Transmitting device,
180 ... First block, 182 ... S / P circuit, 184
... switch circuit, 186 ... switch circuit, 188 ... rounding circuit, 190 ... shuffling circuit, 192 ...
FIFO circuit, 194 ... Word width conversion circuit, 196 ... F
IFO circuit, 200 ... Timing generation circuit a, 202 ...
Timing generation circuit b, 204 ... Control circuit, 2
06 ... Reference signal generating circuit, 210 ... Second block, 2
12 ... Multiplexing circuit, 214 ... FIFO circuit, 216 ... Control circuit, 218 ... Timing generation circuit c, 22
... delay processing circuit, 24 ... delay processing circuit, 220 ... measurement bit generating circuit, 222 ... delay processing circuit, 6 ... receiving section,
32 ... Receiving device, 320 ... First block, 322 ... Input data control circuit, 324 ... Register circuit, 326 ... C
RCC calculation circuit, 328 ... Addition circuit, 330 ... Memory circuit, 332 ... Memory circuit, 334 ... Register circuit, 33
6 ... Register circuit, 338 ... Control circuit, 340
... Timing generation circuit d, 350 ... Second block, 3
52 ... Output data control circuit, 354 ... Register circuit, 3
56 ... Reference signal generation circuit, 358 ... Deshuffling circuit, 360 ... Conceal circuit, 362 ... Error correction circuit, 364 ... FIFO circuit, 366 ... Error correction circuit,
368 ... Switch circuit, 370 ... Timing generation circuit e, 372 ... Reference signal generation circuit, 374 ... Switch circuit, 376 ... P / S circuit, 378 ... Control circuit,
36 ... Clock control device, 38 ... Clock generation device

Claims (7)

[Claims] 1. An asynchronous transmission mode (ATM) communication line for supplying audio data and video data of the D2 system, or any one of them as transmission data to be transmitted, and using a predetermined transmission packet to supply a predetermined clock. A data transmission method for transmitting via a predetermined communication line such as, for example, converting the transmission data into a word width suitable for the communication line, shuffling, and transmitting on the transmission side to the line clock supplied by the communication line. Sync data that indicates the operation timing and that is used to match the operation timing of the reception side with the operation timing of the transmission side, identification data that is used to identify the transmission data, and the transmission data that is included in the same transmission packet Data amount data indicating the data amount of the data and shuffling method indicating the shuffling method for the transmission data. Data, predetermined control data transmitted between the transmitting side and the receiving side, and measurement data used for measuring a transmission delay time generated between the transmitting side and the receiving side, A data transmission method for multiplexing call data used for a call between the transmission side and the reception side and the shuffled transmission data into the predetermined transmission packet for transmission. 2. When the communication line has a prohibition code for prohibiting transmission, each of the data included in the transmission packet, which may have the prohibition code, is combined with these data to prohibit the transmission. The data transmission method according to claim 1, wherein additional data that does not generate a code is added. 3. A transmission delay time that is set by the receiving side to process the transmission data, and the transmission data included in the transmission packet is received from the transmitting side to the receiving side. The data transmission method according to claim 1, wherein the data transmission is generated earlier than the actual time. 4. The identification data is transmitted at the transmitting side.
The data transmission method according to claim 3, wherein the transmission time includes delay time data indicating a time when the transmission time is generated earlier than an actual time. 5. The receiving side receives the transmission packet from the communication line, and from the received transmission packet, the transmission data, the synchronization data, the identification data, the data amount data, and Shuffling data, the control data,
The measurement data and the call data are separated, the transmission data separated based on the shuffling data is deshuffled, and the deshuffling shifter the transmission data is converted into the original word width. Data transmission method. 6. An object of transmission from a first data transmission device via a predetermined communication line such as an ATM communication line,
Data transmission device for transmitting the transmission data such that predetermined transmission data such as audio / video data whose processing time is determined by the second data transmission device reaches the processing time of the second data transmission device. At least the first data transmission device is configured to transmit the transmission data that is earlier than the actual time by a transmission delay time that occurs between the first data transmission device and the second data transmission device. Transmission data generating means, word width conversion means for converting the transmission data into a word width suitable for the communication line, shuffling means for shuffling the generated transmission data, and shuffled transmission data And the operation timing of the first data transmission device with respect to the line clock supplied by the communication line. The synchronization data used to match the timing of the first data transmission device with the synchronization data, the identification data used to identify the transmission data, and the data amount of the transmission data included in the same transmission packet are shown. Data amount data, shuffling data indicating a shuffling method for the transmission data, predetermined control data transmitted between the first data transmission device and the second data transmission device, and the first data transmission device. Between the first data transmission device and the second data transmission device, and the measurement data used to measure the transmission delay time generated between the second data transmission device and the second data transmission device. Multiplexing the call data used for the call, and a multiplexing means for generating a predetermined transmission packet, and the generated transmission packet for the communication time. Data transmission device having a transmitting means for transmitting to said second data transmission device via. 7. The second data transmission device comprises: receiving means for receiving the transmission packet from the communication line; and the transmission data, the synchronization data, and the identification data from the received transmission packet. The data amount data, the shuffling data, the control data,
Deshuffling means for separating the measurement data and the call data, and deshuffling the transmission data separated based on the shuffling data, and a deshuffling shifter Word width for converting the transmission data to the original word width The data transmission device according to claim 6, further comprising an inverse conversion unit.