JPH098811A - Word width conversion device - Google Patents

Abstract

PURPOSE: To convert data whose word width is 10 bits in an SMPTE-259M (SDI) system into data whose word width is eight bits, which fits to an ATM system. CONSTITUTION: A FIFO circuit 414 sequentially stores highest eight bits for one sample (three words) of AES/EBU data, which are included in 10 bits parallel data S180. A FIFO circuit 416 stores the lowest two bits of AES/EBU data. DFF circuits 4181 -4183 hold lowest two bits outputted from the FIFO circuit 416 and add two dummy bits of 01 and the like. A selector circuit 420 multiplexes data stored in the FIFO circuit 414 with data stored in the DFF circuits 4181 -4183 and the added dummy bits, and generates eight bits parallel data S40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial digital interface (SDI; SMPTE-259) having a word width of 10 bits during transmission methods having different word widths.
M) and an asynchronous transmission mode with a word width of 8 bits (AT
The present invention relates to a word width conversion device that changes the word width so as to conform to each method when data is transmitted to and from M).

[0002]

2. Description of the Related Art Conventionally, SMPTE (SoP) has been used as an infrastructure for transmitting digital audio / video data in a television broadcasting station or the like.
serial Digital Interface (SDI; Serial Digital I) defined as SMPTE-295M in the Society of Motion and Television Engineering
nterface) type transmission device is used. further,
A serial digital data interface (SDDI; Serial Digital Data Interface) that improves the SDI system while maintaining compatibility and enables variable length data and multiple types of data to be transmitted in one transmission packet.
rface) method is also proposed. In addition, recently, an asynchronous transmission mode (AT
The M) method has been put to practical use.

[0003]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention Between a television broadcasting station and the like, an SDI system or an SD system is used via an ATM communication line.
There is a request to send and receive DI audio / video data. However, the transmission packet of the above-mentioned SDI system has a 1-word 10-bit structure, and as it is, it is not suitable for an ATM communication line for transmission using an ATM cell having a 1-word 8-bit structure. Further, in the ATM communication line, there is a problem that the data to be transmitted should not have a data pattern of FFh, 00h, 00h.

The present invention has been made in view of the above-mentioned problems of the prior art. The transmission method has different word widths of data, for example, an SDI type transmission apparatus having a word width of 10 bits and a word width of 8 bits. It is an object of the present invention to provide a word width conversion device capable of changing the word width so that the data to be transmitted can be adapted to each system when data is transmitted to and from the ATM system transmission device. . Further, the present invention allows the SDI to be generated without causing a data pattern prohibited in the ATM communication line.
It is an object of the present invention to provide a word width conversion device capable of converting 10-bit data having a word width of the system into 8-bit data having an ATM method.

[0005]

In order to achieve the above object, a word width conversion apparatus according to the present invention is configured such that one sample is a predetermined data consisting of k words each having a word width of m bits. A word width conversion device for converting data having a word width of n bits (k, m, n is an integer, m> n), and a predetermined one of the bits included in each word of the predetermined data for one sample. First word width converting means for storing k first parts each including n, and m− bits other than the predetermined n of the bits included in each word of the predetermined data for one sample. From the k second parts including n, the second parts are respectively [n /
(M−n)] (where, [X] represents an integer not exceeding X) and the second data including each of them is [k / [n / (m
-N)]] (when k / [n / (m-n)] is an integer) or [k / [n / (m-n)]] + 1 (k /
[n / (m−n)] is not an integer) second word width conversion means to be generated and stored, the first portion stored in the first word width conversion means, and the second Multiplexing means for multiplexing the second data stored in the word width converting means to generate a predetermined transmission packet, and transmitting the predetermined transmission packet generated by the multiplexing means to a predetermined communication line. And a transmitting means for performing.

[0006] Preferably, the predetermined data is AES /
Audio data having a word width of 10 bits (k = 3, m = 10) in which one sample is composed of three words, such as the EBU method, wherein the first word width conversion means is the audio data for one sample. Of the bits included in each of the words, each of the three first portions including eight (n = 8) corresponding to the word width of the asynchronous transfer mode (ATM) or the like is stored, and the second portion is stored. The word width conversion means stores 8 bits stored in the first word width conversion means among bits included in each word of the predetermined data for one sample.
One of the second data including three second portions is generated and stored from three second portions each including two other than the three, and the multiplexing unit is configured to store the three data. The first part and the one second part are multiplexed to generate the predetermined transmission packet, and the transmitting means transmits the predetermined transmission packet generated by the multiplexing means to the ATM or the like. Send to a specified communication line.

Preferably, the second word width conversion means adds the two dummy bits having different values to the three second parts to generate the second data.
Preferably, receiving means for receiving the predetermined transmission packet transmitted from the transmitting means via the predetermined communication line, and the first transmission packet included in the predetermined transmission packet received by the receiving means. It further comprises data reproducing means for reproducing the predetermined data by adding the corresponding second portions to the respective portions.

[0008]

The first word width converting means is, for example, an AES / EBU method (SMPTE-276M, AES; Audio Engineering So-
8 words corresponding to the word width (8 bits) when the ATM communication line handles data from each word of one sample of voice data (hereinafter referred to as AES / EBU data) of ciety INC, EBU; European Broadcasting Union)
Each bit is fetched and stored as the three first parts. The second word width changing means extracts the remaining lower 2 bits from each word of the AES / EBU data for one sample and stores them, and further adds a flag of 2 bits to the second word width of 8 bits. One piece of data is generated and stored.

The multiplexing means stores the three first parts and the one second data stored in each of the first word converting means and the second word converting means into a predetermined transmission packet. This part is multiplexed with an ancillary data area of a PDU packet, which will be described later, to generate this transmission packet. The transmission means sends the transmission packet generated by the multiplexing means to an ATM communication line that handles data having a word width of 8 bits.

[0010]

First Embodiment A first embodiment of the present invention will be described below.
FIG. 1 is a diagram showing a configuration of a data transmission system 1 according to the present invention. Actually, not only two transmission devices 10 and 30 but also more transmission devices are connected to the ATM communication line 20, and the transmission devices 10 and 30 correspond to the transmission devices 30 and 10, respectively. Although the constituent parts are included in each other, they are omitted in FIG. 1 for simplification of the drawing.

As shown in FIG. 1, a data transmission system 1
Is composed of a transmission device 10 on the transmission side, an ATM communication line 20, and a transmission device 30 on the reception side.
Between 0 and 30, predetermined data, for example, audio / video data for a program is transmitted via the ATM communication line 20.
The 155.52 MHz clock supplied from the ATM communication line 20 to the transmission devices 10 and 30 is divided by 8, and
The frequency of the line clock NCLK used when processing the TM cell as 8-bit parallel data is 19.44.
MHz (155.52 / 8). On the other hand, the internal clock 4f _sc generated when transmitting by the SDI system is about 1
4.3 MHz. If they are accurate, the frequencies of these clocks have an integer ratio (NCLK: 4f _sc = 11).
88: 875).

The transmission device 10 on the transmission side includes a clock generator 12 and a digital video tape recorder (VTR) 1.
4. An RTS generator 16 and a transmitter (TX) 18 are included. The clock generator 12 is used in the transmission device 10 by using, for example, a crystal oscillator.
Generates 3MHz internal clock 4f _sc , VTR14,
It is supplied to the RTS generation device 16 and the transmission device 18.

The VTR 14 records / reproduces digital audio / video data of the D2 standard in synchronization with the internal clock 4f _sc, and uses the SDI system or SDDI system (hereinafter, simply SD.
It is output to the transmitting device 18 in the 143 Mbps serial format according to the I method). The RTS generator 16 is
Line clock NCL supplied from ATM communication line 20
Synchronous data RTS (Residual Time Stamp) which indicates an actual integer ratio of the frequency of the internal clock 4f _{sc to} the frequency of K and is used for establishing synchronization with the transmission devices 10 and 30.
).

FIG. 2 is a diagram showing the configuration of the transmission device 18 shown in FIG. As shown in FIG.
Serial / parallel conversion circuit (S / P conversion circuit) 18
0, word width conversion circuit (10/8) 44, shuffling circuit 184, multiplexing circuit (MUX) 186 and ATM
It is composed of a cell generation circuit 188.

The transmission device 18 multiplexes the synchronous data RTS input from the RTS generation device 16 and the audio / video data PVD input from the VTR 14 into a predetermined transmission packet (FIG. 6), and connects the ATM communication line 20. It is transmitted to the transmission device 30 on the receiving side via The S / P conversion circuit 180 converts the audio / video data PVD input by the SDI system into 10-bit parallel data S180 and outputs it to the word width conversion circuit 44.

FIG. 3 shows the word width conversion circuit 4 shown in FIG.
It is a figure which shows the structure of No. 4. FIG. 4 is a diagram showing the operation timing of each part of the word width conversion circuit 44 shown in FIG. In FIG. 4, the names shown in (A) to (I) are
This corresponds to the signal name of each part of the word width conversion circuit 44 in FIG.

FIG. 5 is a diagram showing the operation timing of each portion of the word width conversion circuit 44 shown in FIG.
The names shown in (A) to (G) in FIG. 5 correspond to the signal names of the respective parts of the word width conversion circuit 44 in FIG. The line clock NCL of FIG. 4 (F) and FIG. 5 (A)
The symbol a shown in K indicates the correspondence in timing between FIG. 4 (F) and FIG. 5 (A).

As shown in FIG. 3, the word width conversion circuit 44.
Is composed of a first word width conversion unit 400 and a second word width conversion unit 410, and the word width conversion unit 410 is
Timing generation circuit (TG) 412, first FIFO circuit (FIFOa) 414, FIFO circuit (FIFOb)
416, D-type flip-flop circuit (DFF circuit) 41
8 _0-418 consists of ₃ and a selector circuit (SEL) 420.

The word width conversion unit 400 is shown in FIG.
As shown in (B), in the 10-bit parallel data S180 input from the S / P conversion circuit 180 in synchronization with the internal clock signal 4f _sc , the data related to the video is converted from 10 bits to 8 bits, It outputs to the input terminal a of the selector circuit 420. In the word width conversion unit 410, the timing generation circuit 412 controls the ATM communication line 20.
Line clock NCLK and internal clock 4 supplied from
The timing signal WE shown in FIGS. 4 (C), (G) and FIGS. 5 (B)-(F) is obtained by using f _{sc and} other signals.
N, REN, LCLK0 to LCLK3, SELC are generated.

The FIFO0 circuit 414 is shown in FIG.
As shown in (D), 10-bit parallel data S18
0, a timing signal (write enable signal) WEN showing the timing of 1 sample 3 words shown in Table 1 and a word width of 10 bits and including AES / EBU data used for audio data transmission in the SDI system. Is activated (logical value is 0),
In synchronization with the internal clock 4f _sc , the upper 8 bits of AES / EBU data (S180a; A0 [9: 2] to C2
[9: 2]) are sequentially stored.

Further, the FIFO0 circuit 414 is shown in FIG.
As shown in (F), (G), (H), the FIFO0 circuit 4
Timing signal (read enable signal) indicating the timing of outputting the AES / EBU data stored in 14
While REN is active (logical value is 0),
Output to the input terminal b of the selector circuit 420 in synchronization with the line clock NCLK.

[0022]

[Table 1] AES / EBU data configuration bits / words: 3X: 3X + 1: 3X + 2: ---------------------------------------- ---: b9: b8 ': b8': b8 ': b8: (2 ⁵ ): (2 ¹⁴ ): P: b7: (2 ⁴ ): (2 ¹³ ): C: b6: (2 ³ ): (2 ¹² ): U: b5: (2 ² ): (2 ¹¹ ): V: b4: (2 ¹ ): (2 ¹⁰ ): MSB (2 ¹⁹ ): b3: LSB (2 ⁰ ): (2 ⁹ ) ): (2 ¹⁸ ): b2: CH (MSB): (2 ⁸ ): (2 ¹⁷ ): b1: CH (LSB): (2 ⁷ ): (2 ¹⁶ ): b0: Z: (2 ⁶ ): (2 < ¹⁵ >): -------------------------------- (-) (1) However, X is an integer. . b8 'shows the logical inversion value of the 8th bit of each word.

As shown in Table 1, AES / EB
In U data, the logical inversion value of the 8th bit is used as the 9th bit of each word because all bits of each word of audio data of the AES / EBU system become 0 or 1, and the TRS (3FFh of the SDI system is used. 000h, 000
h, 000h; h represents a hexadecimal number. This is the same as the following).

The FIFO circuit 416 is shown in FIG.
As shown in (D), the timing signal WEN has a logical value of 0.
While the FIFO0 circuit 414 sequentially stores the upper 8 bits of the AES / EBU data, the lower 2 bits of the AES / EBU data are synchronized with the internal clock 4f _sc.
Bit (S180b; A0 [1: 0] to C2 [1: 0]
) Are sequentially stored. Further, the FIFO circuit 416 is
As shown in FIGS. 4F, 4G, and 4I, the DFF circuit 418 is synchronized with the line clock NCLK while the timing signal read enable signal has the logical value 0.
_It outputs to each input terminal of _{0 to} 418 ₃ .

The DFF circuits 418 _{0 to} 418 ₃ are shown in FIG.
As shown in (A) to (E), the AES / E output from the FIFO circuit 416 is synchronized with the timing signals LCLK0 to LCLK3 output from the selector circuit 420.
The lower 2 bits of 4 words of BU data are latched and output to the input terminal c of the selector circuit 420.

The selector circuit 420 is shown in FIG.
As shown in (G), while the selection signal SELC has the logical value 0, the upper 8 bits (A0 [9: 2] to E0 [9: 2]) of the AES / EBU data input to the input terminal a. Are sequentially output in synchronization with the line clock NCLK, and the DFF circuit 418 ₀ while the selection signal SELC has the logical value _0.
～418 ₃ four lower 2 bits stored in (A0
[1: 0] to D2 [1: 0]) are selected and sequentially output, and these are multiplexed to obtain 8-bit parallel data S44.
Output as

In other cases, the selector circuit 420
Selects 8-bit word width data input from the input terminal a and outputs it as 8-bit parallel data S44. The shuffling circuit 184 shuffles (interleaves) the 8-bit parallel data S44 and outputs it to the multiplexing circuit 186 as shuffling data.

FIG. 6 is a diagram showing the structure of a transmission packet (SSCU-PDU packet, hereinafter abbreviated as "PDU packet") generated by the multiplexing circuit 186 shown in FIG. The number attached to the left of the PDU packet indicates the byte length of each data, and the table attached to the right of the PDU packet indicates the contents of the corresponding data. Multiplexing circuit 18
6 multiplexes the shuffling data and the synchronization data RTS input from the RTS generation device 16 into a predetermined transmission packet (PDU packet) shown in FIG. 6, and outputs the multiplexed data to the ATM cell generation circuit 188. .

ATM generated by the multiplexing circuit 186
The data converted into cells and transmitted to the ATM communication line 20 is multiplexed into the PDU packet shown in FIG. PD
In the U packet, the data TRS is FFh, 00h,
00h is the content and indicates the head position of the PDU packet.
Data TRS, ancillary data (ANC; ANCi
llary) area and video data (VIDEO) area except for data inserted every 5 bytes
It is prohibited that the data included in the packet has a value of 00h or FFh.

The synchronization data RTS generated by the RTS generation device 16 is stored in the data RTS1 and RTS2.
This synchronization data RTS is the same as the external clock NCLK 11
832 from the count value of the internal clock 4f _sc during 88 cycles
Is a 6-bit value obtained by subtracting. However, since the transmission packet is transmitted at the time of 910 cycles of the internal clock 4f _sc , two count values may appear during the transmission of one transmission packet. 2 of data RTS1 and RTS2
The reason for securing the two areas is to handle such a case.

The data RTS1 and RTS2 are used in the transmission device 10 on the receiving side to establish network synchronization. A valid bit V (Varid) is entered in the sixth bit of the data RTS1 and RTS2, and the content of the valid bit V is, for example, a logical value 1 when these data are valid and when they are not valid. Has a logical value of 0. Further, in order to prevent the data value from becoming 00h and FFh, the logically inverted value of the valid bit V is added as the seventh bit.

The data LNID (Line Number ID) 1 is
It is used for identifying audio / video data included in the ancillary data area and video data area in the same PDU packet, and the 0th to 2nd bits are a field number (FN; Fiel
d Number), and the third to seventh bits having a value of 0 to 31 indicate a line number (LN; Line Number) indicating a line including audio / video data.

The data LN1 takes a value in the range of 1 to 525 and is used together with the data LNID1 for identifying the audio / video data within the range of 2 fields. The 1st byte and the 2nd byte of the data LN1 have the 0th to 4th bits and the 5th bit of the numerical value, respectively.
9th bit is entered, and the 5th bit of each contains the logically inverted value of the 4th bit for the same reason as the valid bit V of the data RTS1 and RTS2.

The data LNID2 and LN2 are transmitted in order to compensate the synchronization between the audio / video data of the entire station such as a television broadcasting station in which the transmission device 30 on the receiving side is used and the received audio / video data. Used when the transmission device 10 on the transmission side performs processing (advance compensation processing) for transmitting audio / video data at a timing earlier than the audio / video data transmitted by the entire television broadcasting station on the transmission side. To be

That is, in the data LNID2 and LN2, the audio / video data included in the same PDU packet is advanced by a number of lines ahead of the timing at which the audio / video data which should be originally transmitted in the television broadcasting station on the transmitting side. It indicates whether the data is transmitted to the transmission device 30. The data LN
The details of the contents of ID2 and LN2 are the same as those of the above-mentioned data LNID1 and LN1.

By referring to the data LNID2 and LN2, the transmission device 3 on the receiving side can identify the shuffling method and the like from the audio / video data included in the ancillary data area and the video data area.
That is, of the audio / video data, the shuffling block (for 23 lines) of the data portion related to the video is data L
Discrimination is performed from NID2 and LN2, and deshuffling is performed for each shuffling block.

The data Flag has packet table (PT) data indicating the data amount of the ancillary data portion and the video data portion in the 0th to 3rd bits. The fourth to seventh bits include bits sb0 to sb3. These bits sb0 to sb3 are used to convey the shuffling method on the encoder side.

Data RS422-ch1, RS422-
ch2 is, for example, the transmission device 1 on the transmission side and the reception side.
It is used for transmission of control data and the like using RS422 between computers (not shown) connected to 0 and 30, respectively. Data RS422-ch1, RS422
-The high-order 4 bits or the low-order 4 bits of the data to be transmitted are input to the 0th to 3rd bits of ch2, and the data contained in the 0th to 3rd bits are set to the high bits of the 4th bit. Bit UL (Upper / Lower) that is 1 when it is 4 bits and 0 when it is the lower 4 bits
Goes in. For the same reason as the valid bit V of the data RTS1 and RTS2, the logical inversion value of the fourth bit is entered in the fifth bit. Further, in the 6th bit, the data RS422-
A valid bit V indicating whether or not ch1 and RS422-ch2 are valid is added.

The data VOICE contains voice data used for communication and the like. For example, the audio data can be sampled at a sampling frequency substantially equal to the sampling frequency of a PCM encoding device used for general telephone communication, and the horizontal synchronization signal ( 15.75K
Hz) 8 bits are generated, one for every two cycles. Therefore, one audio data is 1 for each cycle of the horizontal sync signal.
It will be transmitted over two generated PDU packets. In the case shown in FIG. 6, the upper 4 bits or the lower 4 bits of the audio data are put in the 0th to 3rd bits of the data VOICE.

Furthermore, the data RS42 is contained in the fourth bit.
Similarly to 2-ch1 and RS422-ch2, the 0th to 3rd
A bit UL indicating whether the bit data is the upper 4 bits or the lower 4 bits is inserted, and the fifth bit is
The logically inverted value of the fourth bit is inserted for the same reason as the valid bit V of the data RTS1 and RTS2, and further, the valid bit V indicating whether or not the audio data is valid is added.

Further, in the 6th and 7th bits, the transmission devices 10 and 30 themselves and the ATM communication line 20 are set to P.
Bits 8F1 and 8F2 (8F is an abbreviation for 8 Frame) used for measuring the delay time given to the DU packet are entered. The data put in the data LNID2 and LN2 is calculated based on the delay time measured using these bits 8F1 and 8F2.

The spare area is an area reserved as a spare in case another use occurs.
Similarly to 1 and RTS2, the logic inversion value of the 6th bit is put in the 7th bit so that the value is neither 00h nor FFh. Data CRCC1, CRCC2, C
The error correction code of the preceding data area is put in each RCC3. Similar to the data RTS1 and RTS2, the logic inversion value of the sixth bit is put in the seventh bit so that the value is neither 00h nor FFh.

The word length of the ancillary data area is, for example, 69 words, and the word width is converted by the word width conversion unit 410 of the word width conversion circuit 44 described above.
S / EBU data is entered. For example, the word width conversion circuit 44 converts 55 words of AES / EBU data into 8
When converted into bits, the 8-bit parallel data obtained as a result of the conversion has 68 bits and 6 bits. In such a case, in order to prevent the prohibition code (00h, FFh) from being generated, the 2-bit value 01 or 10 is put in the remaining 2 bits. Entered 01
Or, 10 is discarded when the PDU packet is reproduced by the receiving device 32. In this area,
The AES / EBU data is in the order of the lower word at the front of the PDU packet and the upper word at the rear of the PDU packet.

In the video data area, of the video data whose word width has been converted by the word width conversion unit 400 of the word width conversion circuit 44, mainly data relating to video is stored. The video data is in the order of the lower byte in front of the PDU packet and the upper byte in the rear.

The ancillary data area and video data area of the PDU packet have variable lengths, and these areas may not include valid data. In addition, the data RS422-ch1, VOICE, etc., are valid bits V
Therefore, for example, when only the valid data V of the data VIOCE is 1 and the valid data V of the other data is 0, only the data VOICE is valid and all the other data are invalid. means.

The ATM cell generation circuit 188 converts the data multiplexed in the PDU packet shown in FIG. 6 into an ATM cell and outputs it as transmission data TXD to the ATM communication line 20. The ATM communication line 20 (FIG. 1) is an Asynchronous Transfer Mode (ATM).
Data is transmitted between the transmission devices 10 and 30 by the method, and a line clock NCLK of 19.44 MHz is supplied to the transmission devices 10 and 30.

The transmission device 30 (FIG. 1) on the receiving side comprises a reception device (RX) 32, a VTR 34, a clock control device 36 and a clock generation device 38.
The ATM cell transmitted from the
Transmission device 1 based on TS and line clock NCLK
Internal clock 4f synchronized with 0 side internal clock 4f _sc
Play _sc to separate audio / video data from PDU packets and record.

FIG. 7 is a diagram showing the configuration of the receiving device 32 shown in FIG. As shown in FIG. 7, the receiving device 32 is
ATM cell disassembly circuit 320, separation circuit 322, deshuffling circuit 324, concealment circuit 326, word width conversion circuit 328 and parallel / serial conversion circuit (P /
S conversion circuit) 330.

The ATM cell disassembling circuit 320 is used in the transmission device 1.
The transmission data RXD (= TXD) transmitted from 0 through the ATM communication line 20 is received by using the line clock NCLK, and the address part of the ATM cell is deleted to obtain the data shown in FIG.
The PDU packet format shown in FIG.
Output to

The separation circuit 322 uses the internal clock 4f _sc to input the PD input from the ATM cell disassembly circuit 320.
Separate the synchronization data RTS from the U packet,
This synchronization data RTS is transferred to the FIF of the clock control device 36.
A write enable signal WEN indicating the timing of writing to the O circuit 360 (FIG. 7) is generated and output to the clock control device 36. Further, the separation circuit 322 separates audio / video data and other data from the PDU packet and outputs it to the deshuffling circuit 324.

The deshuffling circuit 324 is the separation circuit 3
The audio / video data input from 22 is deshuffled (unshuffled) by a method corresponding to the shuffling circuit 184 and output to the concealment circuit 326. The concealment circuit 326 performs error detection using CRC data and the like included in the PDU packet, and conceals (error correction) the input audio / video data.
I do.

The word width conversion circuit 328 is used by the transmission device 10.
The word width conversion circuit 44 of FIG. 2 (FIG. 2) is operated to convert the concealed 8-bit parallel audio / video data into 10-bit parallel data conforming to the SDI system, and the P / S conversion circuit 330 is operated. Output to.
That is, the word width conversion circuit 328 selects the upper 8 bits of the AES / EBU data for the data corresponding to the AES / EBU data among the input 10-bit parallel data.
The bit parts are taken out, the corresponding 2 bits of the AES / EBU data are added to these parts, and the original AES / EBU data is reproduced. For the video data, the reverse processing of the word width conversion unit 400 is performed. To reproduce the original video data.

The P / S conversion circuit 330 converts the 10-bit parallel data into 143 Mbps serial SDI data, and outputs it to the VTR 34 as conversion into D2 standard audio / video data RVD.

The VTR 34 (FIG. 1) has an internal clock 4f.
_The audio / video data RVD input from the P / S conversion circuit 330 is recorded in synchronization with _sc . Clock generator 3
Reference numeral 8 denotes, for example, a voltage controlled oscillator circuit having a crystal oscillator circuit, which generates an internal clock 4f _sc having a frequency according to the control of the clock control device 36 via the clock control signal CC, and each component of the transmission device 30. Supply to. The clock control device 36 generates a clock control signal CC based on the synchronous data RTS input from the reception device 32, and the clock generation device 38 is generated via this clock control signal CC.
There controlling the frequency of the internal clock 4f _sc generated to synchronize the internal clock 4f _sc of the transmission device 30 to the internal clock 4f _sc of the transmission device 10. In addition, the transmitting device 1 described above
8 (FIGS. 2 and 3), the FIFO0 circuit 4
14 corresponds to the first word width conversion means according to the present invention,
The FIFO circuit 416 corresponds to the second word width converting means according to the present invention, and the selector circuit 420 to the multiplexing circuit 186.
Corresponds to the multiplexing means according to the present invention, and the ATM cell generation circuit 188 corresponds to the transmission means according to the present invention.

The operation of the data transmission system 1 will be described below. In the transmission device 10, the VTR 14 reproduces the audio / video data of the D2 standard, and outputs it to the transmission device 18 as 143 Mbps serial audio / video data PVD. On the other hand, the RTS generation device 16 uses the internal clock 4f _sc generated by the clock generation device 12 and the AT
Based on the line clock NCLK supplied by the M communication line 20, the synchronous data RT indicating how many cycles the internal clock 4f _sc enters during the 1188 cycles of the line clock NCLK.
S is generated and sequentially output to the transmission device 18.

The transmitting device 18 uses the audio / video data PVD.
And the synchronization data RTS are multiplexed into the PDU packet shown in FIG. 4, which is further converted into an ATM cell, and AT
The data is transmitted to the transmission device 30 via the M communication line 20. The ATM communication line 20 transmits the ATM cells transmitted from the transmission device 10 to the transmission device 30, and supplies the transmission device 30 with a line clock NCLK.

In the transmission device 30, the ATM cell transmitted from the transmission device 10 is received by the reception device 32, the address part of the ATM cell is removed, and the PDU packet is reproduced. In addition, the receiving device 32 uses the PDU
The synchronous data RTS is separated from the packet and is output to the clock controller 36 together with the write enable signal WEN for writing the synchronous data RTS. In addition, the receiver 32 separates the transmitter 1 from the PDU packet.
The audio / video data RVD corresponding to the audio / video data PVD of 0 is output to the VTR 34, and the VTR 34 records this.

The clock controller 36 controls the synchronous data RT
S, internal clock supplied from clock generator 38
4f_sc, And the times supplied from the ATM communication line 20.
A clock generator 38 based on the line clock NCLK
Internal clock 4f generated by _scFrequency of the transmission device 1
Internal clock 4f at 0_scClock system to synchronize with
The control signal CC is generated and output to the clock generator 38.
Power. The clock generator 38 generates a clock control signal C.
Internal clock signal 4f with frequency according to C_scProduces
It is supplied to each part of the transmission device 30.

As described above, when the word width conversion unit 410 of the word width conversion circuit 44 converts the word width of the AES / EBU data, the value of the upper 2 bits of each word of the AES / EBU data is changed. Must be 01 or 1
Since it becomes 0, the value of the data is 00 except for the word containing the data latched by the DFF circuits 418 _{0 to} 418 _3.
It will never be h or FFh. Therefore, the continuous code (FF) prohibited in the ATM communication line 20
h, 00h, 00h) does not occur.

Further, one PDU packet (FIG. 6) contains AES / EBU data of 4 channels and 4 samples at the maximum. Therefore, the maximum number of words of AES / EBU data included in one PDU packet is 48 words, and the word width conversion unit 410 converts this into a word width of 8 words.
When converted to bit data, it becomes exactly 60 words, and no fractional bits occur. Also, one PDU
When the packet includes 3 channels of AES / EBU data, that is, 36 words of AES / EBU data, the number of words after conversion by the word width conversion unit 410 is 4
Therefore, in this case, too, no fractional bits are generated. Therefore,
The use of the word width conversion unit 410 simplifies the processing of AES / EBU data.

Further, the circuit of the word width conversion circuit 44 is relatively simple and does not significantly increase the device scale of the transmission device 10. Further, when the word width conversion circuits 44 and 328 are used, the SDI system widely used as the infrastructure in television broadcasting stations and the like can be used as the interface of the VTRs 14 and 34, so that the existing equipment can be used. It can be easily connected to an ATM communication line.

The circuit configuration of each part of the data transmission system 1 shown in the above embodiment, the logical value and the waveform of the signal, etc. are examples, and it is possible to replace them with a circuit or the like capable of realizing an equivalent function. . Further, although the VTR device is exemplified as the device connected to the transmission devices 18 and 32, the device is not limited to this, and for example, an editing device for inputting / outputting data in the SDI system or a transmission facility in the SDI system is connected. You may.

The present invention can be applied not only to conversion between data having a word width of 10 bits and a word having a word width of 8 bits but also to word width conversion between data having different word widths. For example, when converting data having a word width of 9 bits into a word width of 5 bits, the FIFO0 circuit 41 is used.
4 is a 5-bit width, only the DFF circuit 418 ₀ having a 4-bit width is provided, and the logical inversion value of the third bit of the data held in the DFF circuit 418 ₀ is added as the fourth bit. The word width conversion unit 410 may be configured by changing the timing of the timing signal generated by the generation circuit 412 accordingly.

Further, the PDU packet shown in FIG. 6 is an example, and the present invention can be applied to a transmission method using a transmission packet of another format. Further, the data transmission system 1 according to the present invention can be applied to any of these data, data for information processing, and the like in addition to audio / video data. The data transmission system 1 according to the present invention can have various configurations, such as the modification shown here, in addition to the above-mentioned embodiments.

[0065]

[Second Embodiment] A second embodiment of the present invention will be described below.
FIG. 8 is a diagram showing a configuration of a word width conversion circuit 40 used in place of the word width conversion circuit 44 shown in FIG. In FIG. 8, of the components of the word width conversion circuit 40, the same components as those of the word width conversion circuit 44 are designated by the same reference numerals. FIG. 9 is a diagram showing the operation timing of each portion of the word width conversion circuit 44 shown in FIG. The names shown in (A) to (I) in FIG. 9 correspond to the signal names of the respective parts of the word width conversion circuit 44 in FIG.

FIG. 10 is a diagram showing the operation timing of each portion of the word width conversion circuit 44 shown in FIG. The names shown in (A) to (F) in FIG. 10 correspond to the signal names of the respective parts of the word width conversion circuit 44 in FIG. The symbol a shown in the line clock NCLK in FIGS. 9 (F) and 10 (A) is the same as in FIG. 9 (F) and FIG.
The correspondence of the timing between (A) is shown.

As shown in FIG. 8, the word width conversion circuit 40
From the configuration of the word width conversion circuit 44 to the DFF circuit 418.
Except for ₀ , only DFF circuits 418 _{1 to} 418 ₃ are set, and D
For example, two bits having a value of 01 are added to the data stored in the FF circuits 418 _{1 to} 418 ₃ . The word width conversion circuit 40 is used in the transmitter 18 in place of the word width conversion circuit 44. Like the word width conversion circuit 44, the word width conversion circuit 40 applies word data having a word width of 10 bits to the ATM communication line 20. Convert to 8-bit data.

As shown in FIGS. 9A and 9B, the 10-bit parallel data S180 is input to the word width conversion circuit 40 in synchronization with the internal clock 4f _sc . FIFO0
As shown in FIGS. 9C and 9D, the circuit 414 has the same internal clock 4f as in the word width conversion circuit 44.
Synchronize with _sc , upper 8 bits of AES / EBU data (S
180a; A0 [9: 2] to C2 [9: 2]) sequentially,
Remember. In addition, the FIFO0 circuit 414 is
As shown in (G) and (H), as in the word width conversion circuit 44, the upper 8 bits of the stored AES / EBU data are input to the input terminal b of the selector circuit 420 in synchronization with the line clock NCLK. Output.

The FIFO circuit 416 is shown in FIG.
As shown in (D), as in the word width conversion circuit 44, AES / EBU is synchronized with the internal clock 4f _sc.
Lower 2 bits of data (S180b; 0, 1, A0
[1: 0] to C2 [1: 0]) are sequentially stored. In addition, the FIFO circuit 416 is configured as shown in FIGS.
As shown in (I), the lower 2 bits of the stored AES / EBU data are synchronized with DF in synchronization with the line clock NCLK.
It outputs to each input terminal of the F circuits 418 _{1 to} 418 ₃ .

The DFF circuits 418 _{1 to} 418 ₃ are shown in FIG.
As shown in (A) to (D), the AES / E output from the FIFO circuit 416 is synchronized with the timing signals LCLK1 to LCLK3 output from the selector circuit 420.
The lower 2 bits of 4 words of BU data are latched, and two dummy bits of fixed value 01 are added and output to the input terminal c of the selector circuit 420. By adding two bits having different values such as a fixed value 01 as dummy bits, the value of the data input to the input terminal c of the selector circuit 420 is 00h or FF.
As a result, the prohibition code (FFh, 00h, 00h) in the ATM communication line 20 can be prevented from occurring.

The selector circuit 420 is shown in FIG.
As shown in (F), as in the word width conversion circuit 44, while the selection signal SELC has a logical value of 0, the higher 8 bits (A0 [9: 2] to D2 [9: 2]) are sequentially output in synchronization with the line clock NCLK, and while the selection signal SELC has the logical value 0, the three lower order bits stored in the DFF circuits 418 _{1 to} 418 ₃ are stored. 2 bits (A0 [1: 0] to D2
[1: 0]) and dummy bits of fixed value 01 added to each of these 6 bits are sequentially output and multiplexed to obtain 8-bit parallel data S40.
Output as

The shuffling circuit 184 (FIG. 2) shuffles the 8-bit parallel data S40 and outputs it to the multiplexing circuit 186. The multiplexing circuit 186 stores the shuffling data and the synchronization data RTS input from the RTS generator 16 in a predetermined transmission packet (P
DU packet) and ATM as multiplexed data
It is output to the cell generation circuit 188.

The multiplexing circuit 186 is the shuffling circuit 1
If the shuffling data input from 84 is less than the data length (69 words) of the ancillary data area shown in FIG. 6, for example, the value is AAh, 55h, or any other dummy value other than 00h, FFh. The data is added to form 69 bytes and output to the ATM cell generation circuit 188. Thus, as dummy data, the value is 00h, F
The reason other than Fh is used for preventing the generation of the prohibition code in the above-mentioned ATM communication line 20.

Each part below the ATM cell generation circuit 188 operates as shown in the first embodiment, and the transmission data T
XD is generated and output to the ATM communication line 20.
In the transmission device 30, the word width conversion circuit 328 of the reception device 32 is configured to perform processing corresponding to the word width conversion circuit 40 to convert 8-bit word width data into 10-word width data. Need to be
That is, the word width conversion circuit 328 removes the dummy bit and the dummy data from the data whose word width has been changed by the word width conversion circuit 40 as described above, and the AES
The original AES / EBU is obtained by adding the lower 2 bits to the upper 8 bits of each word included in one sample of / EBU data.
Data Play data.

As described above, in the data transmission system 1, even if the word width conversion circuit 44 is replaced with the word width conversion circuit 40, the ATM between the transmission devices 10 and 30 is similarly changed.
Data transmission via the communication line 20 is possible. Also,
Even if the word width conversion circuit 40 is used, the word width conversion circuit 44
The same effect as can be obtained.

One PDU packet (FIG. 6) includes AES / EBU data for 4 channels and 4 samples at the maximum. Therefore, the AE included in one PDU packet
The maximum number of words for S / EBU data is 48 words,
If the word width conversion circuit 40 is used, exactly 64
It becomes a word and no fractional bits occur. Also, one P
When the DU packet includes AES / EBU data of 3 channels, that is, 36 words of AES / EBU data, the number of words after conversion by the word width conversion circuit 40 is 4
8, and no fractional bits are generated in this case either. Therefore,
Even if the word width conversion circuit 40 is used, the word width conversion circuit 4
As in the case of using 4, data handling becomes simple.

When the word width conversion circuit 40 is used instead of the word width conversion circuit 44, the amount of data after conversion increases to some extent. However, since the transmission capacity of the ATM communication line 20 has a sufficient margin as compared with the transmission capacities of the transmission devices 10 and 30, there is no problem at all. The word width conversion circuit 40 shown in the second embodiment can be modified similarly to the word width conversion circuit 44.

[0078]

As described above, according to the word width conversion apparatus of the present invention, a transmission method in which the word widths of data are different, for example, an SDI type transmission apparatus having a word width of 10 bits and a word width of 8 bits are used. When data is transmitted to and from the ATM type transmission device, the word width can be changed so that the data to be transmitted conforms to each type. Further, according to the word width conversion device of the present invention, the word width 10 of the SDI system can be generated without generating a data pattern prohibited in the ATM communication line.
Bit data can be converted into ATM-type data having a word width of 8 bits.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a data transmission system according to the present invention.

FIG. 2 is a diagram showing a configuration of a transmission device shown in FIG.

FIG. 3 is a diagram showing a configuration of a word width conversion circuit shown in FIG.

FIG. 4 is a diagram showing operation timings of respective parts of the word width conversion circuit shown in FIG. 3;

5 is a diagram showing the operation timing of each part of the word width conversion circuit shown in FIG. 3;

6 is a diagram showing a configuration of a PDU packet generated by the multiplexing circuit shown in FIG.

FIG. 7 is a diagram showing a configuration of a receiving device shown in FIG.

8 is a diagram showing a configuration of a word width conversion circuit 40 used in place of the word width conversion circuit 44 shown in FIG.

9 is a diagram showing operation timings of respective parts of the word width conversion circuit shown in FIG. 8;

10 is a diagram showing the operation timing of each part of the word width conversion circuit shown in FIG. 8;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Data transmission system, 10 ... Transmission device, 12 ... Clock generation device, 14 ... VTR, 16 ... RTS generation device,
18 ... Transmission device, 180 ... S / P conversion circuit, 44, 40
... Word width conversion circuit, 400, 410 ... Word width conversion unit, 412 ... Timing generation circuit, 414, 416 ... F
IF0 circuit, 418 _{0 to} 418 ₃ ... DFF circuit, 184
... Shuffling circuit, 186 ... Multiplexing circuit, 188 ... A
TM cell generation circuit, 20 ... ATM communication line, 30 ... Transmission device, 32 ... Reception device, 320 ... ATM cell disassembly circuit,
322 ... Separation circuit, 324 ... Deshuffling circuit, 32
6 ... Conceal circuit, 328 ... Word width conversion circuit, 33
0 ... P / S conversion circuit, 34 ... VTR, 36 ... Clock control device, 360 ... FIFO circuit, 362 ... Latch circuit,
366 ... Latch circuit, 368 ... Switch circuit, 370 ...
Switch control circuit, 372 ... NOT circuit, 374 ... Counter circuit, 376 ... DFF, 378 ... Decoder circuit, 3
80 ... Counter circuit, 382 ... DFF, 384 ... Comparison circuit, 38 ... Clock generator

Claims (4)

[Claims] 1. Predetermined data composed of k words each having a word width of m bits is converted into data having a word width of n bits (k, m, n is an integer, m> n) for each sample. A word width conversion device, comprising: first word width conversion means for storing k first parts each including a predetermined n number of bits included in each word of the predetermined data for one sample. , Among the bits included in each word of the predetermined data for one sample, the second portion k from the second portion k consisting of mn pieces other than the predetermined n pieces, respectively.
[n / (m−n)] (where [X] represents an integer not exceeding X), each of which includes the second data having a word width of n bits is [k / [n / (m−n)] ]] Pieces (k / [n / (m
-N)] is an integer) or [k / [n / (m-
n)]] + 1 (when k / [n / (m−n)] is not an integer) second word width conversion means for generating and storing, and the first word width conversion means for storing the second word width conversion means. Multiplexing means for multiplexing a first part and the second data stored in the second word width converting means to generate a predetermined transmission packet; and the predetermined means generated by the multiplexing means. A word width conversion device having a transmission means for transmitting a transmission packet to a predetermined communication line. 2. The predetermined data has a word width of 10 in which one sample of AES / EBU method is composed of 3 words.
Audio data of bits (k = 3, m = 10), wherein the first word width conversion means includes an asynchronous transfer mode (ATM) among bits included in each word of the audio data for one sample. 3 pieces of the first portions each including 8 pieces (n = 8) corresponding to the same word width are stored, and the second word width conversion means stores each word of the predetermined data for one sample. Of the bits included in the first word width converting means, each of which includes two second bits other than the eight bits, the word width 8 including three second parts each. One of the second data of bits is generated and stored, and the multiplexing means multiplexes the three first parts and the one second part to generate the predetermined transmission packet. Generate, said transmitting means generates by said multiplexing means The word width conversion device according to claim 1, wherein the predetermined transmission packet is transmitted to the predetermined communication line such as ATM. 3. The second word width conversion means adds the two dummy bits having different values to the three second parts to generate the second data. The described word width conversion device. 4. A receiving means for receiving the predetermined transmission packet transmitted from the transmitting means via the predetermined communication line, and the first transmission packet included in the predetermined transmission packet received by the receiving means. 2. The word width conversion device according to claim 1, further comprising a data reproducing unit that reproduces the predetermined data by adding the corresponding second portion to each of the portions.