JPH0936837A - Digital signal error monitoring system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve capacity for detecting the lack/double reading of a vertical bit string, which occurs at the transmission of a parallel data signal 5. SOLUTION: An error monitoring signal line is povided, and the signal is transmitted by permitting a monitoring frame 12 consisting of a monitoring header 10 and a monitoring payload 11 to synchronize with a data frame 9. The monitoring header 10 is provided with error detection information obtained from the vertical parity of the parallel data signal 5. The monitoring payload 11 is the vertical parity of the data payload part of the parallel data signal 5 and it detects an error synchronized in the respective signals of the parallel data signals 5 by using the monitoring frame 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal error monitoring system in a digital signal processing device or a digital signal transmission device, and more particularly to a parallel digital signal error monitoring system.

[0002]

2. Description of the Related Art At present, it has become common to transmit digital data not only in computers but also in communications, and it is required to ensure high reliability of digital data in transmission.

A parity check is widely used as one of the measures for ensuring high reliability in a digital signal processing device or a digital signal transmission device. The parity check adds a parity bit to the unit data to be monitored,
It is usual to determine the value of the parity bit so that the number of "1" s contained in them is even or odd for each data, that is, the parity is fixed to either even parity or odd parity. This makes it possible to detect a bit error in one unit of data. However, as a conventional technique, as disclosed in Japanese Patent Laid-Open No. 62-34422, a fault detection capability in which the even and odd of parity bits added to each data transmitted serially is alternately changed to be in the same code continuous state. And Japanese Patent Application Laid-Open No. 5-347653
As disclosed in Japanese Patent Laid-Open Publication No. JP-A-2003-264, in a transmission system in which each bit of data is transmitted in parallel, there is also a system in which even or odd parity bits are alternately changed for each data so that data loss or double-feeding can be monitored. It was

Further, when data is transmitted synchronously between transmission lines by using parallel transmission lines, horizontal parity for adding a parity bit for every predetermined number of bits transmitted in series to each transmission line, and the transmission line There was also a system (horizontal / vertical parity check system) in which a parity bit was added to the synchronized bits between the data and the data and the vertical parity transmitted in parallel were used together.

Further, there has been a method of increasing the number of additional bits for error checking to form a cyclic code and improving the error detection ability and error correction ability.

[0006]

When an attempt is made to use the above-mentioned conventional technique as an error monitoring system for parallel data signals in which fixed-length data frames each consisting of a data header and a data payload are synchronously transmitted in parallel, There are problems. As an example of transmission error, the read clock for reading the transmitted data frame does not synchronize with each bit of the data frame, and the entire vertical bit sequence, which is a synchronized bit sequence on the parallel transmission path, is not read and is lost. , The same vertical bit string may be read twice. Such errors are more likely to occur due to subtle clock deviations and clock waveform distortions as the transmission speed increases.

When a simple parity check is used for vertical parity, only a single error in the target vertical bit string can be detected, and the above-mentioned missing / double reading of the vertical bit string cannot be detected. There is a problem that the error monitoring capability is low.

In the system in which the vertical parity is changed alternately, when only one vertical bit string is missing / read twice, the same parity continues two times at that location, so that an error can be detected. However, it is not possible to detect two consecutive missing lines.

The horizontal / vertical parity check system has a problem in that the device becomes complicated because the transmission rate must be converted in order to insert the horizontal parity. Although the clock frequency used for transmission after horizontal parity insertion is higher than that before insertion, it may be difficult in high-speed data transmission near the upper limit of transmission speed.

In addition, a method of error-monitoring the data of each transmission line as a cyclic code is a CRC (Cyclic R
edundancy Check), but
In order to follow the increase in transmission speed, it is necessary to take measures such as providing a plurality of CRC processing circuits and performing parallel processing.
There is a problem that the device scale becomes large.

The first aspect of the present invention is to eliminate a vertical bit string loss inside a digital signal processor or digital signal transmitter.
The purpose of the present invention is to provide a digital signal error monitoring system with excellent error detection capability when double reading occurs, and to suppress the increase in the size and cost of the digital signal processing device and the digital signal transmission device while suppressing the transmission. It is intended to realize high reliability and high transmission speed.

[0012]

According to a first aspect of the present invention, there is provided a digital signal error monitoring system having an error monitoring signal line for transmitting a monitoring frame composed of a monitoring header and a monitoring payload in synchronization with a data frame. The header has error detection information obtained from the vertical parity of the parallel data signal, the supervisory payload is the vertical parity of the data payload part of the parallel data signal, and the error synchronized between the signals of the parallel data signal using the supervisory frame Is characterized by being able to detect.

According to a second aspect of the digital signal error monitoring system, the error detection information contained in the monitor header is the horizontal parity of the vertical parity contained in the monitor payload.

The digital signal error monitoring system according to a third aspect of the present invention is characterized in that the error detection information contained in the monitoring header is a check bit when the monitoring payload is cyclically encoded as an information bit.

According to a fourth aspect of the digital signal error monitoring system of the present invention, the error detection information contained in the monitoring header is a check bit when the vertical parity of the data frame is cyclically encoded as an information bit.

According to a fifth aspect of the digital signal error monitoring system of the present invention, the error detection information contained in the monitor header is the number of vertical parity "1" or "0" contained in the monitor frame.

A digital signal error monitoring system according to a sixth aspect of the present invention has an error monitoring signal line for transmitting a monitoring frame composed of a monitoring header and a monitoring payload in synchronization with a data frame, and the monitoring header has each monitoring frame. It is characterized in that it has immutable data and can detect an error in synchronization between the respective data headers of the parallel data signal by using the supervisory frame.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same reference numerals refer to the elements having the same functions, and the description thereof will be omitted.

[First Embodiment] FIG. 1 is a block diagram of a signal transmission system according to one embodiment of the present invention. The signal transmitting device 1 and the signal receiving device 2 include a parallel data signal line 3 for transmitting four data signals and one error monitoring signal line 4
And are connected by.

FIG. 2 is a timing chart showing the structures of the parallel data signal 5 and the error monitor signal 6 transmitted through both the signal lines. In the figure, time passes from left to right. A data header 7 and a data payload 8 are alternately arranged in each data signal of the parallel data signal 5. The data header 7 and the data payload 8 following it form one data frame 9. The data header 7 holds a bit pattern indicating the start of a frame, a transmission destination of the frame, a frame number, and other information used for control of transmission. The data payload 8 is substantive information to be transmitted. Data header 7 and data payload 8
Each data signal composed of and is transmitted in parallel in synchronization.
The error supervisory signal 6 is synchronized with the data header and the data payload of the parallel data signal 5, respectively, and the supervisory header 10,
The surveillance payload 11 is transmitted. One supervisory frame 1 with supervisory header 10 and supervisory payload 11 following it
Make up 2.

FIG. 3 shows the first embodiment of the present invention.
6 is a timing chart of a specific example of the parallel data signal 5 and the error monitoring signal 6 transmitted from the signal transmission device 1. In this figure, bit values that are not related to the invention are omitted. Although the data payload 8 and the monitoring payload 11 are each 8 bits for simplicity of illustration and description, in reality, they generally have a longer bit length.

The monitoring payload 11 has 4 bytes synchronized with it.
It is a string of vertical parity check bits of one data payload. More specifically, a check bit is defined so that even bits are synchronized with each other in the four data payloads.
1 are arranged and transmitted.

The last 1 bit of the monitor header 10 contains "1" which is the parity of this monitor payload "10110011". The last 1 bit of the monitoring header 10 is the horizontal parity of the vertical parity of the four data payloads.

The signal receiving device 2 reads the parallel data signal 5 and the error monitoring signal 6 shown in FIG. FIG. 4 illustrates a parallel data signal 5 and an error monitor signal 6 received by the signal receiving apparatus 2 for explaining the error detection operation of this embodiment.
3 is a timing chart of a specific example of FIG. In this figure, FIG.
The third and fourth bits of the data payload 8 and the supervisory payload 11 are not read because they are not read due to the disturbance of the read clock of the signal receiving device 2, and the first and second bits of the supervisory header 10 'of the next supervisory frame are lost. Is '01'
It is shown that the items up to and including the above are recognized as the erroneous monitoring payload 13 in which the missing has occurred. In this case, the parity of the wrong monitoring payload 13 becomes an even parity, and the last 1 of the monitoring header set at the time of transmission is set.
Since it is different from the bit, the signal receiving device 2
Data payload 8 after transmission from the signal transmission device 1
It is possible to detect that an error has occurred in. In this way, among two consecutive missing or other missing / double reading,
The parity of the wrong monitoring payload 13 is the monitoring header 10
An error that would be different from the parity checksum of the data payload in the transmission stored in the can be detected by the present invention.

Further, an individual bit error in each vertical bit string of the data payload can be detected by the parity check bit stored in the monitor payload.

Here, all the parity check bits stored in the monitoring payload 11 are set to have vertical parity as even parity. In addition, it is possible to complement the case where an error can be detected and enhance the error detecting ability.

[Embodiment 2] FIG. 5 is a timing chart of a concrete example of the parallel data signal 5 and the error monitor signal 6 transmitted from the signal transmitting apparatus 1 in the second embodiment of the present invention. Also in this figure, the bit values that are not related to the invention are omitted. In this embodiment, the error detection information of a certain data frame is stored in the monitor header 14 of the monitor frame synchronized with the next data frame.

The monitoring payload 11 is a string of vertical parity check bits of the data payload as in the first embodiment.

The last part of the monitoring header 14 contains a check bit string "0100" when the monitoring payload "10110011" is cyclically encoded as information bits. The check bit string is obtained as follows. Here, the generator polynomial of the cyclic code is G (X) = X ⁴ + X + 1 (1). The information bit sequence is a monitoring payload contents as information polynomial is expressed as ^{U (X) = X 7 +} X 5 + X 4 + X + 1 ......... (2). U (X) is multiplied by X ⁴ based on the order of G (X), and is divided by G (X) (modulo 2 division, the same applies below), that is, X ⁴ · U ( X) /
The remainder polynomial R (X) of G (X) is expressed by the following equation.
'0100' in which the coefficients of (X) are arranged is the check bit string.

R (X) = X ² (3) The cyclic code is an encoded information polynomial, F (X) = X ⁴ · U (X) + R (X) (4) It is a coefficient, that is, “101100110100” in which a check bit string and an information bit string are arranged. Here, the remainder obtained by dividing F (X) by G (X) is 0, that is, mod {F (X), G (X)} = 0 ... (5).

FIGS. 6 and 7 are timing charts of specific examples of the parallel data signal 5 and the error monitor signal 6 received by the signal receiving apparatus 2 for explaining the error detection operation of this embodiment. In FIG. 6, the third and fourth bits of the data payload 8 and the monitoring payload 11 are not read and are lost due to the disturbance of the read clock of the signal receiving device 2,
1st bit, 2nd of the supervisory header 14 of the next supervisory frame
It is shown that bits up to '01' are moved up and recognized as the erroneous monitoring payload 13 in which the missing has occurred. In this case, the wrong monitoring payload 1
The polynomial expression of the bit string '100011010100' consisting of 3 and the check bit string in the monitoring header 14 is as follows.

F ′ (X) = X ¹¹ + X ⁷ + X ⁶ + X ⁴ + X ² (6) The signal receiving device 2 has a circuit for performing CRC processing,
The circuit calculates the remainder by dividing F ′ (X) by G (X), and mod {F ′ (X), G (X)} ≠ 0 (7) It is detected that an error has occurred in the data payload 8 after the transmission.

FIG. 7 shows that the fourth bit of the data payload 8 and the monitor payload 11 is read twice and the fifth bit is missing. In this case, the polynomial expression of the bit string '101110110100' composed of the incorrect monitoring payload 15 and the check bit string in the monitoring header 14 is as follows.

F ′ (X) = X ¹¹ + X ⁹ + X ⁸ + X ⁷ + X ⁵ + X ⁴ + X ² (8) Also in this case, since the equation (7) is satisfied as in the previous case, the signal reception The device 2 can detect that an error has occurred in the data payload 8 after transmission from the signal transmission device 1.

As described above, among two consecutive missing lines and other missing / double reading, the erroneous monitoring payload bit pattern is less than or equal to a predetermined number determined by the bit pattern of the monitoring payload 11 at the time of transmission and the number of inspection bits. An error that causes a difference can be detected and its position can be specified by the present invention.

Further, similarly to the first embodiment, by using the conventional technique together, the monitoring payload 11 is set to alternate between even parity / odd parity for each bit to complement the case where an error can be detected, thereby enhancing the error detection capability. .

[Third Embodiment] FIG. 8 is a diagram showing the structure of a data frame and a supervisory frame transmitted from the signal transmitting apparatus 1 according to the third embodiment of the present invention. The bit string u _P stored in the monitoring payload 11 is a string of vertical parity check bits of the data payload as in the first and second embodiments. The monitoring header 16 contains
A check bit string r is stored when the vertical parity check bits for the entire data frame are cyclically encoded as an information bit string.

Let k be the degree of the generator polynomial G (X) of the cyclic code.
Next, let the length of the data header 7 be n bits. If the polynomials corresponding to the vertical parity check bits of the data header 7 and the bit string u _P of the contents of the monitoring payload 11 are U _H (X) and U _P (X), the information polynomial U (X),
Each remainder polynomial R (X) and coded information polynomial F (X) _{is, U (X) = U H} (X) + X n · U P (X) ......... (9) R (X) = mod {X ^k · U (X) / G (X)} (10) F (X) = R (X) + X ^k · U (X) ... (11)

FIG. 9 and FIG. 10 are structural views of the data frame and the supervisory frame showing an example of an error at the time of reading by the signal receiving device 2.

In the example shown in FIG. 9, the vertical bit string is missing or read twice at the shaded portion of the payload portion, and the polynomial corresponding to this erroneous monitoring payload 17 is _UP '( X). In this case, U _H (X)
Can be obtained from the data header 7, so an erroneous information polynomial U ′ (X), an erroneous coded information polynomial F ′ (X)
Are respectively U ′ (X) = U _H (X) + X ⁿ · UP _P ′ (X) ……… (12) F ′ (X) = R (X) + X ^k · U ′ (X) ……… It is expressed as (13). The signal receiving device 2 has a circuit for performing a CRC process, and the circuit calculates a remainder by dividing F '(X) by G (X), and mod {F' (X), G (X)}. Since ≠ 0 (14), it is detected that an error has occurred in the data frame after transmission from the signal transmission device 1.

The example shown in FIG. 10 is a bit position in which the check bit string of the monitoring header is stored, and is shown in a shaded area in the drawing when the vertical bit string in the header portion is missing or is read twice. is there. In this case, both the polynomial corresponding to the vertical parity check bit of the data header 7 and the remainder polynomial corresponding to the check bit string become erroneous, and these are U _H ′ (X) and R ′ (X), respectively.
U _H ′ (X) can be obtained from the incorrect data header 18. Incorrect information polynomial U '(X), incorrect coded information polynomial F' (X), respectively, U '(X) = U H' (X) + X n · U P (X) ......... (15) F ′ (X) = R ′ (X) + X ^k · U ′ (X) ... (16) Comparing equations (13) and (16), even if the vertical bit string has the same reading error, the error at the position where the check bit string of the monitoring header corresponding to equation (16) described here is stored is as follows. It can be seen that the error location of the coded information polynomial is doubled compared to the error in the payload corresponding to equation (13). Therefore, the upper limit of the number of error detection bits in this case is lower than the predetermined number of check bits, but (1
The fact that an error has occurred can be detected from equation (4), as in the previous case.

That is, also in this case, as in the previous case, the expression (14) is established, and thus the signal receiving apparatus 2 can detect that an error has occurred in the data frame after the transmission from the signal transmitting apparatus 1. it can. Embodiment 2
Similarly, the ability to detect errors and locate them is determined by the number of check bits.

The present invention has error detection capability in both the data header and the data payload.

[Fourth Embodiment] FIG. 11 is a timing chart of a concrete example of the parallel data signal 5 and the error monitor signal 6 transmitted from the signal transmitting apparatus 1 in the fourth embodiment of the present invention. In this figure, bit values that are not related to the invention are omitted.

The monitoring payload 11 has 4
It is a string of vertical parity check bits of one data payload. More specifically, a check bit is defined so that even bits are synchronized with each other in the four data payloads.
1 are arranged and transmitted.

The last 4 bits of the surveillance header 19 contain "0101" which is a binary representation of "5" which is the number of "1" s in the surveillance payload "10110011".

The signal receiving device 2 reads the parallel data signal 5 and the error monitoring signal 6 shown in FIG. Figure 12
6 is a timing chart of a specific example of the parallel data signal 5 and the error monitoring signal 6 received by the signal receiving device 2 for explaining the error detection operation of the present embodiment. In this figure, the third and fourth bits of the data payload 8 and the supervisory payload 11 of FIG. 11 are not read because they are not read due to the disturbance of the read clock of the signal receiving apparatus 2, and the first header of the supervisory header 19 'of the next supervisory frame. It is shown that bits up to '01', which is the second bit, are carried up and recognized as the erroneous monitoring payload 20 in which the above-mentioned omission occurred. In this case, "1" in the wrong monitoring payload 20
The number is 4 and is different from the number 5 recorded in the monitoring header 19 set at the time of transmission. Therefore, the signal receiving device 2 transmits data from the signal transmitting device 1 to the data payload 8 after transmission. It is possible to detect that an error has occurred.

[Embodiment 5] In the present invention, the same bit string is recorded in the supervisory header of each supervisory frame and transmitted from the signal transmitter 1 together with the data frame. The bit pattern recorded in the monitoring header is the signal receiving device 2
I will also remember it. The signal receiving device 2 compares the read monitoring header with the bit pattern of the monitoring header stored in itself, and when they are different from each other, the vertical bit string of the data header is lost after the transmission from the signal transmitting device 1.
Judge that an error in reading occurred.

The bit string to be recorded in the monitoring header may be one fixed codeword of the cyclic code system, and the difference between the monitoring header contents at the time of transmission and the time of reception may be detected by CRC.

[0050]

According to the digital signal error monitoring system of claims 1 to 6 of the present invention, a parallel data signal in which a fixed-length data frame composed of a data header and a data payload is synchronously transmitted in parallel. The detection capability for errors such as missing vertical bit strings and double reading is improved. In particular, there is an effect that the ability to detect two consecutive missing vertical bit strings is improved. This error detection is performed mainly by processing the monitoring frame of the error monitoring signal line, and the amount of data to be processed is smaller than when processing individual data frames of the parallel data signal, and the error detection circuit is simple and digital. The signal processing device / digital signal transmission device can be reduced in cost and size. In addition, since the conversion of the transmission rate is unnecessary, the effect of suppressing the complication of the device can be suppressed, and the high transmission rate can be maintained.

According to the digital signal error monitoring system of claim 6,
Errors in the data header can be detected.

According to the digital signal error monitoring system of claim 2 of the present invention, the bit pattern consisting of the vertical parity of the data payload changes, and the vertical bit string is missing.
There is an effect that misreading can be detected.

According to the digital signal error monitoring method of the third aspect of the present invention, it is possible to detect a missing vertical bit string in the data payload and double reading error, and to specify the error location.

According to the digital signal error monitoring method of the fourth aspect of the present invention, it is possible to detect a missing vertical bit string in the data header and the data payload and a double reading error, and to specify the error location.

According to the digital signal error monitoring method of the fifth aspect of the present invention, it is possible to detect a missing vertical bit string and a double reading error in which the number of even or odd vertical parities of the data payload changes.

[Brief description of drawings]

FIG. 1 is a block diagram of a signal transmission system according to the present invention.

FIG. 2 is a timing chart showing configurations of a parallel data signal and an error monitoring signal.

FIG. 3 is a timing chart of a parallel data signal and an error monitor signal during transmission according to the first embodiment.

FIG. 4 is a timing chart of a read parallel data signal and an error monitoring signal according to the first embodiment.

FIG. 5 is a timing chart of a parallel data signal and an error monitor signal during transmission according to the second embodiment.

FIG. 6 is a timing chart of a read parallel data signal and an error monitoring signal according to the second embodiment.

FIG. 7 is a timing chart of a read parallel data signal and an error monitoring signal according to the second embodiment.

FIG. 8 is a structural diagram of a data frame and a supervisory frame during transmission according to the third embodiment.

FIG. 9 is a structural diagram of a read data frame and a monitor frame according to the third embodiment.

FIG. 10 is a structural diagram of a read data frame and a monitor frame according to the third embodiment.

FIG. 11 is a timing chart of a parallel data signal and an error monitor signal during transmission according to the fourth embodiment.

FIG. 12 is a timing chart of a read parallel data signal and an error monitoring signal according to the fourth embodiment.

[Explanation of Codes] 1 signal transmitter, 2 signal receiver, 3 parallel data signal lines, 4 error monitoring signal lines, 5 parallel data signals, 6
Error monitoring signal, 7 data header, 8 data payload, 9 data frame, 10, 14, 16, 19
Monitoring header, 11, 13, 15, 17, 20 monitoring payload, 12 monitoring frames.

Claims (6)

[Claims] 1. In a digital signal error monitoring system for a parallel data signal in which a fixed-length data frame composed of a data header and a data payload is transmitted in parallel in synchronization, a monitoring frame composed of a monitoring header and a monitoring payload is provided. It has an error monitor signal line that is transmitted in synchronization with the data frame, the monitor header has error detection information obtained from the vertical parity of the parallel data signal, and the monitor payload is the vertical parity of the data payload of the parallel data signal. Yes, a digital signal error monitoring method characterized by being able to detect errors that are synchronized between the parallel data signals using a monitoring frame. 2. The digital signal error monitoring system according to claim 1, wherein the error detection information included in the monitoring header is a vertical parity checksum included in the monitoring payload. 3. The digital signal error monitoring system according to claim 1, wherein the error detection information included in the monitoring header is a check bit when the monitoring payload is cyclically encoded as an information bit. 4. The digital signal error monitoring system according to claim 1, wherein the error detection information included in the monitoring header is a check bit when cyclic coding is performed using vertical parity of the data frame as information bits. 5. The digital signal error monitoring system according to claim 1, wherein the error detection information included in the monitor header is the number of vertical parity “1” s or “0” included in the monitor frame. 6. A digital signal error monitoring system for a parallel data signal in which a fixed-length data frame composed of a data header and a data payload is synchronously transmitted in parallel, in a digital signal error monitoring system, a monitoring frame composed of a monitoring header and a monitoring payload. It has an error supervisory signal line that is transmitted in synchronization with the data frame, and the supervisory header has invariant data for each supervisory frame. Digital signal error monitoring method characterized by being able to detect.