JPH0936736A - Voltage controller oscillator circuit - Google Patents

Voltage controller oscillator circuit

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Publication number
JPH0936736A
JPH0936736A JP8155247A JP15524796A JPH0936736A JP H0936736 A JPH0936736 A JP H0936736A JP 8155247 A JP8155247 A JP 8155247A JP 15524796 A JP15524796 A JP 15524796A JP H0936736 A JPH0936736 A JP H0936736A
Authority
JP
Japan
Prior art keywords
circuit
voltage
frequency
controlled oscillator
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8155247A
Other languages
Japanese (ja)
Other versions
JP2737747B2 (en
Inventor
Katsuyuki Ikeda
勝幸 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP8155247A priority Critical patent/JP2737747B2/en
Publication of JPH0936736A publication Critical patent/JPH0936736A/en
Application granted granted Critical
Publication of JP2737747B2 publication Critical patent/JP2737747B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PROBLEM TO BE SOLVED: To attain a stable circuit with less drift by taking the symmetry of each circuit into account thereby canceling fluctuation in characteristics with each other in the design of an integrated circuit. SOLUTION: When a free run frequency of a voltage controlled oscillator 104 changes, a voltage applied to a terminal 112 is changed automatically to keep an oscillating frequency of the circuit 104 to be a frequency fref of an oscillation circuit 107. When an optional voltage is given to a terminal 111 of a 2nd signal synthesis means 103, a voltage at a terminal 112 is adjusted so that the oscillating frequency of the circuit 104 is the fref . Thus, when the reference voltage at the terminal 112 is given to a 1st signal synthesis means 101, the oscillating frequency of the 1st voltage controlled oscillator 102 becomes fref by arranging characteristics of the means 101, 103 and the circuit 104. When the frequency fref set to be a desired free run frequency fc and the voltage applied to the means 101 is the reference voltage, the oscillating frequency of the circuit 102 is fc and then the circuit for the free run frequency ffc is realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は位相固定ループ(P
LL,Phase Locked Loop)等に用い
られる電圧制御発振回路に関する。本発明は電圧制御発
振回路の特にフリーラン周波数の安定化を計った回路に
関する。
TECHNICAL FIELD The present invention relates to a phase locked loop (P
The present invention relates to a voltage controlled oscillator circuit used for LL, Phase Locked Loop, etc. The present invention relates to a voltage-controlled oscillator circuit, particularly to a circuit in which the free-run frequency is stabilized.

【0002】[0002]

【従来の技術】従来より電圧制御発振回路は非常に多く
発表されている。図3に例としてPLL用1チップ相補
MOS集積回路(CMOS・IC)に用いられている電
圧制御発振回路を掲げる。NチャネルトランジスタN1
のゲートに加えられる制御電圧によりコンデンサC1
流入する電流を制御し発振周波数をコントロールする。
抵抗R1 ,R2 はそれぞれ制御電圧感度係数、フリーラ
ン周波数を決定する。
2. Description of the Related Art A large number of voltage-controlled oscillator circuits have been published. FIG. 3 shows, as an example, a voltage controlled oscillator circuit used in a one-chip complementary MOS integrated circuit for PLL (CMOS IC). N-channel transistor N 1
The control voltage applied to the gate of control the current flowing into the capacitor C 1 to control the oscillation frequency.
The resistors R 1 and R 2 determine the control voltage sensitivity coefficient and the free-run frequency, respectively.

【0003】また他の例として図4には特公昭56ー8
6509により公知の電圧制御発振回路を示す。該回路
はリングオシレータに流入する電流をソースに接続され
たトランジスタT41〜T46のゲート電圧により制御し発
振周波数を制御するものである。この回路は図4の回路
に比較し外付部品が不要で消費電力、実装スぺースも小
さい利点があるが正確で安定な発振回路は作りにくい。
As another example, FIG. 4 shows Japanese Patent Publication No. 56-8.
6509 shows a known voltage controlled oscillator circuit. This circuit controls the oscillation frequency by controlling the current flowing into the ring oscillator by the gate voltage of the transistors T 41 to T 46 connected to the sources. Compared with the circuit of FIG. 4, this circuit does not require external parts and has the advantages of low power consumption and small mounting space, but it is difficult to make an accurate and stable oscillation circuit.

【0004】また図3の回路でも安定度は充分とは言え
ない。
Further, the circuit of FIG. 3 cannot be said to have sufficient stability.

【0005】[0005]

【発明が解決しようとする課題】一般に電圧制御発振回
路に対し、安定度の要求されるのはフリーラン周波数及
び電圧制御感度係数である。前者は電圧制御発振回路の
制御端子に加えられる電圧(制御電圧)が基準レべルの
ときの発振周波数である。基準レべルは通常制御可能な
入力電圧範囲の中央、例えばCMOS・ICでは電源電
圧の1/2に選ばれ、制御電圧をVC ・基準レべルの電
圧をVS として△VC を △VC =VC ーVS ・・・・・(1) と定義すればフリーラン周波数は△VC =0のときの発
振周波数と言い直しても良い。電圧制御感度係数KV は f0 =fC +KV ・△V・・・(2) として定義される。fC はフリーラン周波数、f0 は電
圧制御発振回路の発振周波数である。
Generally, for a voltage controlled oscillator circuit, it is the free run frequency and the voltage controlled sensitivity coefficient that are required to have stability. The former is the oscillation frequency when the voltage (control voltage) applied to the control terminal of the voltage controlled oscillator circuit is at the reference level. The reference level is usually selected at the center of the controllable input voltage range, for example, 1/2 of the power supply voltage in a CMOS IC, and the control voltage is V C and the reference level voltage is V S , and ΔV C is If it is defined as ΔV C = V C −V S (1), the free-run frequency may be restated as the oscillation frequency when ΔV C = 0. The voltage control sensitivity coefficient K V is defined as f 0 = f C + K V · ΔV (2) f C is the free run frequency, and f 0 is the oscillation frequency of the voltage controlled oscillator circuit.

【0006】フリーラン周波数fC のドリフ卜はPLL
においては系のキャプチャレンジのドリフトとなって悪
影響があらわれる。 また、回路部品定数のばらつきに
よるfC のばらつきは無視できない程度に大きく、従来
はコス卜高を覚悟した上で高制度部品を用いるか、組立
後に半固定抵抗や半固定コンデンサにより調整、合せ込
みをする必要があった。また電圧制御感度係数KV のド
リフトはPLLを構成した場合、系の応答速度のドリフ
卜となって悪影響があらわれる。
The drift of the free-run frequency f C is a PLL
In, the adverse effect appears as a drift of the capture range of the system. Also, the variation in f C due to the variation in the circuit component constant is so large that it cannot be ignored. Conventionally, high precision components should be used after preparing for high cost, or after assembly, adjustment and adjustment with a semi-fixed resistor or semi-fixed capacitor. Had to do. When the PLL is constructed, the drift of the voltage control sensitivity coefficient K V becomes a drift of the response speed of the system and has an adverse effect.

【0007】これ等のドリフトの原因は周囲温度の変
化、使用電源の変動、部品定数の軽時変化等である。特
にfC の変動はこれ等の要因により大きくドリフ卜す
る。一方KV は回路の構成部品の相対精度により決まる
様にすることができ半導体集積回路技術等により素子値
の絶対精度はなくとも相対的に充分な卜ラッキング特性
を持たせることによりその変動を小さくできる。
The causes of these drifts are changes in the ambient temperature, fluctuations in the power supply used, changes in the component constants at light times, etc. In particular, the fluctuation of f C is greatly drifted due to these factors. On the other hand, K V can be determined by the relative accuracy of the components of the circuit, and its variation can be reduced by providing a relatively sufficient racking characteristic even though there is no absolute accuracy of the element value by semiconductor integrated circuit technology or the like. it can.

【0008】本発明は従来の電圧制御発振回路のドリフ
卜を押える回路方式に関するものであって回路の構成部
品の定数のばらつき変動による発振回路の定数(fC
V)の変動を小さくし回路の安定性を増大することに
ある。
The present invention relates to a circuit system that suppresses the drift of a conventional voltage controlled oscillator circuit, and the oscillator circuit constant (f C ,
The purpose is to reduce the fluctuation of K V ) and increase the stability of the circuit.

【0009】本発明の他の目的は回路定数の絶対精度に
対しての変動を抑えることにより集積回路化しやすい電
圧制御発振回路を提供することにある。
Another object of the present invention is to provide a voltage controlled oscillator circuit which can be easily integrated into an integrated circuit by suppressing the fluctuation of the circuit constant with respect to the absolute accuracy.

【0010】[0010]

【課題を解決するための手段】本発明の電圧制御発振回
路は、第1の合成信号により発振周波数が制御される第
1の電圧制御発振器と、前記第1の電圧制御発振器と同
等の特性を有し第2の合成信号により発振周波数が制御
される第2の電圧制御発振器、前記電圧制御発振回路の
出力の位相と基準信号の位相を比較する比較回路を有す
る位相固定ループとを備える電圧制御発振回路であっ
て、第1の制御信号と、前記比較回路より出力される第
2の制御信号とをそれぞれ電流に変換して加算し前記第
1の合成信号を出力する第1の信号加算回路と、前記第
2の制御信号と基準電圧とをそれぞれ電流に変換して加
算し前記第2の合成信号を出力する第2の信号加算回路
とを有することを特徴とする。
A voltage-controlled oscillator circuit according to the present invention has a first voltage-controlled oscillator whose oscillation frequency is controlled by a first synthesized signal and a characteristic equivalent to that of the first voltage-controlled oscillator. A second voltage-controlled oscillator having an oscillation frequency controlled by the second combined signal; and a phase-locked loop having a comparison circuit for comparing the phase of the output of the voltage-controlled oscillation circuit with the phase of the reference signal. An oscillating circuit, which is a first signal adding circuit for converting a first control signal and a second control signal output from the comparison circuit into currents and adding the currents to output the first combined signal. And a second signal adder circuit for converting the second control signal and the reference voltage into currents, adding the currents, and outputting the second combined signal.

【0011】[0011]

【発明の実施の形態】図1は、本発明の概念を示す図で
ある。101,103は同一の特性を有する様に設計さ
れた信号合成手段で例えば端子109に与えられる信号
(以下、電圧値として話をすすめる。電流値、電荷値等
他の物理量でも話は同じである。)をV11、端子110
に加わる信号電圧をV21、信号合成手段101の出力端
子114にあらわれる電圧をV01とすると V01=f(V11,V21)・・・・・(3) fは任意関数の様な特性を有する回路である。以下、簡
単のために V01=aV11+bV21+C・・・・(4) とする。(a,b,Cは定数) 同様端子111、端子112に加えられる電圧をそれぞ
れV12,V22,とし信号合成手段103の出力端子11
5の電圧をV02としたとき V02=aV12+bV22十C・・・・(5) とする。102,104は特性のそろった電圧制御発振
回路であり出力情号の周波数F1 ,F2 は F1 =KV 01+d・・・・・・・(6) F2 =KV 02+d・・・・・・・(7) とする(dは定数).107は位相比較回路で電圧制御
発振回路104の出力と安定な周波数の発振をする発振
回路(例えば水晶発振回路)の出力信号と位相比較をし
その位相差に比較した量の信号を出力する。105はロ
ーパスフィルタ(LPF)で位相比較回路の出力から希
望する信号成分のみをとり出すために通常入れられる。
1 is a diagram showing the concept of the present invention. Reference numerals 101 and 103 denote signal synthesizing means designed to have the same characteristics. For example, a signal given to the terminal 109 (hereinafter, referred to as a voltage value. The same applies to other physical quantities such as a current value and a charge value. .) To V 11 , terminal 110
V 21 a signal voltage applied to, when the voltage appearing at the output terminal 114 of the signal combining means 101 and V 01 V 01 = f (V 11, V 21) ····· (3) f is such as arbitrary function It is a circuit having characteristics. Hereinafter, for the sake of simplicity, it is assumed that V 01 = aV 11 + bV 21 + C ... (4). (A, b, C are constants) Similarly, the voltages applied to the terminals 111 and 112 are V 12 and V 22 , respectively, and the output terminal 11 of the signal synthesizing means 103.
When the voltage of 5 is V 02 , V 02 = aV 12 + bV 22 +10 C ... (5). Reference numerals 102 and 104 denote voltage controlled oscillator circuits having uniform characteristics, and the output signal frequencies F 1 and F 2 are F 1 = K V V 01 + d (6) F 2 = K V V 02 + D ... (7) (d is a constant). Reference numeral 107 denotes a phase comparison circuit, which compares the output of the voltage controlled oscillation circuit 104 with the output signal of an oscillation circuit (for example, a crystal oscillation circuit) that oscillates at a stable frequency, and outputs a signal of an amount compared with the phase difference. Reference numeral 105 is a low-pass filter (LPF), which is normally inserted in order to extract only a desired signal component from the output of the phase comparison circuit.

【0012】LPF105の出力は第2の信号合成回路
103の第2の入力端子112に負帰還する。すなわち
第2の電圧制御発振回路104、位相比較回路106、
LPF105、信号台成手段103はPLLを構成し第
2の電圧制御発振回路の発振周波数は発振回路107の
発振周波数frefと等しくなる。電圧制御発振回路1
04の出力周波数は位相比較回路106、LPF105
の特性によりfrefと位相まで完全に一致させること
もできるし、またfrefの突発的な変化に対しては追
従しない様にすることもできる。発振回路107は通
常、充分安定な発振をする回路を用いるので系の応答を
速くしても問題はない。また電圧制御発振回路104の
出力周波数とfrefは周波数のみ追従し、位相は誤差
があつてもよいから回路の構成はかなり自由度がある。
発振回路107が不安定でジッタ等を有する時は設計に
よりその影響を軽減できる。
The output of the LPF 105 is negatively fed back to the second input terminal 112 of the second signal synthesis circuit 103. That is, the second voltage controlled oscillator circuit 104, the phase comparison circuit 106,
The LPF 105 and the signal generating means 103 constitute a PLL, and the oscillation frequency of the second voltage controlled oscillation circuit becomes equal to the oscillation frequency fref of the oscillation circuit 107. Voltage controlled oscillator circuit 1
The output frequency of 04 is the phase comparison circuit 106 and the LPF 105.
It is possible to make fref and the phase completely coincide with each other by the characteristic of, and it is also possible not to follow a sudden change of fref. Since the oscillator circuit 107 normally uses a circuit that oscillates sufficiently stably, there is no problem even if the response of the system is fast. Further, the output frequency of the voltage controlled oscillator circuit 104 and fref follow only the frequency, and there may be an error in the phase, so there is considerable freedom in the configuration of the circuit.
When the oscillator circuit 107 is unstable and has a jitter or the like, its influence can be reduced by design.

【0013】さて、電源電圧の変動、温度特性、経時変
化等により電圧制御発振回路104のフリーラン周波数
が変動した場合を考えよう。このとき系は自動的に端子
112に加わる電圧を上げ下げして電圧制御発振回路1
04の発振周波数はfrefを保つ。また第2の信号合
成手段103の第1の制御端子111に任意の電圧値を
与えた場合もその電圧値にかかわらず第2の電圧制御発
振回路の発振周波数はfrefとなる様、端子112の
電圧は自動的に調整される。
Now, let us consider a case where the free-run frequency of the voltage controlled oscillator circuit 104 fluctuates due to fluctuations in the power supply voltage, temperature characteristics, changes over time, and the like. At this time, the system automatically raises and lowers the voltage applied to the terminal 112 to change the voltage controlled oscillation circuit 1
The oscillation frequency of 04 keeps fref. Further, even if an arbitrary voltage value is given to the first control terminal 111 of the second signal synthesizing means 103, the oscillation frequency of the second voltage controlled oscillator circuit becomes fref regardless of the voltage value. The voltage is adjusted automatically.

【0014】従って、第2の信号合成回路の第1の入力
端子111に基準となる電圧Vsを与えると第2の入力
端子112は自動的にレべル調整され電圧制御発振回路
104の発振周波数frefに等しくなる。図1に示す
様に第2の信号合成手段103の第2の入力端子112
の電圧を第1の信号合成手段101の第2の入力端子1
10にも与えると第1、第2の信号合成手段、電圧制御
発振回路はそれぞれ特性がそろっているので第1の電圧
制御発振回路102の発振周波数は第1の信号合成手段
101の第1の入力端子109に与えられる電圧がVS
のときfrefとなる。frefを希望するフリーラン
周波数fC に等しく設定しておけば端子109の電圧が
S のとき電圧制御発振回路102の発振周波数はfC
となる。従って図1の回路全体を端子109を制御端
子、113を出力端子とする電圧制御発振回路とすれば
フリーラン周波数がfC の電圧制御回路を実現できたこ
とになる。回路内の2つの信号合成手段101,10
3、電圧制御発振回路102,104の持性は等しいと
仮定して議論をしてきたが、この仮定は極めて妥当なも
のである。特にモノシリック集積回路化した場合、各々
は数ミリ角のチップ上に高精度で対称性よく作り込むこ
とができる。各々の回路は同時に製造されるため経時変
化があったとしても同一の経過時間であり持性が各々で
異なってくることは少ない。また電源電圧や温度変化に
対しても同一の電源にて使用されるし、また、きわめて
近い場所に配置されているため双方に温度差を生じ特性
が異なってくることも少ない。集積回路の設計時に各々
の回路の対称性を充分配虜しておけば、各特性の変動は
互いにキャンセルしあってドリフトの少ない安定な電圧
制御発振回路を実現できる。
Therefore, when the reference voltage Vs is applied to the first input terminal 111 of the second signal synthesizing circuit, the second input terminal 112 is automatically level-adjusted and the oscillation frequency of the voltage controlled oscillator circuit 104 is adjusted. will be equal to fref. As shown in FIG. 1, the second input terminal 112 of the second signal combining means 103.
To the second input terminal 1 of the first signal combining means 101.
10, the characteristics of the first and second signal synthesizing means and the voltage controlled oscillator circuit are the same, so that the oscillation frequency of the first voltage controlled oscillator circuit 102 is the same as that of the first signal synthesizing means 101. The voltage applied to the input terminal 109 is V S
In case of, it becomes fref. If fref is set equal to the desired free-run frequency f C , the oscillation frequency of the voltage controlled oscillator circuit 102 is f C when the voltage at the terminal 109 is V S.
Becomes Therefore, if the entire circuit of FIG. 1 is a voltage controlled oscillator circuit having the terminal 109 as a control terminal and the terminal 113 as an output terminal, a voltage control circuit having a free-run frequency f C can be realized. Two signal combining means 101, 10 in the circuit
3. The discussion has been made on the assumption that the voltage-controlled oscillator circuits 102 and 104 have the same characteristics, but this assumption is extremely valid. In particular, in the case of forming a monolithic integrated circuit, each can be built on a chip of several millimeters square with high accuracy and good symmetry. Since each circuit is manufactured at the same time, even if there is a change over time, the same elapsed time is maintained and the sustainability is unlikely to differ from one another. Further, the same power source is used for the power supply voltage and the temperature change, and since they are arranged at extremely close places, it is unlikely that a temperature difference occurs between them and the characteristics are different. If the symmetry of each circuit is taken into consideration when designing the integrated circuit, the fluctuations of the respective characteristics cancel each other out and a stable voltage controlled oscillator circuit with less drift can be realized.

【0015】図2は以上の本発明の考え方にもとづき半
導体集積回路により実現できる電圧制御発振回路の具体
例を示す図である。201は信号合成回路で卜ランジス
タT1 及びT2 のゲー卜電圧を変えることにより各々の
ドレイン電流を変える。T1,T2 のドレイン電流は含
成(加算)され卜ランジスタT13に流れ込み電圧に変換
される。この電圧は第1の電圧制御発振回路の制御電圧
であり、MOS卜ランジスタで構成される電圧制御発振
回路202に入力される。この回路は卜ランジスタ
7 ,T10,T8 ,T11,・・・T9 ,T12により構成
される奇数段のインバータによりリングオシレータを構
成し、各々のトランジスタのソースさらにトランジスタ
4 ,T5 ・・・T6 ,T15,T16・・・T17を直列に
入れ、これ等のトランジスタのゲート電位を制御するこ
とによりリングオシレータに電源より流入する電流を制
御し発振周波数を制御するものである。本発明の例では
端子212,214の電位が低くなる程T13のドレイン
電圧(電圧制御発振回路202の制御電圧)が上昇し発
振周波数が上がる。すなわち(4)式においてa,bが
負、(6)式においてKV が正の場合である。端子21
2,214のレべルが高い時に高い周波数で発振させた
ければ例えば201,202の回路のトランジスタの極
性をすべて逆(PチャネルトランジスタをNチヤネル
に、NチャネルトランジスタをPチャネルに)にすれ
ば、a,bが負、KV が負となり達成できる。205,
206は出力を得るためのバッファ回路である。
FIG. 2 is a diagram showing a specific example of a voltage controlled oscillator circuit which can be realized by a semiconductor integrated circuit based on the above idea of the present invention. Reference numeral 201 denotes a signal synthesizing circuit, which changes the drain current of each of the transistor transistors T 1 and T 2 by changing the gate voltage thereof. The drain currents of T 1 and T 2 are included (added) and flow into the transistor T 13 to be converted into a voltage. This voltage is the control voltage of the first voltage controlled oscillator circuit, and is input to the voltage controlled oscillator circuit 202 composed of a MOS transistor. This circuit Bok transistor T 7, T 10, T 8 , T 11, ··· T 9, constitute a ring oscillator by an odd number of stages of the inverter constituted by the T 12, the source further transistor T 4 of each transistor, T 5 ··· T 6, T 15 , T 16 put · · · T 17 in series, controlling the oscillation frequency by controlling the current flowing from the power supply to the ring oscillator by controlling a gate potential of the transistor of this such To do. In the example of the present invention, the lower the potential of the terminals 212 and 214, the higher the drain voltage of T 13 (the control voltage of the voltage controlled oscillator circuit 202) and the higher the oscillation frequency. That is, this is the case where a and b are negative in the equation (4) and K V is positive in the equation (6). Terminal 21
If it is desired to oscillate at a high frequency when the level of 2,214 is high, for example, the polarities of the transistors of the circuits 201 and 202 are all reversed (P channel transistor is N channel, N channel transistor is P channel). , A, b are negative and K V is negative, which can be achieved. 205,
206 is a buffer circuit for obtaining an output.

【0016】203,204はそれぞれ201,202
と同様の回路構成を持つ信号合成回路、電圧制御発振回
路である。内部構成は同じなので図では内部を省略して
ある。第2の電圧制御発振回路の出力はパッファ207
を通し位相比較回路208に入力される。211は水晶
発振回路でフリーラン周波数の基準となる周波数fre
f(=fC )を発振する発振回路である。通常はこの信
号は位相比較回路208に入力され第2の電圧制御発振
回路204の出力と位相比較されるとともに他の回路の
タイミングクロック、システムクロックなどと共用され
る。もし他の回路の要求するクロック信号等の周波数と
希望するfC が異なる場合はノード219または218
の一方か双方に分周回路や周波数変換回路を入れること
により水晶発振回路211の発振周波数の整数倍、整数
分の1、それ等の差、整数分の整等にfC を設定するこ
とが可能である。分周回路や周波数変換回路はデジタル
回路で構成でき半導体集積回路化に際して何ら障害は生
じない。217はローパスフィルタで位相比較回路20
8の出力に含まれる高周波成分を除去する。出力は第2
の信号合成回路203の第2の入力端子215に帰還さ
れる。第1の入力端子213にはfC を発振させたい入
力信号レべル(基準レべル)を与えるべく電源電圧を分
圧する抵抗R11,R12が接続されている。抵抗は半導体
集積回路内に正確なものは作りにくいが相対精度は非常
に高く作ることが可能である。この端子には例えばツエ
ナーダイオードによる基準電圧等のもっと正確な電圧源
を接続しても良い。第1及び第2の信号の信号合成回路
の第2の入力端子214,215にはローパスフィルタ
217内部の異なったところから信号をとり出し接続し
ているが抵抗R4 はPLL系の安定化のために必要な抵
抗であって図1の場合と本質的に異なるものではない。
Reference numerals 203 and 204 denote 201 and 202, respectively.
The signal synthesizing circuit and the voltage controlled oscillating circuit have the same circuit configuration. Since the internal structure is the same, the inside is omitted in the figure. The output of the second voltage controlled oscillator circuit is the puffer 207.
Is input to the phase comparison circuit 208 through. Reference numeral 211 is a crystal oscillation circuit, which is a frequency fre which is a reference of the free-run frequency.
This is an oscillation circuit that oscillates f (= f C ). Normally, this signal is input to the phase comparison circuit 208 to be phase-compared with the output of the second voltage controlled oscillation circuit 204, and is also used as a timing clock or system clock for other circuits. If the frequency of the clock signal required by another circuit is different from the desired f C, the node 219 or 218
It is possible to set f C to an integral multiple of the oscillation frequency of the crystal oscillator circuit 211, an integer fraction, a difference between them, or an integer fraction adjustment by inserting a frequency dividing circuit or a frequency converting circuit in either one or both. It is possible. The frequency dividing circuit and the frequency converting circuit can be configured by digital circuits, and no trouble occurs when the semiconductor integrated circuit is formed. 217 is a low-pass filter, which is a phase comparison circuit 20.
The high frequency component included in the output of 8 is removed. Output is second
Is fed back to the second input terminal 215 of the signal combining circuit 203. The first input terminal 213 is connected to resistors R 11 and R 12 that divide the power supply voltage to give an input signal level (reference level) for oscillating f C. It is difficult to make an accurate resistor in the semiconductor integrated circuit, but the relative accuracy can be made very high. A more accurate voltage source such as a reference voltage by a Zener diode may be connected to this terminal. Signals are taken out from different points inside the low-pass filter 217 and connected to the second input terminals 214 and 215 of the signal combining circuit for the first and second signals, but the resistor R 4 stabilizes the PLL system. The resistance required for this purpose is not essentially different from the case of FIG.

【0017】図2の構成を見ると抵抗R11〜R15、コン
デンサC11〜C13、水晶発振子Xを除けばすべてMOS
卜ランジスタで構成されている。抵抗、コンデンサは絶
対精度が要求されることは無い。従って抵抗は半導体集
積回路に内蔵できる。また必要とする発振周波数のレン
ジによっても異なるがコンデンサC11も内蔵が可能であ
ることが多い。低い周波数が必要なときは出力端子21
6に分周回路を接続することにより、PLL系は高い周
波数で発振させておけばC1 も小容量で済み集積回路化
が容易となる。
Looking at the configuration of FIG. 2, all are MOS except resistors R 11 to R 15 , capacitors C 11 to C 13 , and a crystal oscillator X.
It is composed of a land transistor. Absolute accuracy is not required for resistors and capacitors. Therefore, the resistor can be built in the semiconductor integrated circuit. Also, although it depends on the required oscillation frequency range, the capacitor C 11 can often be incorporated. Output terminal 21 when low frequency is required
By connecting the frequency divider circuit to 6, the PLL system can be made to oscillate at a high frequency so that C 1 can have a small capacity and an integrated circuit can be easily formed.

【0018】以上述べた様に本発明によれば高精度部品
を用いることなくきわめて安定な電圧制御発振回路を実
現できる。高精度の部品を用いる必要が無いから半導体
集積回路化がきわめて容易となり実装上、製造上のメリ
ッ卜が大きい。
As described above, according to the present invention, an extremely stable voltage controlled oscillator circuit can be realized without using high precision parts. Since it is not necessary to use high-precision parts, it is extremely easy to make a semiconductor integrated circuit, and mounting and manufacturing have a great deal of merit.

【0019】本発明による例(図1,2)と従来例(図
3,4)を比較すると本発明の方がかなり複雑になって
おり従来例に比較してあまリメリットが無い様に思われ
るかも知れない。しかし事実は逆なのであって半導体集
積回路上に図2の回路を構成する場合そのチップ上に占
める面積はわずかである。図4の従来例の様に外付部品
を必要とするときは半導体集積回路上のボンディングバ
ッドの面積や出力卜ランジスタ(例えば図4のコンデン
サC1 (外付)を駆動するP4 ,P5 ,N2 ,N3 、抵
抗R1 ,R2 (外付)を駆動するP1 ,N1 )に大きな
ものが必要となりそれ等の占める面積の方が本発明の回
路に比べはるかに大きくなっているのである。また本発
明では水晶発振回路の様な安定な発振回路を必要とする
が、通常大規模集積回路では電圧制御発振回路の他に安
定な基準パルス列が必要な場合が多く、これと共用すれ
ば良いので本発明を実施するにあたって障害とはならな
い。また本発明では図1のノード116または117、
図2のノード218,219に直列な分周回路または周
波数変換回路を入れ、その分周比等を論理回路で制御す
ることにより同一の回路で任意にフリーラン周波数を設
定することができる。
Comparing the example according to the present invention (FIGS. 1 and 2) with the conventional example (FIGS. 3 and 4), the present invention is considerably complicated, and it seems that there is no merit compared with the conventional example. May be done. However, the fact is the opposite, and when the circuit of FIG. 2 is formed on the semiconductor integrated circuit, the area occupied on the chip is small. When external components are required as in the conventional example of FIG. 4, the area of the bonding pad on the semiconductor integrated circuit and the output transistor (for example, P 4 and P 5 for driving the capacitor C 1 (external) of FIG. 4) are used. , N 2 , N 3 , and P 1 , N 1 for driving the resistors R 1 , R 2 (external) are required to be large, and the area occupied by them is much larger than that of the circuit of the present invention. -ing Further, although the present invention requires a stable oscillation circuit such as a crystal oscillation circuit, a large-scale integrated circuit usually requires a stable reference pulse train in addition to the voltage controlled oscillation circuit, and it may be used together with this. Therefore, it does not hinder the implementation of the present invention. In the present invention, the node 116 or 117 of FIG.
By inserting a frequency dividing circuit or a frequency converting circuit in series in the nodes 218 and 219 of FIG. 2 and controlling the frequency dividing ratio and the like by a logic circuit, the free running frequency can be arbitrarily set in the same circuit.

【0020】[0020]

【発明の効果】この様に本発明は集積回路の容易な電圧
制御発振回路を安定化する方法を示し、デジタル集積回
路にも容易に組込める電圧制御発振回路を示した。本発
明を実施すればコス卜、実装スペースを減少でき機器を
実現していく上で大いに貢献できる。
As described above, the present invention shows a method for stabilizing an easy voltage controlled oscillator circuit of an integrated circuit, and a voltage controlled oscillator circuit which can be easily incorporated in a digital integrated circuit. By implementing the present invention, the cost and the mounting space can be reduced, and it can greatly contribute to the realization of a device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例を示す図。FIG. 1 is a diagram showing an embodiment of the present invention.

【図2】本発明の実施例を示す図。FIG. 2 is a diagram showing an embodiment of the present invention.

【図3】従来の電圧制御発振回路を示す図である。FIG. 3 is a diagram showing a conventional voltage controlled oscillator circuit.

【図4】従来の電圧制御発振回路を示す図である。FIG. 4 is a diagram showing a conventional voltage controlled oscillator circuit.

【符号の説明】[Explanation of symbols]

101.201 第1の信号合成回路 103,203 第2の信号合成回路 102,202 第1の電圧制御発振回路 104,204 第2の電圧制御発振回路 106,208 位相比較回路 105,217 ローパスフイルタ 107,211 基準周波数発振回路 109,212 第1の信号合成回路の第1の入力端
子。制御端子 110,214 第1の信号合成回路の第2の入力端子 111,213 第2の信号合成回路の第1の入力端子 112,215 第2の信号合成回路の第2の入力端子 113,216 出力端子
101.201 first signal synthesizing circuit 103,203 second signal synthesizing circuit 102,202 first voltage control oscillating circuit 104,204 second voltage control oscillating circuit 106,208 phase comparator circuit 105,217 low-pass filter 107 , 211 Reference frequency oscillation circuits 109, 212 First input terminals of the first signal synthesis circuit. Control terminals 110, 214 Second input terminals of first signal combining circuit 111, 213 First input terminals of second signal combining circuit 112, 215 Second input terminals of second signal combining circuit 113, 216 Output terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 第1の合成信号により発振周波数が制御
される第1の電圧制御発振器と、 前記第1の電圧制御発振器と同等の特性を有し第2の合
成信号により発振周波数が制御される第2の電圧制御発
振器、前記電圧制御発振回路の出力の位相と基準信号の
位相を比較する比較回路を有する位相固定ループとを備
える電圧制御発振回路であって、 第1の制御信号と、前記比較回路より出力される第2の
制御信号とをそれぞれ電流に変換して加算し前記第1の
合成信号を出力する第1の信号加算回路と、 前記第2の制御信号と基準電圧とをそれぞれ電流に変換
して加算し前記第2の合成信号を出力する第2の信号加
算回路とを有することを特徴とする電圧制御発振回路。
1. A first voltage-controlled oscillator whose oscillation frequency is controlled by a first synthesized signal; and an oscillation frequency which is controlled by a second synthesized signal and has characteristics equivalent to those of the first voltage-controlled oscillator. A voltage-controlled oscillator circuit comprising: a second voltage-controlled oscillator; and a phase-locked loop having a comparator circuit for comparing the phase of the output of the voltage-controlled oscillator circuit with the phase of the reference signal, the first control signal comprising: A first signal addition circuit that converts the second control signal output from the comparison circuit into a current and adds the current to output the first combined signal; and the second control signal and the reference voltage. And a second signal adding circuit for converting the currents into currents, adding the currents, and outputting the second combined signal.
JP8155247A 1996-06-17 1996-06-17 Voltage controlled oscillator Expired - Lifetime JP2737747B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8155247A JP2737747B2 (en) 1996-06-17 1996-06-17 Voltage controlled oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8155247A JP2737747B2 (en) 1996-06-17 1996-06-17 Voltage controlled oscillator

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3018748A Division JPH0770999B2 (en) 1991-02-12 1991-02-12 Voltage controlled oscillator

Publications (2)

Publication Number Publication Date
JPH0936736A true JPH0936736A (en) 1997-02-07
JP2737747B2 JP2737747B2 (en) 1998-04-08

Family

ID=15601756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8155247A Expired - Lifetime JP2737747B2 (en) 1996-06-17 1996-06-17 Voltage controlled oscillator

Country Status (1)

Country Link
JP (1) JP2737747B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010268223A (en) * 2009-05-14 2010-11-25 Nippon Telegr & Teleph Corp <Ntt> Clock data reproduction circuit
JP2010288255A (en) * 2009-05-14 2010-12-24 Nippon Telegr & Teleph Corp <Ntt> Clock data reproducing circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5494261A (en) * 1977-12-30 1979-07-25 Ibm Variable frequency oscillating system
JPS56110306A (en) * 1980-02-05 1981-09-01 Nippon Telegr & Teleph Corp <Ntt> Voltage control type oscillator for pll frequency synthesizer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5494261A (en) * 1977-12-30 1979-07-25 Ibm Variable frequency oscillating system
JPS56110306A (en) * 1980-02-05 1981-09-01 Nippon Telegr & Teleph Corp <Ntt> Voltage control type oscillator for pll frequency synthesizer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010268223A (en) * 2009-05-14 2010-11-25 Nippon Telegr & Teleph Corp <Ntt> Clock data reproduction circuit
JP2010288255A (en) * 2009-05-14 2010-12-24 Nippon Telegr & Teleph Corp <Ntt> Clock data reproducing circuit
JP2010288257A (en) * 2009-05-14 2010-12-24 Nippon Telegr & Teleph Corp <Ntt> Clock data reproducing circuit
JP2010288256A (en) * 2009-05-14 2010-12-24 Nippon Telegr & Teleph Corp <Ntt> Clock data reproducing circuit
JP2013034267A (en) * 2009-05-14 2013-02-14 Nippon Telegr & Teleph Corp <Ntt> Clock-data regeneration circuit

Also Published As

Publication number Publication date
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