JPH0936414A - Light emitting/receiving element and fabrication thereof - Google Patents

Light emitting/receiving element and fabrication thereof

Info

Publication number
JPH0936414A
JPH0936414A JP18415095A JP18415095A JPH0936414A JP H0936414 A JPH0936414 A JP H0936414A JP 18415095 A JP18415095 A JP 18415095A JP 18415095 A JP18415095 A JP 18415095A JP H0936414 A JPH0936414 A JP H0936414A
Authority
JP
Japan
Prior art keywords
diffusion
light
light emitting
substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18415095A
Other languages
Japanese (ja)
Other versions
JP3126632B2 (en
Inventor
Masumi Yanaka
真澄 谷中
Mitsuhiko Ogiwara
光彦 荻原
Masaharu Nobori
正治 登
Hiroyuki Fujiwara
博之 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP18415095A priority Critical patent/JP3126632B2/en
Publication of JPH0936414A publication Critical patent/JPH0936414A/en
Application granted granted Critical
Publication of JP3126632B2 publication Critical patent/JP3126632B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To obtain a light emitting/receiving element, and a fabrication method thereof, in which high light emitting quantity and light receiving quantity can be attained with high efficiency. SOLUTION: A Zn doped P type diffusion region 2 is formed on an N type GaAsP or N type GaAlAs epitaxial substrate 1 thus forming a PN junction closely to the end face of substrate and the driving voltage is switched to emit light or receive light.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、受発光素子及びその製
造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting / receiving element and a method for manufacturing the same.

【0002】[0002]

【従来の技術】従来より、電子写真方式の複写機、プリ
ンタ、スキャナーあるいはファクシミリやこれらの複合
機が備える露光光源およびイメージセンサとして、種々
のものが提案されている。例えば、特開昭56−122
069号公報及び特開昭58−157252号公報に開
示されているものでは、LED(Light Emit
ting Diode)アレイを露光光源及びイメージ
センサの双方に用いる。
2. Description of the Related Art Hitherto, various types of exposure light sources and image sensors have been proposed for an electrophotographic copying machine, a printer, a scanner, a facsimile or a composite machine of these. For example, JP-A-56-122
In the devices disclosed in JP-A-069 and JP-A-58-157252, an LED (Light Emit) is disclosed.
toning diode array is used for both the exposure light source and the image sensor.

【0003】これは、LEDのPN接合に順方向電圧を
印加してキャリアを注入すれば、キャリアの再結合によ
り発光を生じ、またLEDのPN接合に逆方向電圧を印
加して光を照射すれば、キャリアの生成により光電流が
得られるという点に着目して、LEDアレイを露光光源
及びイメージセンサの双方に利用するものである。前記
露光光源及びイメージセンサにおいては、上面発光型L
EDが使用されていた。
This is because if a forward voltage is applied to the PN junction of an LED to inject carriers, light is emitted by recombination of the carriers, and a reverse voltage is applied to the PN junction of the LED to irradiate light. For example, the LED array is used as both an exposure light source and an image sensor, paying attention to the fact that a photocurrent can be obtained by generating carriers. In the exposure light source and the image sensor, the top emission type L
The ED was being used.

【0004】[0004]

【発明が解決しようとする課題】従来の上面発光型LE
Dの作製に当たっては、一般に、基板上に拡散マスクを
形成し、拡散マスクの拡散窓を介し不純物を選択的に拡
散させてPN接合を形成する。この際、拡散窓内側の全
面にわたって一様な深さを有する深いPN接合を形成す
るが、不純物のサイド拡散により、拡散窓外側の窓周縁
部分の狭い線状領域に浅いPN接合が形成される。
Conventional Top-Emitting LE
In manufacturing D, a diffusion mask is generally formed on a substrate, and impurities are selectively diffused through a diffusion window of the diffusion mask to form a PN junction. At this time, a deep PN junction having a uniform depth is formed over the entire surface inside the diffusion window, but a shallow PN junction is formed in a narrow linear region on the window peripheral portion outside the diffusion window due to side diffusion of impurities. .

【0005】前記上面発光型LEDでは、拡散深さ(X
j と記す)と発光強度の関係は、図27に示すように、
あるXj maxなる拡散深さaまで発光強度は増加し、
jmaxをピークに発光強度は減少する。ただし、作
製方法の違いにより、Xj maxに多少の差異がある
が、この傾向は一般的に成り立つ。
In the top emitting LED, the diffusion depth (X
As shown in FIG. 27, the relationship between j ) and the emission intensity is
The emission intensity increases up to a certain diffusion depth a of X j max,
The emission intensity decreases at the peak of X j max. However, although there is some difference in X j max due to the difference in the manufacturing method, this tendency generally holds.

【0006】一方、拡散深さXj と受光感度の関係は、
図28に示すように、Xj が減少するにつれて受光感度
は増加する。ここで、受光感度の測定は、赤文字の原稿
読み取りに適した550nmの照射光で行った。以上述
べたように、上面発光型LEDで効率よく受発光を行う
場合には、発光強度が最大になるようなXj max、ま
た受光感度が最大になるようなXj にしなければならな
いため、1つの素子で受発光を効率よく行うことは不可
能であった。
On the other hand, the relationship between the diffusion depth X j and the photosensitivity is
As shown in FIG. 28, the light receiving sensitivity increases as X j decreases. Here, the measurement of the light receiving sensitivity was performed with the irradiation light of 550 nm suitable for reading the manuscript of red characters. As described above, since in the case of performing efficiently receiving and emitting light in top-emitting LED is, X j max as luminous intensity becomes the maximum, also the light receiving sensitivity must be X j that maximizes, It was impossible to efficiently receive and emit light with one device.

【0007】また、上面発光型LEDは1チップのサイ
ズも大きくなるため、コストも高くなるという問題が生
じた。そこで、発光及び受光効率が高く、かつ小型で低
コストプロセスが可能な端面発光型LEDを受発光素子
として用いることを試みた。ところが、発光に関しては
発光径が小さいため、上面発光型LEDと同程度の発光
径を得るためには、露光時間を長くする必要があり、受
光に関しては受光面積が小さいため、照射光に対する十
分な信号が得られないという問題が生じた。
Further, since the size of one chip of the top emission type LED becomes large, there is a problem that the cost becomes high. Therefore, an attempt was made to use an edge emitting LED as a light emitting / receiving element, which has high light emitting and light receiving efficiency and is small in size and capable of a low cost process. However, since the emission diameter is small with respect to light emission, it is necessary to lengthen the exposure time in order to obtain the same emission diameter as that of the top-emission LED, and the light receiving area is small with respect to light reception, which is sufficient for the irradiation light. There was a problem that no signal was obtained.

【0008】そこで、本発明は、上記問題点を除去し、
受発光効率が高く、且つ十分な発光量及び受光量を得る
ことができる受発光素子及びその製造方法を提供するこ
とを目的とする。
Therefore, the present invention eliminates the above problems,
It is an object of the present invention to provide a light emitting and receiving element which has high light receiving and emitting efficiency and which can obtain a sufficient amount of emitted light and an amount of received light, and a method for manufacturing the same.

【0009】[0009]

【課題を解決するための手段】本発明は、上記目的を達
成するために、 (1)第1導電型の化合物半導体基板に第2導電型の不
純物を拡散させてなる拡散層を具えた受発光素子におい
て、基板端面近傍に形成されたPN接合で駆動電圧の切
り換えにより基板端面側から発光または受光させるよう
にしたものである。
In order to achieve the above object, the present invention provides (1) a receiving layer comprising a diffusion layer formed by diffusing impurities of a second conductivity type into a compound semiconductor substrate of a first conductivity type. In the light emitting element, a PN junction formed in the vicinity of the end face of the substrate is adapted to emit light or receive light from the end face side of the substrate by switching the drive voltage.

【0010】(2)上記(1)記載の受発光素子におい
て、前記基板端面近傍において、第1導電型領域の一部
分を残留させるようにしたものである。 (3)上記(1)記載の受発光素子において、前記PN
接合が相対向する基板の両端面近傍に延在して設けら
れ、一方の基板端面近傍に位置するPN接合で受光を行
い、もう一方の基板端面近傍に位置するPN接合で発光
させるようにしたものである。
(2) In the light emitting and receiving element according to the above (1), a part of the first conductivity type region is left in the vicinity of the end face of the substrate. (3) In the light emitting / receiving element according to the above (1), the PN
The junctions are provided so as to extend near both end faces of the opposing substrates, and light is received by a PN junction located near one of the substrate end faces and emitted by a PN junction located near the other substrate end face. It is a thing.

【0011】(4)上記(3)記載の受発光素子におい
て、発光部の拡散深さに対して受光部の拡散深さが深く
なるようにしたものである。 (5)上記(1)、(2)、(3)又は(4)記載の受
発光素子において、基板主面からの拡散深さに基づいて
基板端面近傍に形成するPN接合の基板端面側から見た
面積を制御し、発光量または受光量を制御するようにし
たものである。
(4) In the light emitting / receiving element described in (3) above, the diffusion depth of the light receiving portion is deeper than the diffusion depth of the light emitting portion. (5) In the light emitting / receiving element according to (1), (2), (3) or (4) above, from the substrate end face side of a PN junction formed near the substrate end face based on the diffusion depth from the substrate main surface. The amount of light emission or the amount of light reception is controlled by controlling the viewed area.

【0012】(6)第1導電型の化合物半導体基板に第
2導電型の不純物を拡散させた受発光素子の製造方法に
おいて、第1導電型の化合物半導体基板上に拡散防止膜
を積層する工程と、前記拡散防止膜に拡散窓を形成し、
露出させた第1導導電型の領域を拡散制御膜で覆い、前
記拡散制御膜を介し不純物を拡散して、第2導電型の拡
散領域を形成する工程と、基板端面近傍において第1導
電型領域の一部分が残留するように、前記第2導電型の
拡散領域に隣接した第1導電型の化合物半導体基板を部
分的にエッチングする工程とを施すようにしたものであ
る。
(6) A step of laminating a diffusion barrier film on the first conductivity type compound semiconductor substrate in the method for manufacturing a light receiving and emitting device in which the impurities of the second conductivity type are diffused in the first conductivity type compound semiconductor substrate. And forming a diffusion window in the diffusion prevention film,
A step of covering the exposed region of the first conductivity type with a diffusion control film, diffusing impurities through the diffusion control film to form a diffusion region of the second conductivity type, and the first conductivity type near the end face of the substrate. And a step of partially etching the compound semiconductor substrate of the first conductivity type adjacent to the diffusion region of the second conductivity type so that a part of the region remains.

【0013】(7)第1導電型の化合物半導体基板に第
2導電型の不純物を拡散させた受発光素子の製造方法に
おいて、第1導電型の化合物半導体基板上に拡散防止膜
を積層する工程と、前記拡散防止膜に拡散窓を形成し、
第1導電型の領域を露出させる工程と、その露出させた
第1導電型の領域における拡散深さを浅くする領域と深
くする領域とをともに拡散制御膜で覆い、しかもその拡
散制御膜の膜厚を拡散深さを浅く形成する領域上では厚
く、拡散深さを深く形成する領域上では薄くする工程
と、前記拡散制御膜を介し不純物を拡散して、拡散深さ
が浅い第2導電型の第1拡散領域および拡散深さが深い
第2導電型の第2拡散領域を形成する工程と、基板端面
近傍において第2導電型領域の一部分が残留するよう
に、前記第2導電型の拡散領域に隣接した第1導電型の
化合物半導体基板を部分的にエッチングする工程とを施
すようにしたものである。
(7) In a method of manufacturing a light emitting / receiving device in which a second conductivity type impurity is diffused in a first conductivity type compound semiconductor substrate, a step of laminating a diffusion barrier film on the first conductivity type compound semiconductor substrate. And forming a diffusion window in the diffusion prevention film,
Both the step of exposing the region of the first conductivity type and the region of making the diffusion depth in the exposed region of the first conductivity type shallow and the region of making the diffusion depth deep are covered with a diffusion control film, and the film of the diffusion control film is formed. A second conductivity type in which the diffusion depth is shallow and the impurity is diffused through the diffusion control film to make the diffusion layer thicker on the region where the diffusion depth is formed shallower and thin on the region where the diffusion depth is formed deeper. Forming a first diffusion region and a second diffusion region of the second conductivity type having a deep diffusion depth, and diffusing the second conductivity type so that a part of the second conductivity type region remains in the vicinity of the end face of the substrate. And a step of partially etching the first conductivity type compound semiconductor substrate adjacent to the region.

【0014】[0014]

【作用】[Action]

(1)請求項1記載の受発光素子によれば、基板端面近
傍に形成されたPN接合で駆動電圧の切り換えにより、
受光又は発光させる構造にしたので、光吸収層の影響を
受けることなく、単体の素子で受発光することができ
る。 (2)請求項2記載の受発光素子によれば、前記基板端
面近傍において、ホールの拡散層及び空乏層領域が形成
される領域である基板の一部のみを残留させるようにし
たので、光吸収層の影響をほとんど受けることなく、基
板端面方向で形成させたPN接合で受発光させることが
できる。
(1) According to the light emitting and receiving element of the first aspect, by switching the drive voltage at the PN junction formed near the end face of the substrate,
Since the structure is such that it receives or emits light, a single element can receive and emit light without being affected by the light absorption layer. (2) According to the light emitting / receiving element of the second aspect, in the vicinity of the end face of the substrate, only a part of the substrate, which is a region where the diffusion layer and the depletion layer region of the hole are formed, is left. The PN junction formed in the end face direction of the substrate can receive and emit light with almost no influence of the absorption layer.

【0015】(3)請求項3記載の受発光素子によれ
ば、前記PN接合が相対向する基板の両端面近傍に延在
して設けられ、一方の基板端面近傍に位置するPN接合
で受光を行い、もう一方のPN接合で発光させるように
したので、単体の素子で受発光することができるととも
に、発光部と受光部の条件を変えることができる。
(3) According to the light emitting and receiving element of the third aspect, the PN junction is provided so as to extend near both end faces of the opposing substrates, and the PN junction located near one end face of the substrate receives light. Since the light is emitted from the other PN junction, the single element can receive and emit light, and the conditions of the light emitting portion and the light receiving portion can be changed.

【0016】(4)請求項4記載の受発光素子によれ
ば、発光部の拡散深さに対して受光部の拡散深さが深く
なるようにしたので、発光部に対して受光部として使用
するPN接合面積を増加させ、受光量を増加させること
ができる。 (5)請求項5記載の受発光素子によれば、基板主面か
らの拡散深さに基づいて基板端面近傍に形成するPN接
合の基板端面側から見た面積を制御し、発光量及び受光
量を制御するようにしたので、最適な発光量と受光量を
得ることができる。
(4) According to the light receiving and emitting device of the fourth aspect, since the diffusion depth of the light receiving portion is deeper than the diffusion depth of the light emitting portion, the light emitting portion is used as a light receiving portion. It is possible to increase the PN junction area and increase the amount of received light. (5) According to the light emitting / receiving element of the fifth aspect, the area of the PN junction formed in the vicinity of the substrate end face viewed from the substrate end face side is controlled based on the diffusion depth from the substrate main surface, and the light emission amount and the light receiving amount are received. Since the amount is controlled, it is possible to obtain the optimal light emission amount and light reception amount.

【0017】(6)請求項6記載の受発光素子の製造方
法によれば、エッチングにより形成された基板端面近傍
のPN接合を受発光部として使用するため、光吸収層の
影響を受けずに受発光できるとともに、サイズを小さ
く、しかも製造コストの低減を図ることができる。 (7)請求項7記載の受発光素子の製造方法によれば、
上記(6)の効果に加え、発光部側に比して、受光部側
のPN接合面積が大きくなるように形成することがで
き、受光量を増加させることができる。
(6) According to the method for manufacturing a light emitting and receiving element of the sixth aspect, since the PN junction near the end face of the substrate formed by etching is used as the light receiving and emitting portion, it is not affected by the light absorbing layer. It is possible to receive and emit light, have a small size, and reduce the manufacturing cost. (7) According to the method for manufacturing a light emitting and receiving element of claim 7,
In addition to the effect of (6) above, the PN junction area on the light receiving portion side can be formed to be larger than that on the light emitting portion side, and the light receiving amount can be increased.

【0018】[0018]

【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の第1実施例を示
す受発光素子の構成図であり、図1(a)はその受発光
素子の斜視図、図1(b)はその受発光素子の上面図、
図1(c)は図1(a)のA−A線断面図、図1(d)
はその受発光素子の正面図である。
Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a light emitting / receiving element showing a first embodiment of the present invention, FIG. 1 (a) is a perspective view of the light emitting / receiving element, and FIG. 1 (b) is a top view of the light receiving / emitting element.
1C is a sectional view taken along the line AA of FIG. 1A, and FIG.
FIG. 4 is a front view of the light emitting / receiving element.

【0019】ここで、1はN型GaAsP又はN型Ga
AlAsエピタキシャル基板(以下、単に基板とい
う)、2はZnドープのP型拡散領域、3はAl2 3
からなる拡散防止膜、4はAlからなるP側電極、5は
Au合金からなるN側電極である。図1に示すように、
この実施例の受発光素子は、N型エピタキシャル層上に
拡散防止膜3を設け、そこに拡散窓を介してZnドープ
のP型不純物を拡散して、P型拡散領域2を形成し、そ
れによりPN接合を形成し、さらに基板1の端面をエッ
チングし、P型拡散領域2と基板端面の近傍に存在する
N型領域とでPN接合が形成される構造である。
Here, 1 is N-type GaAsP or N-type Ga
AlAs epitaxial substrate (hereinafter, simply referred to as substrate), 2 is a Zn-doped P-type diffusion region, 3 is Al 2 O 3
Is a P-side electrode made of Al, and 5 is an N-side electrode made of Au alloy. As shown in FIG.
In the light emitting / receiving device of this embodiment, a diffusion barrier film 3 is provided on an N type epitaxial layer, and Zn doped P type impurities are diffused through the diffusion window to form a P type diffusion region 2. Is used to form a PN junction, and the end face of the substrate 1 is further etched to form a PN junction between the P type diffusion region 2 and the N type region existing in the vicinity of the end face of the substrate.

【0020】この受発光素子で受発光を行う場合、基板
端面において基板の一部(設計した値:ホールの拡散長
及び空乏層領域が形成される領域)のみ残留させた構造
となっているため、光吸収層の影響をほとんど受けるこ
となく、基板端面方向で形成させたPN接合で受発光で
きる。即ち、基板端面は、P型拡散領域2の端部と所定
距離αだけ離れた位置において、半導体下地の主面と交
差する面で構成されている。この所定(適正)距離は、
受光と発光機能で異なるが、いずれにしろ、受発光部
(PN接合部)近傍に形成される空乏層とホール拡散長
との和で主に規定できる。この空乏層幅は、駆動電圧に
より変わり、ホール拡散長は受光させる光の波長により
変わるが、いずれにしろ、適正距離は、数μm〜数10
μmとなる。
When light is emitted and received by this light emitting and receiving element, the structure is such that only a part of the substrate (designed value: the diffusion length of holes and the region where the depletion layer region is formed) remains on the end face of the substrate. The PN junction formed in the end face direction of the substrate can receive and emit light with almost no influence of the light absorption layer. That is, the end surface of the substrate is formed of a surface that intersects with the main surface of the semiconductor underlayer at a position separated from the end of the P-type diffusion region 2 by the predetermined distance α. This predetermined (appropriate) distance is
Although it differs in light receiving and light emitting functions, in any case, it can be mainly defined by the sum of the depletion layer formed in the vicinity of the light receiving and emitting portion (PN junction portion) and the hole diffusion length. The width of the depletion layer varies depending on the driving voltage, and the hole diffusion length varies depending on the wavelength of light to be received. In any case, the appropriate distance is several μm to several tens.
μm.

【0021】また、P型拡散また、拡散深さを変化させ
ることにより、基板端面方向で形成されるPN接合の面
積を制御できる。このように、基板端面方向に形成され
たPN接合で受発光させる構造である。図2に示すよう
に、本発明の第1実施例の受発光素子で受発光を行う場
合、端面受発光型LEDアレイに、順方向バイアス電圧
を印加し、キャリアを注入すると、PN接合付近で電子
と正孔の再結合により発光する。一方、逆方向バイアス
電圧を印加し、照射光を照射すると、PN接合付近でフ
ォトキャリアが発生し、空乏層領域のP側には正孔が、
N側には電子が蓄積される。
Further, the area of the PN junction formed in the substrate end face direction can be controlled by changing the P-type diffusion or the diffusion depth. As described above, the PN junction formed in the end face direction of the substrate receives and emits light. As shown in FIG. 2, when light is emitted and received by the light emitting and receiving element of the first embodiment of the present invention, when a forward bias voltage is applied to the end face light emitting and receiving type LED array and carriers are injected, near the PN junction is generated. Light is emitted by recombination of electrons and holes. On the other hand, when a reverse bias voltage is applied and irradiated with irradiation light, photocarriers are generated near the PN junction, and holes are generated on the P side of the depletion layer region.
Electrons are accumulated on the N side.

【0022】上記構造のLEDアレイでは、順方向と逆
方向のバイアスを切り換えることにより、1ドットで受
発光機能を得る。次に、本発明の第1実施例の受発光素
子の製造方法について説明する。図3〜図9は本発明の
第1実施例の受発光素子の製造工程図である。なお、各
図において、(a)は平面図、(b)はその平面図の縦
方向(A−B線)断面図、(c)はその平面図の横方向
(C−D線)断面図である。
In the LED array having the above structure, the light emitting / receiving function can be obtained with one dot by switching the bias in the forward and reverse directions. Next, a method of manufacturing the light emitting / receiving element of the first embodiment of the present invention will be described. 3 to 9 are manufacturing process diagrams of the light receiving and emitting device according to the first embodiment of the present invention. In each figure, (a) is a plan view, (b) is a vertical direction (AB line) sectional view of the plan view, and (c) is a lateral direction (CD line) sectional view of the plan view. Is.

【0023】(1)まず、図3(a)〜(c)に示すよ
うに、N型半導体領域101上に拡散防止膜102を積
層させた状態である。この実施例では、N型半導体領域
101としてN型GaAs0.8 0.2 基板、拡散防止膜
102としてAl2 3 膜を使用する。 (2)次に、図4(a)〜(c)に示すように、N型半
導体領域101上に積層した拡散防止膜102に拡散窓
103を設ける。この実施例では、ホトリソ及びエッチ
ング技術を用い、拡散窓103を形成する。
(1) First, as shown in FIGS. 3A to 3C, a diffusion prevention film 102 is laminated on the N-type semiconductor region 101. In this embodiment, an N-type GaAs 0.8 P 0.2 substrate is used as the N-type semiconductor region 101, and an Al 2 O 3 film is used as the diffusion prevention film 102. (2) Next, as shown in FIGS. 4A to 4C, a diffusion window 103 is provided in the diffusion prevention film 102 stacked on the N-type semiconductor region 101. In this embodiment, the diffusion window 103 is formed using photolithography and etching techniques.

【0024】(3)次に、図5(a)〜(c)に示すよ
うに、拡散防止膜102の拡散窓103のN型半導体領
域101上に拡散制御膜104を積層し、その拡散制御
膜104を介して不純物を導入し、P型半導体領域10
5を形成する。ここでは、拡散制御膜104としてPS
G膜、SiO2 膜、Al2 3 膜あるいはSiN膜を積
層する。
(3) Next, as shown in FIGS. 5A to 5C, a diffusion control film 104 is laminated on the N-type semiconductor region 101 of the diffusion window 103 of the diffusion prevention film 102, and its diffusion control is performed. Impurities are introduced through the film 104, and the P-type semiconductor region 10
5 is formed. Here, PS is used as the diffusion control film 104.
A G film, a SiO 2 film, an Al 2 O 3 film or a SiN film is laminated.

【0025】(4)次いで、図6(a)〜(c)に示す
ように、拡散制御膜104〔図5参照〕を全て剥離し、
P側電極となる金属膜106及びN側電極107を積層
する。この実施例では、P側電極となる金属膜106と
してAl膜、N側電極107としてAu合金を使用す
る。
(4) Next, as shown in FIGS. 6A to 6C, the diffusion control film 104 [see FIG. 5] is entirely peeled off,
The metal film 106 to be the P-side electrode and the N-side electrode 107 are laminated. In this embodiment, an Al film is used as the metal film 106 serving as the P-side electrode, and an Au alloy is used as the N-side electrode 107.

【0026】(5)次いで、図7(a)〜(c)に示す
ように、P側電極を形成するためにレジスト108を塗
布しホトリソを行う。 (6)次に、図8(a)〜(c)に示すように、P側電
極となる金属膜106をエッチングしてP側電極106
aを形成し、更に、P型半導体領域105及び一部分の
N型半導体領域101が残留するように、エッチング防
止膜であるレジスト108で覆う。
(5) Then, as shown in FIGS. 7A to 7C, a resist 108 is applied to form a P-side electrode and photolithography is performed. (6) Next, as shown in FIGS. 8A to 8C, the metal film 106 serving as the P-side electrode is etched to remove the P-side electrode 106.
a is formed, and is covered with a resist 108 that is an etching prevention film so that the P-type semiconductor region 105 and a part of the N-type semiconductor region 101 remain.

【0027】(7)次に、図9(a)〜(c)に示すよ
うに、P型半導体領域105及び一部分のN型半導体領
域101が残留するように、N型半導体領域101をエ
ッチッグする。最後に点線で示した部分をダイシングす
ることにより、受発光素子が完成する。図10は本発明
の第2実施例を示す受発光素子の構成図であり、図10
(a)はその受発光素子の斜視図、図10(b)はその
受発光素子の上面図、図10(c)は図10(a)のA
−A線断面図、図10(d)はその受発光素子の正面図
である。
(7) Next, as shown in FIGS. 9A to 9C, the N-type semiconductor region 101 is etched so that the P-type semiconductor region 105 and a part of the N-type semiconductor region 101 remain. . Finally, the portion indicated by the dotted line is diced to complete the light emitting / receiving element. FIG. 10 is a configuration diagram of a light emitting / receiving element showing a second embodiment of the present invention.
10A is a perspective view of the light emitting / receiving element, FIG. 10B is a top view of the light emitting / receiving element, and FIG. 10C is A of FIG. 10A.
FIG. 10D is a front view of the light emitting / receiving element, taken along the line A-A.

【0028】ここで、11は基板(N型GaAsP又は
N型GaAlAsエピタキシャル基板)、12はZnド
ープのP型拡散領域、13はAl2 3 からなる拡散防
止膜、14はAlからなるP側電極、15はAu合金か
らなるN側電極である。この受発光素子は、N型エピタ
キシャル層上に拡散防止膜を設け、そこに拡散窓を介し
てP型不純物を拡散してP型拡散領域12を形成し、そ
れによりPN接合を形成し、更に基板11を部分的にエ
ッチングし、基板端面の近傍においてP型拡散領域に隣
接したN型半導体領域の一部が残留した構造である。
Here, 11 is a substrate (N-type GaAsP or N-type GaAlAs epitaxial substrate), 12 is a Zn-doped P-type diffusion region, 13 is a diffusion prevention film made of Al 2 O 3 , and 14 is a P side made of Al. The electrode 15 is an N-side electrode made of Au alloy. In this light emitting / receiving element, a diffusion prevention film is provided on an N type epitaxial layer, and P type impurities are diffused through the diffusion window to form a P type diffusion region 12, thereby forming a PN junction. This is a structure in which the substrate 11 is partially etched, and a part of the N-type semiconductor region adjacent to the P-type diffusion region in the vicinity of the end face of the substrate remains.

【0029】図11に示すように、本発明の第2実施例
の受発光素子で受発光を行う場合、基板端面において基
板の一部(設計した値:ホールの拡散長及び空乏層領域
が形成される領域)のみ残留させた構造となっているた
め、光吸収層の影響をほとんど受けることなく、基板端
面方向で形成されたPN接合で受発光できる。即ち、基
板端面は、P型拡散領域12の端部と所定距離αだけ離
れた位置において、半導体下地の主面と交差する面で構
成されている。この所定(適正)距離は、受光と発光機
能で異なるが、いずれにしろ、受発光部(PN接合部)
近傍に形成される空乏層とホール拡散長との和で主に規
定できる。この空乏層幅は、駆動電圧により変わり、ホ
ール拡散長は受光させる光の波長じ変わるが、いずれに
しろ、適正距離は、数μm〜数10μmとなる。
As shown in FIG. 11, when light is received and emitted by the light emitting and receiving device of the second embodiment of the present invention, a part of the substrate (designed value: diffusion length of hole and depletion layer region is formed at the end face of the substrate. Since it has a structure in which only the (region to be formed) remains, it is possible to receive and emit light by the PN junction formed in the end face direction of the substrate with almost no influence of the light absorption layer. That is, the end surface of the substrate is a surface that intersects with the main surface of the semiconductor base at a position separated from the end of the P-type diffusion region 12 by a predetermined distance α. This predetermined (appropriate) distance differs depending on the light receiving and light emitting functions, but in any case, the light receiving and emitting section (PN junction section)
It can be mainly defined by the sum of the depletion layer formed in the vicinity and the hole diffusion length. This depletion layer width changes depending on the driving voltage, and the hole diffusion length changes depending on the wavelength of the light to be received, but in any case, the appropriate distance is several μm to several tens of μm.

【0030】この実施例では、図11に示すように、エ
ッチングにより形成された基板の一方の端面で発光さ
せ、もう一方の端面で受光させる、つまり両端面で受発
光させる構造となっている。すなわち、図11に示す端
面受発光型LEDアレイに順方向バイアス電圧を印加
し、キャリアを注入すると、PN接合付近で電子と正孔
の再結合により発光する。一方、逆方向バイアス電圧を
印加し、照射光を照射すると、PN接合付近でフォトキ
ャリアが発生し、空乏層領域のP側には正孔が、N側に
は電子が蓄積される。
In this embodiment, as shown in FIG. 11, one end face of the substrate formed by etching is made to emit light, and the other end face is made to receive light, that is, both end faces are made to receive and emit light. That is, when a forward bias voltage is applied to the end face light emitting and receiving type LED array shown in FIG. 11 and carriers are injected, light is emitted by recombination of electrons and holes near the PN junction. On the other hand, when a reverse bias voltage is applied and irradiation light is irradiated, photocarriers are generated near the PN junction, and holes are accumulated on the P side and electrons are accumulated on the N side of the depletion layer region.

【0031】また、拡散深さを変化させることにより、
基板端面方向で形成されるPN接合面積を制御できる。
さらに、上記した構造では、基板端面に形成されたPN
接合で受発光させるので、素子サイズを小さく、且つ製
造コストが安くできるという効果も得られる。上記構造
のLEDアレイでは、順方向と逆方向のバイアスを切り
換えることにより、1ドットで受発光機能を得る。
By changing the diffusion depth,
The PN junction area formed in the substrate end face direction can be controlled.
Further, in the above structure, the PN formed on the end face of the substrate
Since light is emitted and received by joining, it is possible to obtain an effect that the element size is small and the manufacturing cost can be reduced. In the LED array having the above structure, the light emitting / receiving function can be obtained with one dot by switching the bias in the forward direction and the bias in the reverse direction.

【0032】次に、本発明の第2実施例で示した受発光
素子の製造方法について説明する。図12〜図15は本
発明の第2実施例で示した受発光素子の主要な製造工程
図である。なお、この実施例における、拡散防止膜の積
層工程、拡散防止膜のホトリソ・エッチング工程、拡散
制御膜の積層と拡散工程については、第1実施例の図3
〜図5に示した(1)、(2)及び(3)と同工程であ
るため省略する。
Next, a method of manufacturing the light emitting / receiving element shown in the second embodiment of the present invention will be described. 12 to 15 are main manufacturing process diagrams of the light emitting and receiving element shown in the second embodiment of the present invention. The diffusion preventing film laminating step, the diffusion preventing film photolitho-etching step, the diffusion controlling film laminating step and the diffusion step in this embodiment will be described with reference to FIG.
-The steps are the same as (1), (2) and (3) shown in FIG.

【0033】以後、(4)から(7)の順で説明する。 (4)図12に示すように、拡散制御膜(図示なし)を
全て剥離し、P側電極となる金属膜(Al膜)を積層
し、さらにホトリソ・エッチングにより、P側電極11
3を形成する。この図において、111は基板(N型G
aAsP又はN型GaAlAsエピタキシャル基板)、
112は拡散防止膜、114はP型半導体領域である。
Hereinafter, description will be made in the order of (4) to (7). (4) As shown in FIG. 12, the diffusion control film (not shown) is entirely peeled off, a metal film (Al film) serving as a P-side electrode is laminated, and then the P-side electrode 11 is formed by photolithography etching.
3 is formed. In this figure, 111 is a substrate (N type G
aAsP or N-type GaAlAs epitaxial substrate),
Reference numeral 112 is a diffusion prevention film, and 114 is a P-type semiconductor region.

【0034】(5)次に、図13に示すように、N側電
極を形成すべき部分に開口部を設けてN側電極となる金
属膜(Au合金膜)を積層し、さらにホトリソ・エッチ
ングによりN側電極116を形成する。 (6)次に、図14に示すように、P型半導体領域11
4および一部分のN型半導体領域が残留するように、エ
ッチング防止膜であるレジスト117で覆う。
(5) Next, as shown in FIG. 13, an opening is provided in the portion where the N-side electrode is to be formed, and a metal film (Au alloy film) which will serve as the N-side electrode is laminated and further photolithographic etching is performed. Thus, the N-side electrode 116 is formed. (6) Next, as shown in FIG. 14, the P-type semiconductor region 11 is formed.
4 and a part of the N-type semiconductor region are covered with a resist 117 which is an etching prevention film so as to remain.

【0035】(7)次に、図15に示すように、P型半
導体領域114および一部分のN型半導体領域が残留す
るようにN型半導体領域をエッチングする。最後に点線
で示した部分をダイシングすることにより受発光素子が
完成する。図16は本発明の第3実施例を示す受発光素
子の構成図であり、図16(a)はその受発光素子の斜
視図、図16(b)はその受発光素子の上面図、図16
(c)は図16(a)のA−A線断面図、図16(d)
はその受発光素子の正面図である。
(7) Next, as shown in FIG. 15, the N-type semiconductor region is etched so that the P-type semiconductor region 114 and a part of the N-type semiconductor region remain. Finally, the light emitting and receiving element is completed by dicing the portion indicated by the dotted line. 16 is a configuration diagram of a light emitting / receiving element showing a third embodiment of the present invention, FIG. 16 (a) is a perspective view of the light emitting / receiving element, and FIG. 16 (b) is a top view of the light receiving / emitting element. 16
16C is a sectional view taken along the line AA of FIG. 16A, FIG.
FIG. 4 is a front view of the light emitting / receiving element.

【0036】この実施例は第2実施例で示した受光部分
の受光面積を広くすることにより、改良したものであ
る。ここで、21は基板(N型GaAsP又はN型Ga
AlAsエピタキシャル基板)、22はZnドープのP
型拡散領域、23はAl2 3 からなる拡散マスク、2
4はAlからなるP側電極、25はAu合金からなるN
側電極である。
This embodiment is an improvement made by widening the light receiving area of the light receiving portion shown in the second embodiment. Here, 21 is a substrate (N-type GaAsP or N-type Ga)
AlAs epitaxial substrate), 22 is Zn-doped P
Diffusion region, 23 is a diffusion mask made of Al 2 O 3 , 2
4 is a P-side electrode made of Al, and 25 is N made of an Au alloy.
It is a side electrode.

【0037】図17に示すように、本発明の第3実施例
の受発光素子で受発光を行う場合、エッチングにより形
成された基板の一方の端面で発光させ、もう一方の端面
で受光させる。つまり、両端面で受発光させる構造とな
っており、更に、この受発光素子は、発光部側のP型拡
散領域22aよりも、受光部側のP型拡散領域22bの
拡散深さを深く形成することにより、受光部となる基板
端面側から見たPN接合面積を増加させ、受光量を増加
させる構造である。
As shown in FIG. 17, when the light emitting / receiving element of the third embodiment of the present invention receives and emits light, one end face of the substrate formed by etching is made to emit light and the other end face is made to receive light. That is, the structure is such that both end faces receive and emit light, and further, in this light receiving and emitting element, the diffusion depth of the P type diffusion region 22b on the light receiving portion side is formed deeper than the P type diffusion region 22a on the light emitting portion side. By doing so, the PN junction area viewed from the substrate end surface side which becomes the light receiving portion is increased, and the amount of light received is increased.

【0038】すなわち、図17に示した端面受発光型L
EDアレイに順方向バイアス電圧を印加し、キャリアを
注入すると、PN接合付近で電子と正孔の再結合により
発光する。一方、逆方向バイアス電圧を印加し、照射光
を照射すると、PN接合付近でフォトキャリアが発生
し、空乏層領域のP側には正孔が、N側には電子が蓄積
される。
That is, the edge receiving / emitting type L shown in FIG.
When a forward bias voltage is applied to the ED array and carriers are injected, light is emitted by recombination of electrons and holes near the PN junction. On the other hand, when a reverse bias voltage is applied and irradiation light is irradiated, photocarriers are generated near the PN junction, and holes are accumulated on the P side and electrons are accumulated on the N side of the depletion layer region.

【0039】上記構造のLEDアレイでは、順方向と逆
方向のバイアスを切り換えることにより、1ドットで受
発光機能を得る。次に、本発明の第3実施例で示した受
発光素子の製造方法について説明する。図18〜図24
は本発明の第3実施例で示した受発光素子の主要な製造
工程図である。
In the LED array having the above structure, the light emitting / receiving function can be obtained with one dot by switching the bias in the forward direction and the bias in the reverse direction. Next, a method of manufacturing the light emitting / receiving element shown in the third embodiment of the present invention will be described. 18 to 24
FIG. 7 is a main manufacturing process diagram of the light emitting / receiving element shown in the third embodiment of the present invention.

【0040】なお、この実施例における拡散防止膜積層
工程、拡散防止膜のホトリソ・エッチング工程について
は、第1実施例の図3〜図4に示した(1)及び(2)
と同工程であるため省略する。 (3)まず、図18に示すように、拡散防止膜122の
拡散窓のN型半導体領域121上に、PSG膜、SiO
2 膜、Al2 3 膜、あるいはSiN膜などからなる第
1拡散制御膜123を積層する。
The diffusion preventing film laminating step and the diffusion preventing film photolithographic etching step in this embodiment are shown in FIGS. 3 to 4 of the first embodiment (1) and (2).
Since it is the same process as above, it is omitted. (3) First, as shown in FIG. 18, a PSG film and SiO are formed on the N-type semiconductor region 121 of the diffusion window of the diffusion prevention film 122.
A first diffusion control film 123 composed of two films, an Al 2 O 3 film, a SiN film or the like is laminated.

【0041】(4)次に、図19に示すように、第1拡
散制御膜123をホトリソ・エッチング法により、浅い
拡散深さを形成させる部分のみ残留させ、さらに第2拡
散制御膜124を積層する。その第1及び第2拡散制御
膜123,124を介して不純物を導入し、拡散深さの
異なるP型半導体領域125を形成する。その後、第2
拡散制御膜124を剥離する。
(4) Next, as shown in FIG. 19, the first diffusion control film 123 is left by a photolithography etching method so that only a portion where a shallow diffusion depth is formed remains, and a second diffusion control film 124 is further laminated. To do. Impurities are introduced through the first and second diffusion control films 123 and 124 to form P-type semiconductor regions 125 having different diffusion depths. Then the second
The diffusion control film 124 is peeled off.

【0042】(5)次に、図20に示すように、P側電
極となるAl膜からなる金属膜126を積層する。 (6)次に、図21に示すように、金属膜126をホト
リソ・エッチングによりP側電極126aを形成する。 (7)次に、図22に示すように、N側電極を形成すべ
き部分に開口部を設け、N側電極膜を積層し、さらにホ
トリソ・エッチングによりAu合金からなるN側電極1
27を形成する。
(5) Next, as shown in FIG. 20, a metal film 126 made of an Al film to be a P-side electrode is laminated. (6) Next, as shown in FIG. 21, a P-side electrode 126a is formed on the metal film 126 by photolithography etching. (7) Next, as shown in FIG. 22, an opening is provided in a portion where an N-side electrode is to be formed, N-side electrode films are laminated, and further, N-side electrode 1 made of an Au alloy is formed by photolithography etching.
27 are formed.

【0043】(8)次に、図23に示すように、P型半
導体領域125及び一部分のN型半導体領域121が残
留するように、エッチング防止膜としてのレジスト12
8で覆う。 (9)次に、図24に示すように、P型半導体領域12
5および一部分のN型半導体領域121が残留するよう
に、N型半導体領域121をエッチングする。最後に点
線で示した部分をダイシングすることにより受発光素子
が完成する。
(8) Next, as shown in FIG. 23, the resist 12 as an etching prevention film is formed so that the P-type semiconductor region 125 and a part of the N-type semiconductor region 121 remain.
Cover with 8. (9) Next, as shown in FIG. 24, the P-type semiconductor region 12
The N-type semiconductor region 121 is etched so that 5 and a part of the N-type semiconductor region 121 remain. Finally, the light emitting and receiving element is completed by dicing the portion indicated by the dotted line.

【0044】上記した第2及び第3実施例において、P
側電極及びN側電極をアレイ上面に設けることにより、
LEDアレイをドライバIC上に実装することが可能と
なる。図25は本発明の第4実施例を示す受発光素子と
ドライバICとのモジュールの構成図であり、図25
(a)はLEDアレイの斜視図、図25(b)はそのL
EDアレイの上面図、図25(c)はそのLEDアレイ
の側面図、図25(d)はそのLEDアレイの正面図で
ある。
In the second and third embodiments described above, P
By providing the side electrode and the N-side electrode on the upper surface of the array,
The LED array can be mounted on the driver IC. 25 is a block diagram of a module including a light emitting / receiving element and a driver IC according to the fourth embodiment of the present invention.
FIG. 25A is a perspective view of the LED array, and FIG.
25 (c) is a side view of the LED array, and FIG. 25 (d) is a front view of the LED array.

【0045】図25において、131はドライバIC、
132及び133はそれぞれ受光部用及び発光部用の集
束性ロッドレンズアレイ、134は受発光素子である。
ドライバIC131上の受発光素子134は、バンプ接
続により電気的に接続されている。ここで、バンプ接続
とは半田による接続、熱硬化樹脂による接続または異方
性導電樹脂による接続などである。この実装方式により
ヘッドを小型化できる。
In FIG. 25, 131 is a driver IC,
Reference numerals 132 and 133 denote converging rod lens arrays for the light receiving portion and the light emitting portion, respectively, and 134 denotes a light receiving and emitting element.
The light emitting / receiving element 134 on the driver IC 131 is electrically connected by bump connection. Here, bump connection means connection by solder, connection by thermosetting resin, connection by anisotropic conductive resin, or the like. This mounting method can reduce the size of the head.

【0046】また、上記したようなドライバICと受発
光素子のモジュールを基板に実装することにより、図2
6に示すような読み書きヘッド及び読み書き装置を構成
することができる。ここで、141は受発光素子、14
2はドライバIC、144及び145は書き込み用及び
読み込み用の集束性ロッドレンズアレイ、146は照明
光源、147は原稿、148は原稿設置用ガラス、14
9は現像機、150は帯電器、151は感光ドラム、1
52は転写機、153は用紙である。
By mounting the driver IC and the light emitting / receiving element module as described above on the substrate,
A read / write head and a read / write device as shown in FIG. 6 can be configured. Here, 141 is a light emitting / receiving element, and 14
Reference numeral 2 is a driver IC, 144 and 145 are converging rod lens arrays for writing and reading, 146 is an illumination light source, 147 is a document, 148 is a document setting glass, and 14
9 is a developing machine, 150 is a charger, 151 is a photosensitive drum, 1
Reference numeral 52 is a transfer machine, and 153 is paper.

【0047】この装置では、読み取り用の原稿147を
ガラス基板上でスキャンさせ、照明光源146により原
稿147を照射し、その反射光が読み込み用の集収束性
ロッドレンズアレイ145を通過して、受発光素子14
1の受光部(読み出し部)に入射し電気信号に換える。
なお、印字については前記と同様に行われる。この受発
光素子を使用することにより、ヘッドの機械的な駆動な
しに読み書きすることもできる。
In this apparatus, the reading original 147 is scanned on the glass substrate, and the original 147 is illuminated by the illumination light source 146, and the reflected light passes through the reading converging / converging rod lens array 145 and is received. Light emitting element 14
The light is incident on the first light receiving portion (reading portion) and converted into an electric signal.
The printing is performed in the same manner as described above. By using this light emitting / receiving element, reading / writing can also be performed without mechanically driving the head.

【0048】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。
The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

【0049】[0049]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 (1)請求項1記載の発明によれば、基板端面近傍に形
成されたPN接合で駆動電圧の切り換えにより、受光又
は発光させる構造にしたので、光吸収層の影響を受ける
ことなく、単体の素子で受発光することができる。
As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the first aspect of the invention, the PN junction formed in the vicinity of the end face of the substrate is configured to receive or emit light by switching the drive voltage. The device can receive and emit light.

【0050】(2)請求項2記載の発明によれば、前記
基板端面において、ホールの拡散層及び空乏層領域が形
成される領域である基板の一部分のみを残留させるよう
にしたので、光吸収層の影響をほとんど受けることな
く、基板端面方向で形成させたPN接合で受発光させる
ことができる。 (3)請求項3記載の発明によれば、前記PN接合が相
対向する基板の両端面方近傍に延在して設けられ、一方
の基板端面近傍に位置するPN接合で受光を行い、もう
一方の基板端面近傍に位置するPN接合で受光させるよ
うにしたので、単体の素子で受発光することができると
ともに、発光部と受光部の条件を変えることができる。
(2) According to the second aspect of the present invention, only a part of the substrate, which is the region where the diffusion layer and the depletion layer region of the hole are formed, is left at the end face of the substrate. Light can be emitted and received by the PN junction formed in the direction of the end face of the substrate without being affected by the layers. (3) According to the invention of claim 3, the PN junction is provided so as to extend in the vicinity of both end faces of the opposing substrates, and light is received by the PN junction located in the vicinity of one of the substrate end faces. Since light is received by the PN junction located near the end face of one of the substrates, light can be received and emitted by a single element, and the conditions of the light emitting portion and the light receiving portion can be changed.

【0051】(4)請求項4記載の発明によれば、片方
のPN接合を受光部として機能させる場合、発光部の拡
散深さに対して受光部の拡散深さが深くなるようにした
ので、発光部に対して受光部となるPN接合面積を増加
させ、受光量を増加させることができる。 (5)請求項5記載の発明によれば、基板主面からの拡
散深さに基づいて基板端面のPN接合面積を制御し、発
光量及び受光量を制御するようにした最適な発光量と受
光量を得ることができる。
(4) According to the invention described in claim 4, when one of the PN junctions functions as the light receiving portion, the diffusion depth of the light receiving portion is set to be deeper than the diffusion depth of the light emitting portion. It is possible to increase the amount of light received by increasing the PN junction area that serves as a light receiving portion with respect to the light emitting portion. (5) According to the invention described in claim 5, the PN junction area of the substrate end face is controlled based on the diffusion depth from the main surface of the substrate, and the optimal light emission amount is obtained by controlling the light emission amount and the light reception amount. The amount of received light can be obtained.

【0052】(6)請求項6記載の発明によれば、エッ
チングにより形成された基板端面近傍にPN接合を設け
ることができ、光吸収層の影響を受けずに受発光できる
とともに、サイズを小さく、しかも製造コストの低減を
図ることができる。 (7)請求項7記載の発明によれば、上記(6)の効果
に加え、発光部側に比して、受光部側のPN接合面積が
大きくなるように形成することができ、受光量を増加さ
せることができる。
(6) According to the sixth aspect of the invention, the PN junction can be provided in the vicinity of the end face of the substrate formed by etching, light can be emitted and received without being affected by the light absorption layer, and the size is small. Moreover, the manufacturing cost can be reduced. (7) According to the invention of claim 7, in addition to the effect of the above (6), it can be formed so that the PN junction area on the light receiving portion side is larger than that on the light emitting portion side. Can be increased.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例を示す受発光素子の構成図
である。
FIG. 1 is a configuration diagram of a light emitting / receiving element showing a first embodiment of the present invention.

【図2】本発明の第1実施例を示す受発光素子の動作の
説明図である。
FIG. 2 is an explanatory diagram of an operation of the light emitting / receiving element showing the first embodiment of the present invention.

【図3】本発明の第1実施例の受発光素子の第1製造工
程図である。
FIG. 3 is a first manufacturing process diagram of the light emitting and receiving device of the first embodiment of the present invention.

【図4】本発明の第1実施例の受発光素子の第2製造工
程図である。
FIG. 4 is a second manufacturing process drawing of the light emitting and receiving element of the first embodiment of the present invention.

【図5】本発明の第1実施例の受発光素子の第3製造工
程図である。
FIG. 5 is a third manufacturing process diagram of the light emitting / receiving element of the first embodiment of the present invention.

【図6】本発明の第1実施例の受発光素子の第4製造工
程図である。
FIG. 6 is a fourth manufacturing process diagram of the light emitting / receiving element of the first embodiment of the present invention.

【図7】本発明の第1実施例の受発光素子の第5製造工
程図である。
FIG. 7 is a fifth manufacturing process drawing of the light emitting and receiving device of the first embodiment of the present invention.

【図8】本発明の第1実施例の受発光素子の第6製造工
程図である。
FIG. 8 is a sixth manufacturing process drawing of the light emitting / receiving element of the first embodiment of the present invention.

【図9】本発明の第1実施例の受発光素子の第7製造工
程図である。
FIG. 9 is a seventh manufacturing process drawing of the light emitting and receiving device of the first embodiment of the present invention.

【図10】本発明の第2実施例を示す受発光素子の構成
図である。
FIG. 10 is a configuration diagram of a light emitting / receiving element showing a second embodiment of the present invention.

【図11】本発明の第2実施例を示す受発光素子の動作
の説明図である。
FIG. 11 is an explanatory diagram of the operation of the light emitting / receiving element showing the second embodiment of the present invention.

【図12】本発明の第2実施例の受発光素子の第4製造
工程図である。
FIG. 12 is a fourth manufacturing process diagram of the light emitting / receiving element of the second embodiment of the present invention.

【図13】本発明の第2実施例の受発光素子の第5製造
工程図である。
FIG. 13 is a fifth manufacturing process drawing of the light emitting and receiving device of the second embodiment of the present invention.

【図14】本発明の第2実施例の受発光素子の第6製造
工程図である。
FIG. 14 is a sixth manufacturing process drawing of the light emitting and receiving device of the second embodiment of the present invention.

【図15】本発明の第2実施例の受発光素子の第7製造
工程図である。
FIG. 15 is a seventh manufacturing step diagram of the light emitting / receiving element of the second embodiment of the present invention.

【図16】本発明の第3実施例を示す受発光素子の構成
図である。
FIG. 16 is a configuration diagram of a light emitting / receiving element showing a third embodiment of the present invention.

【図17】本発明の第3実施例を示す受発光素子の動作
の説明図である。
FIG. 17 is an explanatory diagram of the operation of the light emitting / receiving element showing the third embodiment of the present invention.

【図18】本発明の第3実施例の受発光素子の第3製造
工程図である。
FIG. 18 is a third manufacturing step diagram of the light emitting / receiving element of the third embodiment of the present invention.

【図19】本発明の第3実施例の受発光素子の第4製造
工程図である。
FIG. 19 is a fourth manufacturing process diagram of the light emitting / receiving element of the third embodiment of the present invention.

【図20】本発明の第3実施例の受発光素子の第5製造
工程図である。
FIG. 20 is a fifth manufacturing process diagram of the light emitting and receiving device of the third embodiment of the invention.

【図21】本発明の第3実施例の受発光素子の第6製造
工程図である。
FIG. 21 is a sixth manufacturing process drawing of the light emitting / receiving element of the third embodiment of the present invention.

【図22】本発明の第3実施例の受発光素子の第7製造
工程図である。
FIG. 22 is a seventh manufacturing step diagram of the light emitting / receiving element of the third embodiment of the present invention.

【図23】本発明の第3実施例の受発光素子の第8製造
工程図である。
FIG. 23 is an eighth manufacturing process diagram of the light emitting and receiving device of the third embodiment of the invention.

【図24】本発明の第3実施例の受発光素子の第9製造
工程図である。
FIG. 24 is a ninth manufacturing process diagram of the light emitting and receiving device of the third embodiment of the invention.

【図25】本発明の第4実施例を示す受発光素子とドラ
イバICとのモジュールの構成図である。
FIG. 25 is a configuration diagram of a module including a light emitting / receiving element and a driver IC according to a fourth embodiment of the present invention.

【図26】本発明の第4実施例を示す受発光素子とドラ
イバICとのモジュールを適用した読み書きヘッドと読
み書き装置を示す図である。
FIG. 26 is a diagram showing a read / write head and a read / write device to which a module of a light emitting / receiving element and a driver IC according to a fourth embodiment of the present invention is applied.

【図27】従来の上面発光型LEDの拡散深さ(Xj
と発光強度の関係を示す図である。
FIG. 27: Diffusion depth (X j ) of a conventional top-emitting LED
It is a figure which shows the relationship between and the light emission intensity.

【図28】従来の上面発光型LEDの拡散深さと受光感
度の関係を示す図である。
FIG. 28 is a diagram showing the relationship between the diffusion depth and the light receiving sensitivity of a conventional top-emitting LED.

【符号の説明】[Explanation of symbols]

1,11,21,111 N型GaAsP又はN型G
aAlAsエピタキシャル基板 2,12,22 ZnドープのP型拡散領域 3,13,23 Al2 3 からなる拡散防止膜 4,14,24,106a,113,126a Al
からなるP側電極 5,15,25,107,116,127 Au合金
からなるN側電極 22a 発光部側のP型拡散領域 22b 受光部側のP型拡散領域 101,121 N型半導体領域(N型GaAs0.8
0.2 基板) 102,112,122 拡散防止膜(Al2
3 膜) 103 拡散窓 104 拡散制御膜(PSG膜、SiO2 膜、Al2
3 膜あるいはSiN膜) 105,114,125 P型半導体領域 106,126 金属膜 108,117,128 レジスト 123 第1拡散制御膜 124 第2拡散制御膜 131,142 ドライバIC 132,133 受光部用及び発光部用の集束性ロッ
ドレンズアレイ 134,141 受発光素子 144,145 書き込み用及び読み込み用の集束性
ロッドレンズアレイ 146 照明光源 147 原稿 148 原稿設置用ガラス 149 現像機 150 帯電器 151 感光ドラム 152 転写機 153 用紙
1,11,21,111 N-type GaAsP or N-type G
aAlAs epitaxial substrate 2,12,22 Zn-doped P-type diffusion region 3,13,23 Diffusion prevention film made of Al 2 O 3 4,14,24,106a, 113,126a Al
P-side electrode 5,15,25,107,116,127 N-side electrode 22a made of Au alloy 22a P-type diffusion region 22b on the light-emitting side 22b P-type diffusion region 101,121 on the light-receiving side 101-121 N-type semiconductor region (N Type GaAs 0.8
P 0.2 substrate) 102, 112, 122 Diffusion prevention film (Al 2 O
3 film) 103 diffusion window 104 diffusion control film (PSG film, SiO 2 film, Al 2
O 3 film or SiN film) 105, 114, 125 P-type semiconductor region 106, 126 Metal film 108, 117, 128 Resist 123 First diffusion control film 124 Second diffusion control film 131, 142 Driver IC 132, 133 For light receiving part Focusing rod lens array 134, 141 for light emitting part and light receiving / emitting element 144, 145 Focusing rod lens array for writing and reading 146 Illumination light source 147 Original 148 Original setting glass 149 Developing machine 150 Charger 151 Photosensitive drum 152 Transfer machine 153 paper

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 B41J 2/45 H01L 31/10 A 2/455 H01L 31/10 (72)発明者 藤原 博之 東京都港区虎ノ門1丁目7番12号 沖電気 工業株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical display location B41J 2/45 H01L 31/10 A 2/455 H01L 31/10 (72) Inventor Hiroyuki Fujiwara Tokyo 1-7-12 Toranomon, Minato-ku Oki Electric Industry Co., Ltd.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 第1導電型の化合物半導体基板に第2導
電型の不純物を拡散させてなる拡散層を具えた受発光素
子において、 基板端面近傍に形成されたPN接合で駆動電圧の切り換
えにより基板端面側から発光または受光させることを特
徴とする受発光素子。
1. A light emitting and receiving element comprising a diffusion layer formed by diffusing impurities of a second conductivity type in a compound semiconductor substrate of a first conductivity type, wherein a driving voltage is switched by a PN junction formed near an end face of the substrate. A light emitting / receiving element characterized in that light is emitted or received from an end face side of a substrate.
【請求項2】 請求項1記載の受発光素子において、前
記基板端面近傍において、第1導電型領域の一部分を残
留させることを特徴とする受発光素子。
2. The light emitting / receiving element according to claim 1, wherein a part of the first conductivity type region is left in the vicinity of the end face of the substrate.
【請求項3】 請求項1記載の受発光素子において、前
記PN接合が相対向する基板の両端面近傍に延在して設
けられ、一方の基板端面近傍に位置するPN接合で受光
を行い、もう一方の基板端面近傍に位置するPN接合で
発光させることを特徴とする受発光素子。
3. The light emitting and receiving element according to claim 1, wherein the PN junction is provided so as to extend near both end faces of the opposing substrates, and light is received by the PN junction located near one end face of the substrate. A light emitting and receiving device, characterized in that light is emitted from a PN junction located near the end face of the other substrate.
【請求項4】 請求項3記載の受発光素子において、発
光部の拡散深さに対して受光部の拡散深さが深くなるよ
うにしたことを特徴とする受発光素子。
4. The light emitting / receiving element according to claim 3, wherein the diffusion depth of the light receiving portion is deeper than the diffusion depth of the light emitting portion.
【請求項5】 請求項1、2、3または4記載の受発光
素子において、基板主面からの拡散深さに基づいて基板
端面近傍に形成するPN接合の基板端面側から見た面積
を制御し、発光量または受光量を制御するようにしたこ
とを特徴とする受発光素子。
5. The light receiving and emitting device according to claim 1, 2, 3 or 4, wherein the area of the PN junction formed near the substrate end face viewed from the substrate end face side is controlled based on the diffusion depth from the substrate main surface. The light emitting / receiving element is characterized in that the light emitting amount or the light receiving amount is controlled.
【請求項6】 第1導電型の化合物半導体基板に第2導
電型の不純物を拡散させた受発光素子の製造方法におい
て、(a)第1導電型の化合物半導体基板上に拡散防止
膜を積層する工程と、(b)前記拡散防止膜に拡散窓を
形成し、露出させた第1導電型の領域を拡散制御膜で覆
い、前記拡散制御膜を介し不純物を拡散して、第2導電
型の拡散領域を形成する工程と、(c)基板端面近傍に
おいて第1導電型領域の一部分が残留するように、前記
第2導電型の拡散領域に隣接した第1導電型の化合物半
導体基板を部分的にエッチングする工程とを施すことを
特徴とする受発光素子の製造方法。
6. A method of manufacturing a light receiving and emitting device, wherein a second conductivity type impurity is diffused in a first conductivity type compound semiconductor substrate, wherein (a) a diffusion prevention film is laminated on the first conductivity type compound semiconductor substrate. And (b) forming a diffusion window in the diffusion prevention film, covering the exposed region of the first conductivity type with a diffusion control film, and diffusing impurities through the diffusion control film to form the second conductivity type. And (c) partially forming the first conductivity type compound semiconductor substrate adjacent to the second conductivity type diffusion region so that a part of the first conductivity type region remains in the vicinity of the substrate end face. The method for manufacturing a light emitting and receiving element, which comprises performing a step of selectively etching.
【請求項7】 第1導電型の化合物半導体基板に第2導
電型の不純物を拡散させた受発光素子の製造方法におい
て、(a)第1導電型の化合物半導体基板上に拡散防止
膜を積層する工程と、(b)前記拡散防止膜に拡散窓を
形成し、第1導電型の領域を露出させる工程と、(c)
該露出させた第1導電型の領域における拡散深さを浅く
する領域と深くする領域とをともに拡散制御膜で覆い、
しかもその拡散制御膜の膜厚を拡散深さを浅く形成する
領域上では厚く、拡散深さを深く形成する領域上では薄
くする工程と、(d)前記拡散制御膜を介し不純物を拡
散して、拡散深さが浅い第2導電型の第1拡散領域およ
び拡散深さが深い第2導電型の第2拡散領域を形成する
工程と、(e)基板端面近傍において第1導電型領域の
一部分が残留するように、前記第2導電型の拡散領域に
隣接した第1導電型の化合物半導体基板を部分的にエッ
チングする工程とを施すことを特徴とする受発光素子の
製造方法。
7. A method of manufacturing a light receiving and emitting device, wherein a second conductivity type impurity is diffused in a first conductivity type compound semiconductor substrate, wherein (a) a diffusion prevention film is laminated on the first conductivity type compound semiconductor substrate. And (b) forming a diffusion window in the diffusion prevention film to expose a region of the first conductivity type, and (c)
A region for making the diffusion depth shallow and a region for making the diffusion depth deep in the exposed region of the first conductivity type are both covered with a diffusion control film,
Moreover, a step of making the thickness of the diffusion control film thick on a region where the diffusion depth is formed shallow and thin on a region where the diffusion depth is formed deep, and (d) diffusing impurities through the diffusion control film. Forming a second diffusion type first diffusion region having a shallow diffusion depth and a second diffusion type second diffusion region having a deep diffusion depth; and (e) a portion of the first conductivity type region in the vicinity of the end face of the substrate. And a step of partially etching the first-conductivity-type compound semiconductor substrate adjacent to the second-conductivity-type diffusion region, so that the remaining light-emitting element remains.
JP18415095A 1995-07-20 1995-07-20 Light emitting / receiving element and method of manufacturing the same Expired - Fee Related JP3126632B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18415095A JP3126632B2 (en) 1995-07-20 1995-07-20 Light emitting / receiving element and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18415095A JP3126632B2 (en) 1995-07-20 1995-07-20 Light emitting / receiving element and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH0936414A true JPH0936414A (en) 1997-02-07
JP3126632B2 JP3126632B2 (en) 2001-01-22

Family

ID=16148247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18415095A Expired - Fee Related JP3126632B2 (en) 1995-07-20 1995-07-20 Light emitting / receiving element and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3126632B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345998A (en) * 2000-06-02 2001-12-14 Minolta Co Ltd Reading device, reading system and reading method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001345998A (en) * 2000-06-02 2001-12-14 Minolta Co Ltd Reading device, reading system and reading method

Also Published As

Publication number Publication date
JP3126632B2 (en) 2001-01-22

Similar Documents

Publication Publication Date Title
JP2577034B2 (en) Self-scanning light emitting element array and driving method thereof
US6180960B1 (en) Surface light-emitting element and self-scanning type light-emitting device
US8659035B2 (en) Light-emitting device, light-emitting device array, optical recording head, image forming apparatus, and method of manufacturing light-emitting device
US5077587A (en) Light-emitting diode with anti-reflection layer optimization
JP3452982B2 (en) LED print head, LED array chip, and method of manufacturing the LED array chip
US5135877A (en) Method of making a light-emitting diode with anti-reflection layer optimization
JP5327377B2 (en) Light emitting element, light emitting element array, optical writing head, and image forming apparatus
US6064418A (en) Led array, print head, and electrophotographic printer
JPH0645648A (en) Upper surface emission type semiconductor light emitting element and optical detector, optical information processing device, and light emitting device using it
JP3126632B2 (en) Light emitting / receiving element and method of manufacturing the same
JP2016152244A (en) Light emitting element, light emitting element array, optical writing head, and image forming apparatus
JP2004356191A (en) Light emitting device array and its manufacturing method
US5038186A (en) Light emitting diode array
JP4574006B2 (en) Image forming apparatus
JP3187213B2 (en) Light emitting and receiving diode
JP3184063B2 (en) Light emitting / receiving method, light emitting / receiving element and method of manufacturing the same
JP2758587B2 (en) Optical device using self-scanning light emitting element array
GB2238165A (en) A photodetector device
JP2854556B2 (en) Self-scanning light emitting element array and driving method thereof
JP3666547B2 (en) Optical device and manufacturing method thereof
JP4637517B2 (en) Light emitting device and image recording device
JP4578195B2 (en) Light emitting device and image recording device
JP3587568B2 (en) Image reading / writing method, edge emitting / receiving element, optical head for image reading / writing device, method for manufacturing edge emitting / receiving element
JP3126897B2 (en) Manufacturing method of light receiving / emitting element
JP2684873B2 (en) Photoelectric conversion device

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20001024

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081102

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081102

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091102

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091102

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101102

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101102

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111102

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111102

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121102

Year of fee payment: 12

LAPS Cancellation because of no payment of annual fees