JPH0936131A - Bipolar transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bipolar transistor having the small capacity between a base and a collector by a method wherein air spaces are respectively provided between base electrodes and the collector in such a way that the region of each one part of the base electrodes is projected from the base. SOLUTION: A bipolar transistor is provided with a layer structure comprising a collector 2, a base 3 and an emitter 4, which are laminated on a substrate 1. Air spaces are respectively provided between base electrodes 6 and the collector 2 in such a way that the region of each one part of the electrodes 6 is protruding from the base 3. This structure is obtained by making long intentionally an etching time in an etching for digging out a surface for forming collector electrodes 5. As side etchings are put in to the lower parts of the electrodes 6, the area of the junction between an external base and the collector 2 is decreased and the speed of the operation of an element can be increased into high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to increasing the operating speed of bipolar transistors.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view showing the structure of a conventional example of a high speed bipolar transistor. Here, a compound semiconductor hetero bipolar transistor (HBT) will be described as an example. A collector 2, a base 3 and an emitter 4 are stacked on the substrate 1 in a stepwise manner, and a collector electrode 5, a base electrode 6 and an emitter electrode 7 are provided on each of them. The base 3 has a region in contact with the emitter 4 that actually operates as a base, and a region for providing the base electrode 6.
In the present specification, the former is referred to as “intrinsic base” and the latter is referred to as “extrinsic base”.

In such a bipolar transistor, there is a base-collector capacitance C _bc as a factor that determines the upper limit of the operating speed, and it is important how to reduce this value. In order to reduce C _bc , it is necessary to reduce the connection area between the external base and collector layer 2 in the structure shown in FIG. For this reason, conventionally, the area of the external base is reduced by the fine processing technique, the resistance of the junction between the external base and the collector 2 is increased by ion implantation from above the external base, or the area between the external base and the collector 2 is increased. It is practiced to fill the insulator in advance.

[0004]

However, there is a problem that the method of reducing the area of the external base by fine processing cannot reduce the area beyond the limit of photolithography. Also, in the method of implanting ions or filling the insulator,
There is a problem that the resistance of the external base portion increases and the operating speed decreases. Furthermore, either way,
Process conditions are difficult and margins are small.

An object of the present invention is to solve such problems and provide a bipolar transistor having a small base-collector capacitance C _bc .

[0006]

The bipolar transistor of the present invention is characterized in that a gap is provided between the base electrode and the collector so that a part of the region of the base electrode protrudes from the base. With this structure, the junction area between the external base and the collector can be reduced.

In order to manufacture such a structure, when the surface on which the collector electrode is mounted is dug out, the wet etching is intentionally lengthened and side etching is performed down to the bottom of the base electrode. That is, etching for exposing the collector layer is performed until the surface of the base electrode on the collector layer side is exposed. If an appropriate etchant is used, the side etch amount can be controlled only by time, which is very easy in the process. Also, since the base electrode can be made large, the electrode resistance can be kept small.

If it is desired not to etch the collector layer more than necessary, an etching stopper layer made of a material that does not serve as a current barrier is provided in the collector layer. As a result, the amount of etching in the height direction can be limited. As the etching stopper layer, one that is insoluble or hardly soluble in the etchant to be used and is capable of high-quality single crystal growth is used. For example, when GaAs is used as the collector, GaAs or InGaAs is used as the base, and citric acid / hydrogen peroxide is used as the etchant, InGaP is used as the etching stopper layer.

In this specification, the terms "upper" and "lower" are used, but this means a direction with respect to the substrate, and does not have any other spatial meaning.

[0010]

1 is a sectional view showing a first embodiment of the present invention. This bipolar transistor has a layered structure including a collector 2, a base 3 and an emitter 4 stacked on a substrate 1. The layered structure is formed stepwise so that a part of each of the collector 2 and the base 3 is exposed. A collector electrode 5 and a base electrode 6 are provided on the exposed portions, and an emitter electrode 7 is provided on the emitter 4. Furthermore, a gap is provided between the base electrode 6 and the collector 2 so that a part of the region of the base electrode 6 protrudes from the base 3.

This structure is obtained by deliberately lengthening the etching time in etching the surface for forming the collector electrode 5. Since the side etch is formed under the base electrode 6, the junction area between the external base and the collector 2 is reduced, and the device operation can be speeded up.

FIG. 2 is a sectional view showing a second embodiment of the present invention. In this embodiment, a lower collector 8, an etching stopper layer 9 and an upper collector 10 are provided instead of the collector 2 in the first embodiment.

In the structure shown in FIG. 1, since the etching is performed until the required side etching amount is obtained, the thickness of the collector 2 must be ensured for the amount of overetching. If that is unacceptable, an etching stopper layer 9 is provided in the collector. The etching stopper layer 9 is for stopping etching during manufacturing, and is formed of a material that does not affect the operation of the device.

[0014]

EXAMPLES As a specific example, an example in which the present invention is applied to a GaAs-based HBT will be described. The structure shown in FIG. 2 is used, the substrate 1 is semi-insulating GaAs, the lower collector 8 is n ⁺ -GaAs, the etching stopper layer 9 is n ⁺ -InGaP, the upper collector 10 is n ^-- GaAs, and the base 3 is used. As p ⁺ -GaAs or p ⁺ -InGaAs as the emitter 4 and n-AlGaA as the emitter 4
Use s.

4 to 9 show a manufacturing method. In this method, first, as shown in FIG. 4, the lower subcollector layer 18, the etching stopper layer 19, the upper collector layer 20, the base layer 13 and the emitter layer 14 are crystal-grown on the substrate 1. The lower subcollector layer 18, the etching stopper layer 19 and the upper collector layer 20 form a collector layer. Subsequently, as shown in FIG. 5, the emitter electrode 7 is provided on the emitter layer 14 and the emitter layer 14 is etched. As a result, the emitter 4 is formed on a part of the base layer 13. Next, as shown in FIG. 6, the base electrode 6 is formed on the exposed portion of the base layer 13, and the base electrode 6 is formed.
And as shown in FIG. 8, the base layer 3 is etched using the resist 21 to expose the collector layer. Citric acid / hydrogen peroxide is used as the etchant. At this time, etching is performed until the surface of the base electrode 6 on the collector layer side is exposed. The upper collector layer 20 is also etched by this etching, and the etching stops at the etching stopper layer 19. Subsequently, the collector electrode 5 is formed on the exposed etching stopper layer 19 as shown in FIG. 9, and the etching stopper layer 19 and the substrate 1 are etched for isolation between the elements to form the element having the structure shown in FIG. obtain.

FIG. 10 shows Mason's unilateral power gain U and output short-circuit forward current gain h ₂₁ as high frequency characteristics of the prototyped GaAs HBT. From these, the maximum oscillation frequency f _max is about 150 GHz and the short circuit current gain frequency f
_It can be seen that a very excellent characteristic of _T of about 90 GHz is possible. The thickness and composition of each layer of HBT used in this measurement are as follows: contact layer between emitter 4 and emitter electrode 7: thickness 100 nm, n ⁺ -In _x Ga _{1 -x} As (Si: 7 →
15 × 10 ¹⁸ / cm ³ , x = 0 → 0.5), transition region between contact layer and emitter 4: thickness 35
nm, n ⁺ -Al _x Ga _{1 -x} As (Si: 3 → 70 x 1
0 ¹⁷ / cm ³ , x = 0.225 → 0), Emitter 4: Thickness 40 nm, n-Al _0.225 Ga _0.775
As (Si: 3 × 10 ¹⁷ / cm ³ ), spacer between the emitter 4 and the base 3: thickness 5 nm,
Undoped GaAs base 3: thickness 75 nm, p ⁺ -In _x Ga _1-x As
(Mg: 5.4 × 10 ¹⁹ / cm ³ , x = 0 → 0.1), transition region between base 3 and upper collector 10: thickness 4
0 nm, n ⁻ −In _x Ga _1-x As (Si: 5 × 10 ¹⁶
/ Cm ³ , x = 0 → 0.1), upper collector 10: thickness 250 nm, n ^-- GaAs
(Si: 5 × 10 ¹⁶ / cm ³ ), etching stopper layer 9: thickness 10 nm, n ⁺ -InG
aP (6 × 10 ¹⁸ / cm ³ ), lower collector 8: thickness 600 nm, n ⁺ -GaAs (S
i: 7 × 10 ¹⁸ / cm ³ ), substrate 1: thickness 625 μm, semi-insulating GaAs.

[0017]

As described above, the bipolar transistor of the present invention has an effect that the base-collector capacitance C _bc is small and a high oscillation maximum frequency f _max can be obtained.
Also, the etching process required to manufacture such a bipolar transistor can be controlled in time, and the manufacturing method is simple. Further, since the base becomes smaller but the base electrode does not become smaller, the electric resistance does not increase and the characteristics of the element are not deteriorated.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a structure of a conventional example.

FIG. 4 is a diagram showing a method for manufacturing the HBT shown in the second embodiment.

FIG. 5 is a diagram showing a method for manufacturing the HBT shown in the second embodiment.

FIG. 6 is a diagram showing a method for manufacturing the HBT shown in the second embodiment.

FIG. 7 is a diagram showing a method for manufacturing the HBT shown in the second embodiment.

FIG. 8 is a diagram showing a method for manufacturing the HBT shown in the second embodiment.

FIG. 9 is a view showing a method for manufacturing the HBT shown in the second embodiment.

FIG. 10 is a diagram showing high frequency characteristics of a prototype GaAs-based HBT.

[Explanation of symbols]

 1 substrate 2 collector 3 base 4 emitter 5 collector electrode 6 base electrode 7 emitter electrode 8 lower collector 9, 19 etching stopper layer 10 upper collector 13 base layer 14 emitter layer 18 lower subcollector layer 19 etching stopper layer 20 upper collector layer 21 resist

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Daisuke Murata 2-11-13 Nakamachi, Musashino City, Tokyo Terratec Co., Ltd. (72) Inventor Akira Miura 2-11-13 Nakamachi, Musashino City, Tokyo Terratec Co., Ltd. (72) Inventor Go Yagihara, 2-11-13 Nakamachi, Musashino City, Tokyo Terratec Co., Ltd. (72) Inventor, Sadaharu Oka, 2-11-13 Nakamachi, Musashino City, Tokyo

Claims (4)

[Claims] 1. A layered structure including a collector, a base and an emitter laminated on a substrate, wherein the layered structure is formed in a stepwise shape so that a part of each of the collector and the base is exposed, and exposed. In a bipolar transistor in which a collector electrode and a base electrode are provided in each part, a gap is provided between the base electrode and the collector so that a part of the region of the base electrode protrudes from the base. Characteristic bipolar transistor. 2. A collector layer and a base layer are formed on a substrate, an emitter is formed on a partial region of the base layer, an emitter electrode is formed on the emitter, and a base electrode is formed on an exposed portion of the base layer. In the method of manufacturing a bipolar transistor, wherein the base layer is exposed to expose the collector layer, and a collector electrode is formed on the exposed collector layer, etching for exposing the collector layer is performed on the collector electrode side of the base electrode. A method for manufacturing a bipolar transistor, characterized in that the process is performed until the surface of the substrate is exposed. 3. The bipolar transistor according to claim 2, wherein an etching stopper layer made of a material that does not serve as a current barrier is provided in the collector layer to prevent unnecessary etching of the collector layer during etching for exposing the collector layer. Manufacturing method of transistor. 4. The collector layer is formed of GaAs, the base layer is formed of GaAs or InGaAs, the etching stopper layer is formed of InGaP, and the etching for exposing the collector layer is performed using citric acid / hydrogen peroxide as an etchant. Of manufacturing bipolar transistor.