JPH0936130A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to increase the speed of the operation of an element. SOLUTION: A semiconductor device is provided with a semiconductor substrate 1, which has a buried layer having a first conductivity tape and has a second conductivity type different from the first conductivity type, insulating films 4 formed in the surface of this substrate, an emitter-base region 6, which is formed within an element formation region surrounded with these films 4 and has emitter and base diffused layers, and a collector contact region 7, which is formed on the extension in the longitudinal direction of the region 6 and is made a contact with a collector electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a device structure of a bipolar transistor using deep trench device isolation.

[0002]

2. Description of the Related Art In recent years, element isolation using a deep trench has attracted attention and has been widely used as a technique for realizing high speed operation of a bipolar transistor. Conventionally, an element isolation structure using a deep trench has an emitter base region in which an emitter base diffusion layer is present inside a deep trench and a collector contact region for extracting a collector, and these two regions are LOCOS (Local Oxi).
dation of Silicon) It was separated by using an oxide film and a shallow trench. FIG. 6 is a plan view of a conventional semiconductor device having a device structure separated by this LOCOS oxide film.
FIG. 6B shows a cross section taken along the line C-C ′ shown in FIG. 6A, which crosses the emitter base region 6 and the collector contact region 7.

In FIG. 6, n ⁺ buried layers 2 and n
A deep trench is formed in the p-type silicon substrate 1 on which the type epitaxial layer 3 is formed, and an element isolation is performed by embedding an insulating film 4 in the deep trench. An emitter base region 6 and a collector contact region 7 exist in the element forming region surrounded by the deep trench insulating film 4. The emitter base region 6 and the collector region 7 are separated by the LOCOS oxide film 5a. The emitter base region 6 is provided with a p-type base diffusion layer and an n-type emitter diffusion layer. The base diffusion layer has a base electrode 15 through a base lead electrode 11.
And the emitter diffusion layer is connected to
It is connected to the emitter electrode 16 via 4. The base extraction electrode 11 and the emitter extraction electrode 14 are electrically insulated by the insulating films 12 and 13. Further, the collector contact region 7 is connected to the collector electrode 17 via the collector extraction electrode 10.

The deep trench 4 is provided at a position separated from the ends of the emitter base region 6 and the collector contact region 7 by a certain distance X. this is,
This is because a process margin X considering the mask alignment of the deep trench 4, the emitter base region 6, and the collector contact region 7 and the bird's beak region when using the LOCOS method is necessary. RIE (Reactive Ion Etch) is used to separate the area between the emitter base region 6 and the collector contact region 7 and the wide silicon substrate surface.
ing) method or the like to form a groove, and by using the shallow trench-embedded element isolation 5 formed by filling the groove with an insulating film, the process margin X can be reduced due to good controllability of the processed shape. it can. A plan view and a cross-sectional view when this shallow trench buried element isolation is used are shown in FIGS. 7A and 7B, respectively.

In the conventional bipolar transistors shown in FIGS. 6 and 7, the emitter base region 6 has a long rectangular shape because the emitter opening width is reduced in the emitter-base junction capacitance 8 and the base resistance around the emitter. For the purpose of, it is necessary to make the emitter opening width close to the minimum processing size. Therefore, the junction area for passing the necessary current is usually controlled by the length of the emitter. A collector contact region 7 is arranged in parallel with the emitter base region 6. The length of the collector contact region 7 is formed to be substantially equal to the length of the emitter base region in the longitudinal direction.

[0006]

An important factor contributing to the high speed operation of the high speed bipolar transistor is the parasitic capacitance due to the structure. In the case of an npn-type transistor, in an element isolation structure using a deep trench,
The area of the device region inside the deep trench is n ⁺
Junction capacitance (C _js ) between the buried collector layer 2 and the p-type substrate 1
Is greatly affected by the high speed operation of the device. In the conventional device structure as shown in FIG. 6, since the collector contact region 7 is arranged in parallel with the longitudinal direction of the emitter base region 6, the junction capacitance C _js is the area of the emitter base region 6 and the collector contact region 7. And the area between the isolation region between the emitter base region 6 and the collector contact region 7 and the area of the process margin, the junction capacitance is very large.

In the device structure shown in FIG. 7, the area corresponding to the process margin is reduced, but the area of the emitter base region 6, the collector contact region 7 and the region between them cannot be reduced. Also, even if the process margin X is reduced by using a shallow trench to reduce the junction capacitance, when the emitter length becomes long, the capacitance of the area obtained by multiplying the emitter-collector and the separation width between the emitter and the collector length by the emitter length becomes the junction capacitance C _js. Remain.

Therefore, in the conventional semiconductor device, the junction capacitance C _js is not small, and there is a limit in _performing higher-speed element operation.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of operating an element as fast as possible.

[0010]

A semiconductor device according to the present invention includes a semiconductor substrate of a second conductivity type different from the first conductivity type having a buried layer of the first conductivity type, and formed on the surface of the substrate. An emitter base region having an insulating film, an emitter diffusion layer and a base diffusion layer formed in an element formation region surrounded by the insulating film, and a collector electrode formed on an extension of the emitter base region in the longitudinal direction. And a collector contact region to which the contact is made.

The emitter base region and the collector contact region may be separated by an insulator embedded in the shallow trench formed in the element region.

The insulating film is an insulating film embedded in a deep trench formed in the substrate, has openings in the emitter base region and collector contact region, respectively, and is embedded in the deep trench covering the element forming region. They may be separated by an insulating film formed so as to extend over the insulator.

[0013]

According to the semiconductor device of the present invention configured as described above, since the collector contact region is formed on the extension of the long side of the rectangular emitter base region, the collector contact region is formed between the emitter base region and the collector contact region. Even if the isolation width is the same as in the conventional case, the length of the isolation is the same as the short side of the emitter base region, so that the area required for separating the emitter base region and the collector contact region can be greatly reduced. .

Further, the length of the collector contact region can be set to a length necessary and sufficient for making a contact because this region is not arranged in parallel with the emitter base region as in the conventional case, and the length of the collector contact region is lower. The area of can be reduced. As a result, the area of the element formation region can be reduced, and the junction area between the buried layer below the element formation region and the semiconductor substrate, that is, the junction capacitance can be reduced, and the element can operate at high speed. You can

It should be noted that the emitter base region and the collector contact region are each formed with an opening, and the emitter base region and the collector contact are formed by an insulating film formed so as to cover the element formation region and extend over the insulator filled in the deep trench. When the region is separated, the sides of the emitter base region and the collector contact region that contact the deep trench are determined only by the deep trench mask, and the separation between the emitter base region and the collector contact region is determined by the opening mask of the formed insulating film. Since it is determined by the sides, the alignment margin for mask alignment of the emitter base region, the collector contact region and the deep trench is unnecessary. As a result, the junction area, that is, the junction capacitance can be further reduced, and the speed can be further increased.

[0016]

1 shows the configuration of a first embodiment of a semiconductor device according to the present invention. A plan view of the semiconductor device of this embodiment is shown in FIG. 1A, and a cross section taken along a cutting line AA 'shown in FIG. 1A is shown in FIG. A cross section cut along a cutting line BB 'shown in FIG. In the semiconductor device of this embodiment, n is formed on the p-type silicon substrate 1.
^{The +} buried layer 2 is formed, and the n type epitaxial layer 3 is formed on the n ⁺ buried layer 2. Then, a deep trench 4 for element isolation is formed in this substrate, and an insulating film is buried in this deep trench 4. An emitter base region 6 and a collector contact region 7 are provided in the element region surrounded by the deep trench 4.
Are formed.

Unlike the conventional case, the collector contact region 7 is provided on the extension of the emitter base region 6 in the longitudinal direction (see FIG. 1A). The emitter base region 6 and the collector contact region 7 are separated by the insulating film embedded in the shallow trench 5. A p-type base diffusion layer and an n-type emitter diffusion layer are provided in the emitter base region 6, and the base diffusion layer is formed by solid phase diffusion from the base extraction electrode 11 and the base electrode 15 via the base extraction electrode 11. The emitter diffusion layer is formed by solid phase diffusion from the emitter extraction electrode 14 and is connected to the emitter electrode 16 via the emitter extraction electrode 14. The base extraction electrode 11 and the emitter extraction electrode 14 are electrically insulated by the insulating films 12 and 13.
The collector contact region 7 is connected to the collector electrode 17 via the collector extraction electrode 10.

In the emitter base region 6 of the high speed bipolar transistor, the emitter opening width is determined by the minimum processing width dimension of the process to reduce parasitic components, and the emitter length is determined by the amount of current required for circuit operation. Generally, it has a vertically long rectangular pattern as shown.

In the semiconductor device of this embodiment as described above, the collector contact region 7 is provided on the extension of the emitter base region 2 in the longitudinal direction as shown in FIG. Has the same width as the width of the emitter base region 6, and its length is only required to be sufficient for making contact. Thereby, the area of the collector contact region 7 can be reduced as compared with the conventional case. The isolation region between the emitter base region 6 and the collector contact region 7 is also
Even if the separation distance is the same as the conventional case, the width of the collector region 7 is subtracted from the length of the conventional collector contact region 7 shown in FIG. 6 in the longitudinal direction, that is, the length of the emitter base region 6 in the longitudinal direction. It is possible to reduce the area obtained by multiplying the above by the separation distance. Further, the process margin X, which was necessary in the conventional structure shown in FIG. 6, is also unnecessary.

As described above, according to this embodiment, the area of the element region surrounded by the deep trench 4, that is, the junction area between the n ⁺ buried collector layer 2 and the p-type substrate 1 can be reduced. Therefore, the speed of the device can be increased.

Next, FIG. 2 shows the manufacturing process of the first embodiment of the method of manufacturing a semiconductor device according to the present invention. The manufacturing method of this embodiment is for manufacturing the semiconductor device shown in FIG. 1. First, as shown in FIG.
An n ⁺ buried layer 2 is formed thereon, and an n type epitaxial layer 3 thereof is formed. Subsequently, a photoresist pattern is formed and R is used as a mask with this resist pattern.
The shallow trench as shown in FIG. 2A is formed by etching the silicon substrate by about 0.7 μm using the IE method. In addition, in the above etching, if the silicon substrate cannot obtain a sufficient etching selection ratio with a normal photoresist, an oxide film is once deposited on the substrate, and the oxide film is patterned using photolithography to form a mask. Alternatively, the shallow trench may be formed by performing RIE using this mask.

Next, after removing the mask, FIG.
After forming an oxide film 41 on the entire surface as shown in FIG. 3, a photoresist pattern 42 is formed. The oxide film 41 is etched by RIE using the resist pattern 42 as a mask to form a mask for forming a deep trench.
RIE is performed using the mask of the oxide film 41 to form a deep trench in the silicon substrate (FIG. 2).
(C)). At this time, regarding the patterns of the shallow trench and the deep trench, only the mask alignment of the photoresist and the processing conversion difference up to the RIE process may be considered. The width of the emitter base region 6 (see FIG. 1) is 1 μm or more,
The minimum width of the deep trench is about 1 μm, whereas the processing conversion difference is on the order of 0.1 μm. Therefore, this process merge is not shown in FIG.

Next, after removing the mask, the shallow trench and the deep trench are filled with an insulating film,
The surface is planarized to expose the surface of the silicon substrate on the emitter base region 6 and the collector contact region 7 (see FIG. 2D).

In the actual burying process, a thin thermal oxide film is formed on the silicon surface in the trench in consideration of the stability of the surface state and the electrical characteristics, and then the low pressure chemical vapor deposition method (LPCVD) with good step coverage is formed. ) Etc. to deposit an oxide film and fill the trench. The initial thermal oxide film may have a thickness of about several tens of nm so that the shape change and the stress generated by the formation of the thermal oxide film itself are reduced. afterwards,
Embedding planarization is performed by using a technique such as chemical mechanical polishing (CMP) or etch back. After the element isolation is formed as described above, the base drawing poly 11, the emitter poly 14, the wiring 1 are formed by using a well-known technique.
An element forming process such as 5 and 16 processing is performed (see FIG. 2D). In the figure, the structure of a transistor having a double polysilicon self-aligned structure is shown.

Next, the configuration of the second embodiment of the semiconductor device according to the present invention is shown in FIG. FIG. 3A is a plan view of the semiconductor device of this embodiment, and FIG. 3B is a plan view of the semiconductor device.
FIG. 3 is a sectional view taken along the line AA ′ shown in FIG.
FIG. 3C is a sectional view taken along the line BB ′ shown in FIG. FIG. 3B includes a cross section of the emitter base region 6 in which the emitter base junction exists, and FIG.
Is an emitter base region 6 and a collector contact region 7
Including a cross section including.

In the semiconductor device of the second embodiment, the arrangement of the emitter base region 6 and the collector contact region 7 is the same as that of the semiconductor device of the first embodiment, and the emitter base region 6 and the collector contact region 7 are also arranged. The contact region 7 is also surrounded by the insulating film 4 embedded in the deep trench as in the case of the first embodiment.
In the case of the second embodiment, the isolation between the emitter base region 6 and the collector contact region 7 inside the deep trench and the electrical isolation between the base extraction electrode 11 outside the deep trench and the silicon substrate are insulated. This is performed by opening the deposited film 9 at the emitter base region 6 and the collector contact region 7. Except for this separation, it is almost the same as the case of the first embodiment. This emitter base region 6 and collector region 7
In the pattern 19 which opens, the portion which contacts the deep trench other than the isolation portion between the emitter base region 6 and the collector contact region 7 extends to the middle of the deep trench 4 in which the insulator is buried. By using this pattern, the width of the emitter base region 6 is determined by the processing width of the deep trench 4,
Therefore, the pattern 19 is not affected by the misalignment. Therefore, it is not necessary to consider even the slight misalignment between the shallow trench and the deep trench in the first embodiment of the manufacturing method described above. Even if the misalignment actually occurs in this second embodiment, if the width of the deep trench filled with the insulator is about 1 μm, the emitter base region 6 and the collector contact region 7 are opened, and the outside of the deep trench is opened. In order not to open on the silicon region, when a maximum margin of 0.5 μm is provided around the emitter base region 6 and the collector contact region 7, a maximum misalignment of less than 0.5 μm can be allowed.

The process for flattening the buried surfaces of the shallow trench and the deep trench used in the manufacturing method of the first embodiment to uniformly expose only the silicon surface of the emitter base region 6 and the collector contact region 7 is as follows. , The technique for leaving the filling material between the shallow trench patterns of various widths involves technical difficulties,
In the case of the process of leaving the filling material only in the deep trench having a uniform width as in this embodiment, the technical difficulty is low.

As described above, in the semiconductor device of the second embodiment, the margin for mask alignment of the emitter base region 6, the collector contact region 7 and the deep trench 4 is unnecessary, and the semiconductor device of the first embodiment is different from that of the semiconductor device of the first embodiment. Also, the junction area, that is, the junction capacitance can be further reduced, and higher speed operation can be performed.

Next, the manufacturing process of the semiconductor device of the second embodiment will be described with reference to FIG. First, a mask for deep trench formation made of an oxide film (not shown) is formed on the p-type silicon substrate 1 on which the n ⁺ buried layer 2 and the n-type epitaxial layer 3 are formed, and the substrate is formed using this mask. Is etched by using the RIE method.
A deep trench is formed as shown in FIG. Subsequently, as shown in FIG. 4B, the deep trench is filled with an insulator, the surface is flattened, and the surface of the silicon substrate on the emitter base region 6 and the collector contact region 7 is exposed (see FIG. 4B). This embedding process is also the first
As in the case of the above embodiment, it is preferable to deposit a thin thermal oxide film on the deep trench and then deposit an insulator. In order to leave the insulator only in the deep trench 4, the above-mentioned CMP may be used, but since the surface on which the insulator is deposited is almost flat after the deep trench is completely filled, a relatively easy process is possible. For example, RIE of an oxide film, wet etching, or the like can be used.

Next, an insulating film 9 is formed on the entire surface, and only the emitter base region 6 and the collector contact region 7 are opened (see FIG. 4C). The insulating film at this time may be an oxide film, a nitride film (SiN), or a composite film of these. After that, an element structure is formed in the same manner as in the manufacturing method of the first embodiment shown in FIG. 2 (see FIG. 4D).

In the above manufacturing process, the surface of the silicon substrate in a wide region other than the element region is covered with the insulating film 9, and the lead poly 11 for the base or the like, the impurity-doped poly or wiring used as the resistor, the silicon substrate and the like. However, the element isolation structure of the second embodiment may be formed after forming a LOCOS oxide film or a shallow trench in a region outside the region surrounded by the deep trench. In particular, by combining with the element isolation by the LOCOS method, the CMOS portion 30 is formed by the proven LOCOS isolation 25 as shown in FIG. 5, and the bipolar portion is the element isolation structure of the above embodiment aiming at high performance. In addition, it is possible to easily support BiCMOS. FIG. 5 is a sectional view of the configuration of a third embodiment of the semiconductor device according to the present invention which is thus formed into BiCMOS.

By using the manufacturing process shown in FIG. 4, the manufacturing process of the semiconductor device such as the trench filling process and the mask aligning process is facilitated, and the yield and reliability of the device can be improved. Furthermore, by using this manufacturing process, the LOCOS can be applied to the bipolar transistor.
It becomes possible to easily construct a BiCMOS process by combining CMOS transistors formed using element isolation.

Although the npn-type bipolar transistor has been described in the above embodiment, it is needless to say that it can be applied to a pnp-type bipolar transistor by replacing the n-type and the p-type.

[0034]

As described above, according to the present invention, it is possible to reduce the area of the element region such as the emitter base region and the collector contact region inside which is surrounded by the deep trench, and thereby the n ⁺ buried region is formed. It is possible to reduce the parasitic capacitance C _js, which is caused by the junction area between the collector layer and the p-type substrate, and to enable high-speed operation of the device.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a process sectional view showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 3 is a configuration diagram of a second embodiment of a semiconductor device according to the present invention.

4A to 4C are process cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 5 is a sectional view showing the configuration of a third embodiment of the semiconductor device according to the present invention.

FIG. 6 is a configuration diagram of a conventional semiconductor device.

FIG. 7 is a configuration diagram of another example of a conventional semiconductor device.

[Explanation of symbols]

1 p-type silicon substrate 2 n ⁺ buried layer 3 n-type epitaxial layer 4 deep trench (element isolation insulating film) 6 emitter base region 7 collector contact region 8 emitter base junction 9 insulating film 10 collector extraction electrode 11 base extraction electrode 12 insulation film 13 Side Walls 14 Emitter Extraction Electrodes 15 Base Electrodes 16 Emitter Electrodes 17 Collector Electrodes 19 Patterns

Claims (3)

[Claims] 1. A semiconductor substrate of a second conductivity type different from the first conductivity type having a buried layer of the first conductivity type, an insulating film formed on the surface of the substrate, and surrounded by the insulating film. An emitter base region having an emitter diffusion layer and a base diffusion layer formed in the element formation region, and a collector contact region formed on an extension of the emitter base region in the longitudinal direction and contacting the collector electrode. A semiconductor device characterized by being provided. 2. The semiconductor device according to claim 1, wherein the emitter base region and the collector contact region are separated by an insulator embedded in a shallow trench formed in the element formation region. . 3. The insulating film is an insulating film embedded in a deep trench formed in the substrate, and the emitter base region and the collector contact region have openings in the emitter base region and the collector contact region, respectively. 2. The semiconductor device according to claim 1, wherein the semiconductor device is separated by an insulating film formed so as to cover the element formation region and extend over an insulator embedded in the deep trench.