JPH0936087A - Etching method and manufacture of semiconductor device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the reduction in the film of a layer such as SiN(silicon nitride) of, for example, Si3 Ni which is an etching stopper layer of the ground of a layer to be etched and hence to prevent failure based on it from occurring. SOLUTION: In an etching method in a structure where an etching stopper layer 5 is provided on a ground with a level difference such as a semiconductor substrate 1 having a gate electrode 3 and a layer 6 to be etched is formed on the stopper layer 5, etching retardant treatment such as inclination ion etching of, for example, a high-melt-point metal and C is performed to the peripheral part of the stopper layer 3 for etching.

Description

Detailed Description of the Invention

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an etching method and a method for manufacturing a semiconductor device using the etching method. INDUSTRIAL APPLICABILITY The present invention can be used, for example, as an improved method of a thin film forming means when manufacturing a semiconductor integrated circuit device, and particularly as an improved technique of a dry etching method in that case. The present invention is, for example, oxide film on the Si ₃ N ₄ (S
It can be suitably used when selectively etching (iO ₂ , BPSG, etc.).

[0002]

2. Description of the Related Art Various technical trends have been observed in the field of electronic materials, particularly in the field of semiconductor devices. For example, high integration of elements realized by current highly integrated semiconductor circuits such as VLSI and ULSI. Several technical directions have been found in order to make the contents higher, higher density, and higher performance and higher speed of the device. For example, the miniaturization of device dimensions by highly integrated technology, improvement of device structure and circuit, system LSI by high density technology
Is a single item.

Among these directions, it is expected that the process characteristics of the process technology (dry etching technology, CVD technology, etc.) responsible for the miniaturization of the element size by the highly integrated technology will be improved.

In recent years, a self-alignment technique (self-alignment technique) has been attracting attention as a highly integrated technique for reducing the element size. The self-alignment technique includes a salicide technique and a self-aligned contact hole forming technique.

The self-aligned contact hole forming technique is typically a technique of forming an interlayer hole having a diameter of a contact hole or less by photolithography in a self-aligned manner in a source / drain region about the width of a gate electrode.

As a typical device structure in which this technique is utilized, the gate electrode is covered with Si ₃ N ₄ which is an etching stopper layer, and then SiO ₂ , B of the interlayer film are coated.
It is known that PSG is formed into a film. The process gas used in this technique is mainly a C ₄ F ₈ / CO mixed gas system or a CHF ₃ / CO mixed gas system.

With this technique, even if the minimum diameter of the contact hole for photolithography is limited or there is misalignment, the contact hole can be self-aligned in a desired region about the width of the gate electrode.

In such a self-aligned contact hole forming technique, S used as an etching stopper layer
JP-A-6-132252 can be cited as an example disclosing that SiO ₂ etching and BPSG etching having a high selectivity with respect to the i ₃ N ₄ film can be realized.

[0009]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention As described above, CH
Self-aligned contact etching using a F ₃ / CO mixed gas system or the like is a technique that enables self-aligned processing as a highly integrated technique for reducing the element size, but is disadvantageous in the manufacture of semiconductor integrated circuit devices. Have a point.
This will be described below.

As a structure for processing the self-aligned contact, a structure as shown in FIG. 13 is generally used.

In this structure, the polycide gate electrode 3
A sidewall ₄ of Si ₃ N ₄ , SiO ₂ or the like for protecting the LDD layer of the transistor element is formed on the side wall of (in the illustrated example, made of poly Si3a and WSi3b). Si _{3 is used} as an etching stopper layer 5 so as to cover the gate electrode 3 with sidewalls.
N ₄ is formed by the CVD method. Next, the interlayer insulating film 6
SiO ₂ , BPSG, etc. are deposited. Further, the contact hole pattern 7 is patterned on the photoresist by the photolithography method.

An example of performing CHF ₃ / CO etching on this structure is generally as shown in FIG. V
Due to the straightness of the incident ions CFx ⁺ accelerated by the dc bias, anisotropic etching is performed according to the pattern of the openings.

In this example, at the contact bottom (C) and contact side wall (B), selective BPSG and SiO ₂ etching having high selectivity with respect to Si ₃ N ₄ is realized. This is because the sputter etching due to incident ions is small, the Si—C layer is formed on the oxide film surface, and the CFx polymer is sufficiently deposited. On the other hand, Si that is the etching stopper layer 5 that is most exposed to incident ions
The shoulder portion (A) of the ₃ N ₄ thin film is deposited Si—C, CF.
Since the x-polymer is removed by the collision of incident ions, the shoulder of Si ₃ N ₄ is always exposed and Si ₃ N ₄ is sputter etched. Therefore, the film reduction of Si ₃ N ₄ occurs here.

As described above, even if the etching conditions are optimized, when sufficient over-etching corresponding to the maximum contact depth is carried out, the shoulder of Si ₃ N ₄ forming the etching stopper layer is thinned and the gate electrode is reduced. Will be exposed contacts. When the W plug is embedded, the interlayer wiring short-circuits with the gate electrode, resulting in a defect. Therefore, manufacturing disadvantages such as a decrease in the yield of the semiconductor integrated circuit device occur.

The present invention solves the above-mentioned problems of the prior art and solves the problem of S, such as Si ₃ N ₄ , which is an etching stopper layer.
An object of the present invention is to provide an etching method and a method of manufacturing a semiconductor device using the etching method, in which the film thickness of the shoulder of an iN (silicon nitride) film or the like is not reduced, thereby preventing the occurrence of defects based on this.

[0016]

In order to solve the above-mentioned problems, the following technical means are adopted in the etching method of the present invention and the method of manufacturing a semiconductor device using the etching method.

The etching method according to the present invention is an etching method in which an etching stopper layer is provided on a base having a step, and a structure in which an etching target layer is formed on the etching stopper layer is etched. It is difficult to etch,
It is characterized in that the layer to be etched is etched.

According to the method of manufacturing a semiconductor device of the present invention, an etching stopper layer is provided on a base having a gate electrode,
In the method of manufacturing a semiconductor device, which comprises an etching step of forming a layer to be etched on the etching stopper layer and forming a hole in the layer to be etched in a self-aligned manner (that is, in self-alignment), It is characterized in that the above-mentioned layer to be etched is etched by subjecting the shoulder portion of the etching stopper layer to a difficult etching treatment.

In this case, there is provided an etching step of processing a contact hole having an opening width about the width of the gate electrode in a self-aligned manner, and the shoulder portion of the etching stopper layer covering the gate electrode is subjected to the difficult etching treatment. Can be configured.

The etching stopper layer may be made of silicon nitride, the layer to be etched may be made of silicon oxide, and the etching gas may be a fluorine-based gas to which CO is added.

In the present invention, the difficult etching treatment is
A refractory metal (T) is formed on the shoulder portion of the etching stopper layer covering the gate electrode by oblique ion implantation.
i, Zn, W, Mo, Ag, etc.), or
The high melting point metal nitride film or the high melting point metal mixing layer can be formed by mixing.
Here, the refractory metal nitride film or the refractory metal mixing layer does not mean that the refractory metal and the stopper layer, for example, nitrogen are not always formed in a stoichiometric manner. This is because other atoms may be mixed, and these are generically expressed.

In this case, Si ₃ after metal mixing is used.
The shoulder portion of N ₄ can be configured to form a refractory metal nitride film having an amorphous or crystalline property by the subsequent processing, for example, the coating of the interlayer insulating film and the reflow heat treatment.

In the present invention, the difficult etching treatment is
Carbon is ion-implanted or mixed in the shoulder portion of the etching stopper layer covering the gate electrode by oblique ion implantation to form a carbide layer such as a silicon carbide (SiC) layer or a C-mixing layer. It can be configured. Here, the term "carbide layer or C mixing layer" does not mean that C and the silicon constituting the stopper layer are formed in a stoichiometrically consistent manner, and other atoms are mixed. This is because these are generically expressed.

In addition, the shoulder portion of Si ₃ N ₄ after carbon mixing forms a carbide layer (eg, SiC) having an amorphous or crystalline property by the subsequent processing, for example, coating of an interlayer insulating film and reflow heat treatment. can do.

[0025]

According to the present invention, the shoulder of the etching stopper layer below the layer to be etched is made difficult to etch, for example, refractory metal or carbon is introduced to slow down the etching of the shoulder. Therefore, it is possible to prevent the shoulder portion of the etching stopper layer from being etched when the layer to be etched is etched, and thus it is possible to prevent the film reduction.

For example, S is used as an etching stopper layer.
When silicon nitride typified by i ₃ N ₄ is used and SiO ₂ or BPSG is used as the layer to be etched, in the present invention, SiO ₂ or BPSG etching having high selectivity for Si ₃ N ₄ is used. Has a structure in which an extremely shallow metal nitride film (or metal mixing layer) is formed on the shoulder portion of Si ₃ N ₄ which is an etching stopper film, or an extremely shallow SiC thin film (or C mixing layer) is formed. This ultra-shallow metal nitride film (or metal mixing layer) is more robust against incident ion sputtering because it has the formed structure, or this ultra-shallow SiC thin film (or C mixing layer). )
Above, there is an effective CFx polymer deposition that can compete with the sputtering of incident ions (because it has an affinity with the C-containing layer) and the sputter etch stops, thus selectively stopping the Si ₃ N ₃ stopper. ₄ films remain, and contact holes with self-alignment can be easily opened.

As described above, Si having a high selectivity for Si ₃ N ₄ using CHF ₃ / CO chemistry by the conventional magnetron etcher and the like is used.
With O ₂ and BPSG etching, the contact can be opened in a region of the gate electrode width in a self-aligned manner,
Film reduction (Si ₃ N ₄ etching) occurs at the shoulder portion of Si ₃ N ₄ which is an etching stopper. Due to this etching failure, there are disadvantages such as an electrical short circuit and a reduction in the yield of the semiconductor integrated circuit device.

When the conventional structure having only the stopper Si ₃ N ₄ film is used, the shoulder portion of this Si ₃ N ₄ is most exposed to the incident ions and the CFx polymer is removed, so that the Si ₃ It is difficult to prevent film loss due to the progress of sputter etching of N ₄ . I am also concerned about the process margin.

In the present invention, the surface of Si ₃ N ₄ etc. of the shoulder portion having the metal nitride film (metal mixing layer) is always exposed by removing CFx polymer by incident ions. However, refractory metal nitride film (or
Mixed metal layer) is present on the surface layer, and the sputtering efficiency of CFx ⁺ ions with respect to the metal is Si, SiO ₂ ,
Since it is lower than that of Si ₃ N ₄ , the progress of sputter etching is slowed (or the etching reaction of Si ₃ N ₄ is suppressed), and this serves as a protective film for Si ₃ N ₄ below the metal mixing layer. Work effectively.

This metal mixing layer can be formed, for example, by oblique ion implantation so as to cover the entire shoulder portion, which is effective. Therefore, according to the present invention, even when over-etching corresponding to the maximum contact depth is performed, the metal mixing layer and the stopper layer, for example, the Si ₃ N ₄ film remains, and the desired self-aligned contact hole is easily processed. be able to.

Alternatively, in the present invention, the carbide layer which is a difficult-to-etch layer, for example, Si ₃ N _{4 in the} shoulder portion having the SiC thin film (C mixing layer) is also exposed to the incident ions CFx. Since C is mixed, the deposition of CFx polymer, which can compete with the sputtering of incident ions, is sufficiently promoted on this Si—C bond,
The progress of sputter etching is suppressed or stopped. CF
This is because the x polymer is continuously deposited on the Si—C bond with affinity. Therefore, this effectively acts as a protective film of Si ₃ N ₄ or the like below the C mixing layer (for example, SiC layer).

This C-mixing layer can be formed by oblique ion implantation so as to cover the entire shoulder portion, and this is effective. Therefore, even when over-etching corresponding to the maximum contact depth is performed, the C mixing layer and the stopper layer such as Si are used.
_{The 3} N ₄ film remains, and the desired self-aligned contact hole can be easily processed.

[0033]

Embodiments of the present invention will be described below in detail. However, as a matter of course, the present invention is not limited to the examples described below.

Example 1 As an example of the present invention, B which has a metal mixing layer (or a refractory metal nitride film) on the shoulder portion of Si ₃ N ₄ which is an etching stopper according to the present invention will be described below.
A method of processing a self-aligned contact hole in the PSG / (metal mixing layer + Si ₃ N ₄ ) structure will be described with reference to FIGS. 1 to 7.

In this embodiment, an etching stopper layer 5 is provided on a base having a step (in this embodiment, a semiconductor substrate 1 having a gate electrode 3) (FIG. 1), and an etching target layer 6 is formed on the etching stopper layer 5. In the etching method of the structure having the structure (shown in FIGS. 3 to 6), the shoulder portion of the etching stopper layer 3 is subjected to difficult etching treatment (here, treatment using oblique ion implantation shown in FIG. 2), The layer 6 to be etched is etched.

In this embodiment, the etching stopper layer 5 is provided on the base having the gate electrode 3, the layer 6 to be etched is formed on the etching stopper layer 5, and the layer 6 to be etched is opened. In a method of manufacturing a semiconductor device having an etching step of forming connection holes 9 (see FIG. 5) in a coordinated manner (by self-alignment), a shoulder portion of the etching stopper layer 5 is subjected to difficult etching treatment (see FIG. 2). ), The layer to be etched 6 is etched.

In this case, in the present embodiment, an etching step of processing a contact hole having an opening width of about the gate electrode width in a self-aligned manner is provided, and the shoulder portion of the etching stopper layer 5 covering the gate electrode 3 is provided. In this embodiment, the etching-resistant treatment is applied.

In this embodiment, the etching stopper layer 5 is made of silicon nitride, the layer to be etched 6 is made of silicon oxide, and the etching gas is fluorine-based gas to which CO is added.

In the method for manufacturing a semiconductor device of this embodiment, the refractory metal (Ti, Zn) is applied to the shoulder portion of the etching stopper layer 5 covering the gate electrode 3 by the oblique ion implantation method. , W, Mo, Ag, etc.) is ion-implanted or mixed to form the refractory metal nitride film (mixing layer) 8a.

In this case, the shoulder portion (indicated by reference numeral 8a) of Si ₃ N ₄ which is the stopper layer 5 after metal mixing is
By the subsequent coating of the interlayer insulating film and the reflow heat treatment,
It is possible to form an amorphous or crystalline refractory metal nitride film.

More specifically, in this embodiment, the following steps are performed. Please refer to FIG. On the Si substrate 1 which constitutes the wafer to be processed, SiO ₂ used for the gate oxide film 2 and the like is formed.
Thin film 2 and polycide (WSi3b / polyS) on it
i3a), the gate 3 having a structure, the Si ₃ N ₄ sidewall 4 for protecting the LDD, etc.
Microfabrication is performed by film formation, photolithography, and dry etching with desired processing dimensions and shapes. continue,
The Si ₃ N ₄ thin film is used as an etching stopper layer 5 and C
The entire surface is covered with VD. The thickness of Si ₃ N ₄ is
It is about 100 (nm).

Subsequently, a resist 71 is formed again by photolithography in the same pattern as the gate electrode pattern. With this structure, as shown in FIG. 2, refractory metal ions are mixed (ion implantation) by an oblique ion implantation method.

The ion implantation here is a high-dose (medium-dose) implantation with a low-middle acceleration voltage. By the low and medium acceleration ion implantation, the Si as the etching stopper layer 5 is formed.
_A mixing layer is formed only in an extremely shallow upper layer of ₃ N ₄ . This mixing layer becomes a refractory metal nitride layer by the subsequent BPSG reflow heat treatment. This mixing layer is indicated by reference numeral 8a.

Ion implantation conditions at this time are shown below.
Here, Ti ⁺ was ion-implanted as described below. Accelerating voltage 7~60keV Ti ⁺ 1E14~16cm ^{- 2} Temperature room temperature or Atsushi Nobori infusion, where the very shallow mixing layer thickness (Rp + .DELTA.Rp)
Is 8.0 to 45.0 (nm). Ions to the wafer are obliquely implanted within a range of 10 to 60 ° with respect to a normal incident angle of 0 °. After the ion implantation, the resist is stripped off by ashing, sulfuric acid-hydrogen peroxide solution mixture treatment, or the like.

Subsequently, BPSG is formed as the etching target layer 6.
A film is formed by CVD and reflow heat treatment, and the entire surface of the wafer such as the gate electrode region is flattened (FIG. 3). In this state, a resist 72 having a contact hole pattern is formed by photolithography (FIG. 4).

Further, the wafer to be processed is subjected to SiO ₂ etching having a high selectivity to Si ₃ N ₄ by CHF ₃ / CO chemistry using a magnetron etcher. The interlayer insulating film such as BPSG is rapidly etched by the ion assisted etching with CFx ⁺ ions accelerated by the Vcd bias (FIG. 5).

When this BPSG etching progresses and the stopper Si ₃ N ₄ layer (the portion indicated by reference numeral 8a) at the shoulder portion is exposed on the surface, it is subjected to ion collision of CFx ions and the like and sputtering. In this structure having the melting point metal mixing layer or the high melting point metal nitride layer on the shoulder surface, sputter etching of the surface does not proceed because the metal sputtering effect is low. Therefore, the stopper S
i ₃ N ₄ remains as a protective film.

The BPSG etching conditions having a high selectivity to Si ₃ N ₄ (magnetron RIE by C ₄ F ₈ / CO / Ar chemistry) were as follows in this example. Pressure P = 8 (Pa) RF power Pf = 1200 (W) Process gas C ₄ F ₈ / CO / Ar = 10/50/240 (sccm) Backing gas He = 10 (Pa), 10 (sccm) Electrostatic Chuck -1.2 (kV) Temperature control temperature of lower electrode 20 (° C) Chamber wall temperature 80 (° C) BPSG film thickness 410 (nm / min) ± 8.7 (%) to Si ₃ N ₄ selectivity ratio 18

In the prior art, Si ₃ N ₄ on the shoulder portion, which was easily sputter-etched by ion bombardment, was detected by the etching technique of the present invention even when overetching was performed to estimate the maximum contact depth. The mixed Si ₃ N ₄ (the portion indicated by reference numeral 8a) remains. Therefore, contact hole etching of the source / drain regions can be formed with self-alignment.

Since Si ₃ N ₄ of the stopper layer 5 has a residual film until the end due to the presence of the mixing layer 8a, selective contact etching of SiO ₂ is realized. As a result, processing without a gate contact (W plug) short circuit defect could be realized.

In this embodiment, the stopper S having the refractory metal nitride layer (metal mixing layer) of the present invention is used.
BPSG self-aligned contact hole etching (CHF ₃ / CO chemistry vs. Si with i ₃ N ₄ thin film)
The SiO ₂ etching of ₃ N ₄ high selection ratio) can be modified without departing from the scope of the present invention.

As described in detail above, the contact hole etching of the stopper Si ₃ N ₄ structure having the refractory metal mixing layer formed at the shoulder portion by oblique ion implantation of the refractory metal mixing layer as in this embodiment. With (CHF ₃ / CO chemistry), the self-aligned contact can be finely processed in the source / drain regions about the width of the gate electrode without advancing the etching of the shoulder portion of the stopper layer.

According to this embodiment, the stopper Si ₃
Since N ₄ remains in a required film thickness, neither a gate contact (W plug) short circuit defect nor a breakdown voltage defect occurs.

In the prior art, the yield in wafer manufacturing was reduced due to these electrical defects, but in this embodiment, this yield reduction is suppressed and the quality and performance of the element itself are improved. The semiconductor integrated circuit device can be manufactured.

Example 2 As another example of the present invention, a C mixing layer (or an amorphous or crystalline SiC thin film) is provided on the shoulder portion of Si ₃ N ₄ which is an etching stopper.
A method of processing a self-aligned contact hole having a BPSG / (C mixing layer + Si ₃ N ₄ ) structure will be described. Please refer to FIG. 7 to FIG.

In the method of manufacturing a semiconductor device of this embodiment, as the difficult etching treatment, carbon is ion-implanted or mixed into the shoulder portion of the etching stopper layer 5 covering the gate electrode by the oblique ion implantation method. By doing so, the carbide layer (or C mixing layer) 8b is formed (see FIG. 8).

Further, the shoulder portion 8b of Si ₃ N ₄ after carbon mixing makes it possible to form an amorphous or crystalline carbide layer (SiC) by subsequent coating of the interlayer insulating film and reflow heat treatment. It has become a thing.

More specifically, in this embodiment, the following steps are performed. Please refer to FIG. A SiO ₂ thin film 2 used for a gate oxide film and the like, a polycide electrode 3 (WSix3b / polySi3a, etc.), and Si ₃ N ₄ for LDD protection are formed on a Si substrate that constitutes a wafer to be processed. The sidewalls 4 and the like are finely processed to have desired processing dimensions and shapes by conventional CVD film formation, photolithography, and dry etching. Subsequently, a Si ₃ N ₄ thin film as the etching stopper layer 5 is entirely coated by CVD. The thickness of Si ₃ N ₄ is -100 (n
m).

Then, a resist 71 is formed again by photolithography in the same pattern as the gate electrode pattern. With this structure, depending on the oblique ion implantation method,
The carbon ions are mixed (ion implantation) (see FIG. 8).

The ion implantation is a high dose (medium dose) implantation with a low acceleration voltage. By the low-acceleration ion implantation, the mixing layer 8 is limited to the extremely shallow upper layer of Si ₃ N _4.
b is formed. In the present embodiment, this mixing layer 8b becomes a SiC layer having an amorphous or crystalline property by the subsequent BPSG reflow heat treatment.

The implantation conditions of ion implantation in this case in this embodiment are shown below. Accelerating voltage 5~30keV C ⁺ 1E14~16cm ^{- 2} Temperature room temperature or Atsushi Nobori infusion (a very shallow mixing layer thickness (Rp + .DELTA.Rp) is 3
Ions to the wafer to be processed are obliquely implanted within the range of 10 to 60 ° with respect to the normal incident angle of 0 ° (vertical incidence). After the ion implantation, the resist is removed by ashing, treatment with a sulfuric acid-hydrogen peroxide mixture solution, or the like.

Subsequently, a BPSG film is formed as a layer to be etched by CVD and reflow heat treatment, and the entire surface of the wafer such as the gate electrode region is smoothed (FIG. 9). In this state, a resist 72 having a contact hole pattern is formed by photolithography (FIG. 10).

Further, the wafer to be processed is subjected to SiO ₂ etching having a high selectivity ratio to Si ₃ N ₄ by CHF ₃ / CO chemistry using a magnetron etcher. The interlayer insulating film such as BPSG is rapidly etched by ion-assisted etching with CFx ⁺ ions accelerated by the Vcd bias.

When this BPSG etching progresses and the stopper Si ₃ N ₄ layer (the portion indicated by reference numeral 8b) at the shoulder portion is exposed on the surface, it is subjected to ion collision of CFx ⁺ ions and the like and sputtering, but the C mixing layer, Alternatively, in this structure having the amorphous or crystalline SiC layer 8b on the shoulder surface, the CFx polymer is sufficiently deposited on the Si—C bond with an affinity, and thus the sputter etching of the surface does not proceed. Therefore, the stopper remains as a protective film which is Si ₃ N ₄ .

The BPSG etching conditions having a high selectivity to Si ₃ N ₄ (magnetron RIE by C ₄ F ₈ / CO / Ar chemistry) were as follows in this example. Pressure P = 8 (Pa) RF power Pf = 1200 (W) Process gas C ₄ F ₈ / CO / Ar = 10/50/240 (sccm) Backing gas He = 10 (Pa), 10 (sccm) Electrostatic Chuck -1.2 (kV) Temperature control temperature of lower electrode 20 (° C) Chamber wall temperature 80 (° C) BPSG film thickness 410 (nm / min) ± 8.7 (%) to Si ₃ N ₄ selectivity ratio 18

In the prior art, Si ₃ N ₄ on the shoulder portion, which was easily sputter-etched by ion bombardment, was detected by the etching technique of the present invention even when overetching was performed to estimate the maximum contact depth. The mixed Si ₃ N ₄ thin film (the portion indicated by reference numeral 8b) remains. Therefore, contact hole etching of the source / drain regions can be formed with self-alignment.

Since Si ₃ N ₄ of the stopper layer 5 has a residual film to the end due to the presence of the mixing layer 8b, selective SiO ₂ contact etching is realized. As a result, processing without a gate contact (W plug) short circuit defect could be realized.

The remaining film of Si ₃ N ₄ is continuously formed into Si ₃ N ₄ R consisting of CHF ₃ / O ₂ chemistry.
Contact hole 9 removed by IE etching
Needless to say, the hole is completely opened.

In this embodiment, the amorphous or crystalline SiC layer (C mixing layer) of the present invention is used.
In BPSG self-aligned contact hole etching with stopper Si ₃ N ₄ thin film (Si ₃ N ₄ etching pair Si ₃ N ₄ high selectivity of CHF ₃ / CO chemistry), without departing from the context of the invention, its deformation It is possible. For example, the carbon ion implantation by oblique ion implantation according to the present invention may be a full-face implantation without a resist mask (oblique incidence angle 0 °, that is, vertical incidence).

As described in detail above, according to the present embodiment, the amorphous or crystalline SiC layer (Si-C bond can be formed by the BPSG reflow process) in which the C mixing layer is formed by the oblique ion implantation method is used as the shoulder portion. In the contact hole etching of the stopper Si ₃ N ₄ structure (CHF ₃ / CO chemistry), the self-aligned contact is finely processed in the source / drain region about the width of the gate electrode without advancing the shoulder portion of the stopper layer. it can.

Further, according to this embodiment, the stopper Si ₃
Since N ₄ remains in a required film thickness, neither a gate contact (W plug) short circuit defect nor a breakdown voltage defect occurs.

In the prior art, the yield in wafer production is reduced due to these electrical defects, whereas in the embodiment of the present invention, the reduction in yield is suppressed, and further, the quality and performance of the element itself are reduced. An improved semiconductor integrated circuit can be manufactured.

[0073]

According to the etching method of the present invention and the method of manufacturing a semiconductor device using the etching method, the film thickness of the stopper film shoulder does not decrease even when the self-aligned contact is formed, and therefore, the defect based on this does not occur. It was possible to prevent the occurrence of.

[Brief description of drawings]

FIG. 1 shows the steps of Example 1 in order (1).

FIG. 2 shows the steps of Example 1 in order (2).

FIG. 3 shows the steps of Example 1 in order (3).

FIG. 4 shows the steps of Example 1 in order (4).

FIG. 5 shows the steps of Example 1 in order (5).

FIG. 6 shows the steps of Example 1 in order (6).

FIG. 7 shows the steps of Example 1 in order (1).

FIG. 8 shows the steps of Example 2 in order (2).

FIG. 9 shows steps of Example 2 in order (3).

FIG. 10 shows the steps of Example 2 in order (4).

FIG. 11 shows the steps of Example 2 in order (5).

FIG. 12 shows the steps of Example 2 in order (6).

FIG. 13 is a sectional view showing a conventional technique (1).

FIG. 12 is a sectional view showing a conventional technique (2).

[Explanation of symbols]

1 Si substrate 2 Thermal oxide film (SiO ₂ ) 3 W Polycide gate electrode 4 Sade wall (Si
₃ N ₄ , SiO ₂ ) 5 Etching stopper (Si ₃ N ₄ ) 6 Interlayer insulating film (BPSG) 7 Contact pattern resist 8a Metal mixing layer or metal nitride layer 8b Carbon mixing layer, or amorphous or crystalline SiC layer

[Procedure amendment]

[Submission date] November 17, 1995

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of drawings]

FIG. 1 shows the steps of Example 1 in order (1).

FIG. 2 shows the steps of Example 1 in order (2).

FIG. 3 shows the steps of Example 1 in order (3).

FIG. 4 shows the steps of Example 1 in order (4).

FIG. 5 shows the steps of Example 1 in order (5).

FIG. 6 shows the steps of Example 1 in order (6).

FIG. 7 shows the steps of Example 1 in order (1).

FIG. 8 shows the steps of Example 2 in order (2).

FIG. 9 shows steps of Example 2 in order (3).

FIG. 10 shows the steps of Example 2 in order (4).

FIG. 11 shows the steps of Example 2 in order (5).

FIG. 12 shows the steps of Example 2 in order (6).

FIG. 13 is a sectional view showing a conventional technique (1).

Figure 1 4 is a cross-sectional view showing a prior art (2).

[Explanation of reference numerals] 1 Si substrate 2 Thermal oxide film (SiO ₂ ) 3 W Polycide gate electrode 4 Said wall (Si for use in forming LDD)
₃ N ₄ , SiO ₂ ) 5 Etching stopper (Si ₃ N ₄ ) 6 Interlayer insulating film (BPSG) 7 Contact pattern resist 8a Metal mixing layer or metal nitride layer 8b Carbon mixing layer, or amorphous or crystalline SiC layer

Claims (8)

[Claims] 1. An etching method for etching a structure in which an etching stopper layer is provided on a base having a step and an etching target layer is formed on the etching stopper layer, wherein the shoulder portion of the etching stopper layer is subjected to difficult etching treatment. The etching method is characterized in that the etching is performed on the etching target layer. 2. A contact hole is formed in a self-aligning manner by providing an etching stopper layer on a base having a gate electrode, forming an etching layer on the etching stopper layer, and opening the etching layer. A method of manufacturing a semiconductor device comprising a step of etching, wherein a shoulder portion of the etching stopper layer is subjected to a difficult etching treatment to etch the layer to be etched. 3. An etching step of processing a contact hole having an opening width about the width of the gate electrode in a self-aligning manner, wherein a shoulder portion of an etching stopper layer covering the gate electrode is subjected to a difficult etching treatment. The method for manufacturing a semiconductor device according to claim 2, wherein 4. The etching stopper layer is made of silicon nitride, and the layer to be etched is made of silicon oxide.
3. The method of manufacturing a semiconductor device according to claim 2, wherein the etching gas is a fluorine-based gas to which CO is added. 5. A refractory metal is ion-implanted into a shoulder portion of an etching stopper layer covering a gate electrode by oblique ion implantation, or a refractory metal is ion-implanted.
The method for manufacturing a semiconductor device according to claim 2, wherein the refractory metal nitride film or the refractory metal mixing layer is formed by mixing. 6. The etching stopper layer is made of silicon nitride, and the shoulder portion of the etching stopper layer after metal mixing forms a refractory metal nitride film having an amorphous or crystalline property by a subsequent process. The method for manufacturing a semiconductor device according to claim 5. 7. The carbide layer or the C-mixing layer is formed by ion-implanting or mixing carbon into the shoulder portion of the etching stopper layer covering the gate electrode by oblique ion-implantation in the etching-resistant treatment. The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is formed. 8. The etching stopper layer is made of silicon nitride, and the shoulder portion of the etching stopper layer after carbon mixing forms a carbide layer having an amorphous or crystalline property by a subsequent process. Item 3. A method for manufacturing a semiconductor device according to item 2.