JPH0936086A - Plasma treating method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the shape controllability of a fine pattern and to improve the reduction in an etching rate in a deep groove/deep hole. SOLUTION: In a plasma treatment method for changing gas into plasma under reduced pressure and for treating a sample 1 arranged in a treatment room 5 using the plasma, a bias voltage with a part where a potential in positive direction rapidly increases for each specific period is applied to a sample stand 2, a potential difference exceeding, at least, 5V is set when the voltage rapidly increases and electrons in plasma are accelerated and applied to the sample 1, and at least one portion of the surface electric charge of the sample 1 is neutralized, thus efficiently neutralizing the electric charge at the groove bottom/hole bottom according to an accelerated electron, improving the shape controllability of a fine pattern, and improving, for example, the reduction in the etching rate in a deep groove/deep hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma processing method and apparatus, and more particularly to a plasma processing method and apparatus suitable for processing using a bias applied to a sample.

[0002]

2. Description of the Related Art FIG. 11 shows a conventional example of RF bias.
The sample 1 is placed on the sample table 2, the high frequency power for bias 3 outputs the high frequency shown in FIG. 12, and a sinusoidal voltage is applied via the capacitor 4. The processing gas is exhausted while flowing into the processing chamber 5, and the plasma generation high-frequency power source 6 to the coil 7 and the insulator 8 are supplied.
Plasma is generated by the high frequency power applied via the. Since the amount of electrons supplied from the plasma to the sample is as large as several tens to several hundreds times the amount of positive ions, negative charges are accumulated on the sample 1 side of the capacitor 4. Due to this charge, a negatively shifted voltage appears on the substrate as shown in FIG. This negative voltage accelerates the positive ions, which are the etching species, and makes them vertically incident on the sample 1 to enable vertical etching. However, as the sample pattern becomes finer, various problems described below arise due to the charge-up of positive charges on the bottoms of the grooves and holes.

[0003]

In the sample surface potential waveform of FIG. 13, the peak potential is almost the plasma potential (V
Since the peak of the positive voltage for accelerating the electrons in the positive cycle in which the electrons are incident on the sample is almost 0, the electrons are hardly accelerated and are incident on the substrate. Since the capacitance component of the sample surface is zero or a large value, the sample surface potential is generally almost equal to the sample potential.

When a fine pattern is processed using such a bias application method, local charge-up occurs in the sample. Ions are accelerated and vertically enter the sample to reach the bottom surface of the fine pattern, whereas electrons are not accelerated and areotropically incident on the sample, so that the fine pattern is blocked by the mask and reaches the bottom surface. Not possible (electronic shading phenomenon). Therefore, the side surface of the fine pattern is charged up negatively and the bottom surface is charged up positively.

The charge-up caused by the electron shading causes various problems in plasma etching. One of the most serious problems is local abnormal side etch (notch) in polysilicon processing for gate.
Is the occurrence of.

Further, charge-up due to the electron shading phenomenon occurs also in the processing of metal wiring, and causes damage to the gate oxide film. Positive charges generated on the bottom surface of the fine pattern by electron shading are collected in the floating gate connected to the metal wiring,
Damage such as dielectric breakdown occurs in the gate insulating film between the floating gate and the substrate silicon.

In addition to this, the charge-up due to the electron shading phenomenon is a problem in etching fine holes such as trenches and contact holes, which causes irregular shapes such as sub-trench and bowing. As in the case of etching polysilicon, the side surface of the hole is negatively charged and the bottom surface of the hole is positively charged. Due to this charge-up, the orbits of ions, which are etching species, are bent, and the ions are incident on the side surface of the hole and the end of the hole bottom. For this reason, the side surface of the hole and the end of the bottom surface of the hole are etched, and irregular shapes such as bowing and sub-trench are generated.

As one method for solving this problem, Japanese Patent Laid-Open No. 6-61182 discloses a plasma potential (V
By applying a pulse voltage having an amplitude (about 20 volts) of the difference between p) and the floating potential (Vf) and providing a long period during which the sample surface potential (Vs) is equal to the plasma potential (Vp), It is described that electrons are injected into the sample to neutralize the charge on the sample surface. However, since the accelerating energy of the electrons incident on the sample is zero, there is a drawback that the electrons are not sufficiently neutralized at the deep grooves / holes or the bottom of the fine pattern.

The present invention eliminates the electron shading phenomenon and solves various problems caused by the electron shading phenomenon such as notch, charge-up damage, bowing, sub-trench, micro-loading, and reduction of etching rate in the hole depth direction.

An object of the present invention is to provide a plasma processing method and apparatus capable of obtaining a desired etching shape by improving the shape controllability of a fine pattern and improving the etching rate decrease in deep grooves / deep holes. is there.

[0011]

Means for Solving the Problems In plasma processing for converting a gas into plasma under reduced pressure and processing a sample placed in a processing chamber using the plasma, a positive potential is set to a predetermined value on a mounting means for mounting the sample. A bias voltage having a portion that rapidly increases in each cycle is applied, and in the vicinity of the sudden increase in the voltage, electrons in the plasma are accelerated with a potential difference of at least 5 V and are incident on the sample, and at least one of the sample surface charges is charged. This is achieved by neutralizing the parts.

[0012]

In the present invention, there is a period in which the pulse bias voltage is applied to the sample, the sample surface potential (Vs) is set to a value larger than the plasma potential (Vp) by at least 5 V or more, and electrons are accelerated to be incident on the sample. Therefore, accelerated electrons can reach the bottom surface of the fine pattern on the sample surface, prevent the positive charge from being charged up on the bottom surface to prevent notches and the like, and increase the processing speed in the deep groove / hole. It is possible to prevent the deterioration.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a configuration diagram showing an electrode portion to which a bias voltage is applied in the plasma processing apparatus of the present invention.
The electrode portion of this figure is provided, for example, in place of the sample stage portion of the conventional apparatus shown in FIG. In this figure, the same symbols as in FIG. 11 indicate the same members. This embodiment uses a bias pulse power source 3'shown in FIG. 1 in place of the bias high frequency power source 3 of the conventional plasma processing apparatus shown in FIG. The bias pulse power supply 3'periodically outputs a pulse in the positive direction as shown in FIG. When this pulse is applied to the sample 1 via the capacitance component 4, the sample surface potential (Vs) as shown in FIG. 2B is applied to the sample 1. As shown in this figure, in the portion of the pulse width (τw) where the potential of Vs rapidly increases, the value of Vs becomes higher than the plasma potential (Vp) +5 volts, and the electrons are accelerated and enter the sample. Here, τw is the pulse width, T is the pulse period, Vpls is the pulse amplitude, Vp is the plasma potential, and V _DC is the sample 1
Is the DC component of the voltage applied to.

The changes of _VDC / electron acceleration voltage / acceleration electron ratio when the pulse period T is changed under the predetermined values of τw and Vpls are shown in (a) / (b) / (c) of FIG. Show. In FIG. 3, the pulse amplitude (Vpls) is approximately Vp (2
(Τw / T) dependence when the electron accelerating voltage is almost zero, which is equal to 0 volt), and is also shown in the graph of the broken line.

When (τw / T) <0.001, V _DC is approximately 0 V and the acceleration electron ratio is about 0.1 or less. The accelerating electron ratio is close to 1.0, and the higher the electron accelerating voltage, the greater the charge neutralization effect. From FIG. 3C, when (τw / T) is about 0.001 or less, the ratio of accelerating electrons is small and the effect of electron acceleration is difficult to be obtained. Further, in the region of _VDC > -5V, the acceleration of ions is insufficient, so that it is difficult to obtain a vertical shape, and the etching rate is also low, which is not a practically preferable region. However, when the high selection ratio and the low damage are given the highest priority, the upper limit of _VDC may not be taken into consideration.

Further, in the region of _VDC <Vp-Vpls + 5, the electron acceleration voltage is 5 V or less, so that it is difficult for electrons to reach the bottom surface of the deep groove or deep hole. Therefore, it is a region in which it is difficult to improve the shape due to electron acceleration and the reduction in the etching rate in the deep groove / hole. When (τw / T) becomes large, the electron acceleration voltage rapidly decreases as shown in FIG. 3 (b). The region where the accelerating voltage is 5 V or higher varies depending on the type of plasma (electron temperature, electron density, type of ions, etc.), but is generally (τw / T) <0.1, preferably (τw /
T) <0.05. Therefore, the part where the preferable characteristics are obtained is the part where -5volt> _VDC > Vp-Vpls + 5 volts 0.05> ([tau] w / T)> 0.001. This corresponds to the portion shown by the thick line in FIG. In the case shown by the broken line in FIG. 3A, there is no desired region.

The average electron acceleration energy during the period in which the electron current flows into the sample 1 is almost proportional to Vpls-Vp + _VDC , and when this value is 5 V or more, the effect of neutralizing charge at the bottom of the deep hole or groove appears. Then, when this value is 10 volts or more, the above effect becomes remarkable.

When the value of Vpls-Vp + _VDC is about 200 V or more, the adverse effects such as the abrasion of the resist film and the increase of damage are remarkable.

The absolute value of Vp-V _DC is almost proportional to the average energy of ion acceleration. Vpls-Vp + V _DC
The value of is optimized within the range of the above values according to the material of the sample, the pattern, the aspect ratio of the hole, and the like.

In the basic pulse shown in FIG. 2A, Vp
By optimizing Is, (τw / T), etc., the electron acceleration voltage and the ion acceleration voltage can be set to desired values, but (τw / T) is desirable as shown in FIG. 3 (a). The range is narrow. The small range of (τw / T) is limited by the small absolute value of V _DC . To improve this, alternating current with a shorter period than the pulse period,
It is only necessary to superimpose a pulse train having a large (τw / T) in a short cycle and set the minimum value of the absolute value of V _DC by the superposed wave.

FIG. 4 shows an example in which an alternating current having an amplitude Vrf and a pulse having an amplitude Vpls are superposed. V _{DC at} this time
The − (τw / T) characteristic is as shown in FIG.
By setting Vrf> 5 + Vp volts, (τ
Even in a small range of w / T, _VDC <−5 V and desired characteristics can be obtained. The minimum value of (τw / T) in the preferable region shown by the thick line in FIG. 4B corresponds to an accelerating electron ratio of about 0.1 or more (see FIG. 3C).

Another method of setting the minimum absolute value of V _DC is shown in FIGS. FIG. 5A shows the amplitude Vrf.
Is an example in which a pulse is superimposed every n cycles of the alternating current in the vicinity of the maximum peak of the alternating current (100 kHz-100 MHz).

FIG. 5B shows an alternating current (100 kHz-10
This is an example in which the amplitude of 0 MHz) is changed at regular intervals. FIG. 6 shows details in the vicinity of the sharp increase in the amplitude. FIG. 6A shows the output voltage of the pulse bias power supply 3 ′, and FIG.
Shows the surface potential pressure (Vs) of the sample 1, (c) shows the outline of the electron current and ion current at each time, and (d) shows the outline of the electron acceleration voltage.

At the maximum voltage portion where the amplitude sharply increases, the sample surface potential (Vs) becomes Vp + 5 volts or more, and the electrons are accelerated and enter the sample. Therefore, accelerated electrons can reach the bottom of the fine pattern on the sample surface,
It is possible to prevent the positive charges from being charged up on the bottom surface to prevent the occurrence of notches and the like, and also to prevent the processing speed from decreasing in the deep groove / hole. In the case where the absolute value of V _DC is limited to be small by superimposing an alternating current or a pulse train, as shown in FIGS. 6 (b) and 6 (d),
As the value of Vs, with the period of Vp + 5 volts or more,
Below Vp + 5 volts, there is a period near Vp.

By the way, the pulse bias method described above has a drawback that the average of the ion accelerating voltage fluctuates in one cycle, as shown in FIGS. 6 (b) and 7 (b). In order to improve this, an example in which the voltage of the sample stage is clamped and improved is shown in FIG.

A high speed diode 10 and a set voltage holding capacitor 11 are used, and a filter inductance Lc is used.
It is connected to the clamp power supply via 1 to clamp the decrease in the average value of the ion acceleration voltage to a predetermined voltage. When the basic pulse shown in Fig. 2 (a) is applied, the clamp voltage
Vclamp is Vclamp = V _DC −v (v is 0
10 volt). In this case, as shown in FIG. 8B, the capacitance component (C
Since the capacitance component (Cs) on the sample surface is significantly larger than that in 0), the change in the sample surface potential (Vs) due to the ion incidence can be significantly reduced by clamping the voltage of the sample stage. When the waveform shown in FIG. 5B whose amplitude changes periodically is used, the clamp voltage Vcla
mp, Vclamp = V _DC −Vrf−v (v is 0
If about 10 volt), as shown in FIG.
The same effect as in (b) can be obtained.

If there is a capacitance component (Ce: capacitance of the electrostatic adsorption film, for example) between the sample 1 and the sample table 2 and the value thereof is much smaller than Cs, the result is shown in FIG. Also, the method of clamping the sample table is less effective. In this case, as shown in FIG. 9, an electrode which comes into direct contact with the sample 1 is provided, a set voltage holding capacitor 12 is connected to the electrode via a high speed diode 10, and a filter inductance Lcl is further provided. If it is connected to the clamp power source, the same effect as in FIG. 8 can be obtained.

In a normal plasma, 0.01 μs <τw <10 μs, preferably 0.01 μs <τw <0.5 μs 0.001 <(τw / T) <0.1, preferably 0.001 <(τw /T)<0.05 Vp + 10 volt <Vpls -5 volt <V _DC <Vp-Vpls + 5 volt Vp is about 10 to 20 V. In this embodiment, the case where plasma is generated by inductively coupled high frequency is described. It can be commonly applied to, for example, microwave plasma, plasma by a high frequency + DC magnetic field, ECR plasma, etc., regardless of the plasma generation method.

The output waveform of the bias pulse power source 3'is not limited to the waveform shown in FIG. 4-a).
The surface potential (V) of the sample is also shown in FIGS. 4 and 5 in which alternating current is superposed, in which alternating current amplitude is changed, or in which plural pulses shown in FIG. 10 are used.
The present invention can be similarly applied if the sum (τw) in one cycle of the electron acceleration period and the cycle (T) of which the s) becomes 5 V or more higher than the plasma potential (Vp) satisfy the above-mentioned conditions.

As described above, according to the present embodiment, the sample is provided with the pulse bias power source for accelerating the electron of 5 V or more, and the DC component V _{DC and} (τw / T) of the voltage applied to the sample are −5 V <V _DC. Since <Vp-Vpls + 5 volts 0.001 <(τw / T) <0.1 is set, the electrons are accelerated at a potential of 5 volts or more to neutralize positive charge-up on the bottom surface of the fine pattern, Notch generation, micro loading,
It is possible to prevent a decrease in the etching rate in the deep groove / hole, and the ion acceleration voltage is set to a predetermined value or higher to prevent a decrease in the etch rate and a decrease in the directionality of the ions. As a result, charge is effectively neutralized at the groove bottom / hole bottom by accelerated electrons, and the shape controllability of the fine pattern and the deep groove /
The etch rate decrease in deep holes is improved.

[0031]

According to the present invention, a bias voltage having a portion in which the positive direction potential sharply increases every predetermined period is applied to the sample mounting means, and a potential difference exceeding at least 5 V is applied in the vicinity of the sharp increase in the voltage. Then, the electrons in the plasma are accelerated to enter the sample, and at least a part of the surface charge of the sample is neutralized, so that the charge at the groove bottom / hole bottom is efficiently neutralized by the accelerated electrons. As a result, the shape controllability of the fine pattern and the etching rate decrease in the deep groove / deep hole are improved, so that the shape controllability of the fine pattern and the etch rate decrease in the deep groove / deep hole can be improved. effective.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an electrode unit used in a plasma processing apparatus of the present invention.

FIG. 2 is a diagram showing an output waveform of a bias pulse power source of the apparatus of FIG. 1 and a bias voltage waveform applied to a sample.

[FIG. 3] V _DC / electron acceleration voltage / acceleration electron ratio (τw /
It is a figure which shows T) dependence.

FIG. 4 is a diagram showing output waveforms of another embodiment of the bias pulse power supply of the apparatus of FIG.

5 is a diagram showing output waveforms of another embodiment of the bias pulse power supply of the apparatus of FIG.

FIG. 6 is an operation explanatory diagram when the output waveform of the bias pulse power supply of FIG. 5B is used.

FIG. 7 is an operation explanatory diagram when the output waveform of the bias pulse power supply of FIG. 5B is used.

8 is a circuit configuration diagram showing a clamp circuit of the device of FIG.

9 is a circuit configuration diagram showing a clamp circuit of the apparatus of FIG.

10 is a circuit configuration diagram showing a clamp circuit of the device of FIG.

FIG. 11 is a diagram showing a conventional plasma processing apparatus.

FIG. 12 is a diagram showing the diameter of the output of the high frequency bias power supply in FIG.

13 is a diagram showing a waveform of a bias voltage applied to the sample in FIG.

[Explanation of symbols]

1 ... sample, 2 ... sample stage, 3 ... high frequency power supply for bias,
3 '... Bias pulse power supply, 4 ... Capacitance element, 5 ... Processing chamber, 6 ... Plasma generating high frequency power supply, 7 ... Coil, 8 ...
Insulator, 10 ... High speed diode, 11 ... Capacitor for holding set voltage.

Claims (7)

[Claims] 1. A plasma processing method for converting a gas into plasma under a reduced pressure and processing a sample placed in a processing chamber using the plasma, wherein a positive potential is applied to a mounting means for mounting the sample at predetermined intervals. A bias voltage having a sharply increasing portion is applied, and a potential difference exceeding at least 5 volts is applied in the vicinity of the sharp increase in the voltage to accelerate electrons in the plasma to make them enter the sample, and at least the surface charge of the sample A plasma treatment method, which comprises partially neutralizing. 2. A plasma processing method for converting a gas into plasma under a reduced pressure and using the plasma to process a sample placed in a processing chamber, wherein a placing means for placing the sample has an AC voltage and a pulse property of a predetermined cycle. A voltage composed of a mixed voltage is applied, and in the vicinity of a sudden increase in the positive potential of the mixed voltage, a potential difference exceeding at least 5 V is applied to accelerate electrons in the plasma to make them enter the sample, and the surface of the sample A plasma processing method characterized by neutralizing at least a part of electric charges. 3. A plasma processing method for converting a gas into plasma under a reduced pressure and processing a sample placed in a processing chamber by using the plasma, the amplitude of which changes on a mounting means for mounting the sample at predetermined intervals. An AC voltage or a pulsed voltage is applied, and in the vicinity of a sharp increase in the amplitude of the voltage, a potential difference exceeding at least 5 V is applied to accelerate electrons in the plasma to make them enter the sample, and at least the surface charge of the sample A plasma treatment method, which comprises partially neutralizing. 4. A plasma processing method for converting a gas into plasma under a reduced pressure and processing a sample placed in a processing chamber by using the plasma, wherein an alternating voltage which changes every predetermined period on a mounting means for mounting the sample. Alternatively, a pulsed voltage or a voltage composed of a mixture of these is applied, and the surface potential of the sample at that time has a period of being near the plasma potential in the vicinity of the sample or higher, and the surface potential of the sample during that period. Has a period on both sides of above and below with respect to (plasma potential +5 V). 5. A sample placing means, a processing chamber containing the sample placing means, a means for supplying gas into the processing chamber, a means for exhausting the processing chamber, and a plasma in the processing chamber. In the plasma processing apparatus, the output of the power supply for adding an electron acceleration function, which has a portion in which the positive direction potential sharply increases every predetermined period, is applied to the sample stage via a capacitive component, and at least 5 A plasma processing apparatus having a period in which electrons are accelerated by a potential difference exceeding a volt and are incident on the sample. 6. The plasma processing apparatus according to claim 1, wherein a portion of the positive-direction electric potential that sharply increases in a predetermined cycle is less than 5% of the cycle. 7. The plasma processing apparatus according to claim 1, wherein the portion in which the positive-direction potential sharply increases every predetermined period is 0.1% or more and less than 5% in the period.