JPH08241885A - Method and apparatus for surface treating - Google Patents

Abstract

PURPOSE: To reduce the charge-up due to electron shading and to eliminate various problems due to the shading by applying the voltage of a pulse waveform having the rising speed of a specific value or more as a bias voltage. CONSTITUTION: Microwaves generated by a magnetron 18 are introduced into a discharge tube 20 via a waveguide 19, and a plasma of high density is generated by the electron cyclotron resonance of the introduced microwaves and the magnetic field formed by a coil 21. The plasma is grounded by a ground electrode 22 so that the plasma is not largely changed due to the application of the pulse. As a sample, a resist mask is formed on a polysilicon film to be used. The sample 1 is connected to an electrostatic attraction constant-voltage source 24 and a pulse power source 17 via electrostatic attraction insulating ceramic. In order to generate the pulse voltage of the rising speed of 10<3> V/μs or more, the pulse power source of the rising speed of 10<3> V/μs or more is required at the lowest.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface treatment of a sample using plasma, and more particularly to a method of applying a bias voltage to the sample.

[0002]

2. Description of the Related Art The most typical conventional bias application method called RF bias is shown in FIG. Sample to be etched 1
Is connected to a high frequency power supply 3 via a capacitor 2. A high-frequency power source 3 applies a sinusoidal voltage as shown in FIG. At this time, since the electrons supplied from the plasma 4 are several tens of times larger than the ions, negative charges are accumulated on the sample side of the capacitor 2. Due to this capacitor charge, a negatively shifted voltage appears on the substrate as shown in FIG. This negative voltage accelerates the positive ions, which are etching species, and makes them vertically incident on the substrate, thereby enabling vertical etching. In addition to this, as an idea, a method of using a voltage of a pulse waveform as a bias has already been devised in Japanese Patent No. 1095402 and Japanese Patent Laid-Open No. 6-61182. However, there has been no example so far focusing on the importance of the pulse rising speed.

[0003]

In the substrate bias waveform of FIG. 4, since the positive voltage for accelerating the electrons in the positive cycle in which the electrons enter the sample is almost 0, the electrons are hardly accelerated. Incident on the substrate. When a fine pattern is processed using such a bias application method, local charge-up occurs in the sample. The mechanism of this charge-up generation is shown in FIG. Since the ions 5 are accelerated and enter the sample, they reach the bottom surface of the fine pattern, while the electrons 6 are not accelerated and areotropically incident on the sample, so that the fine pattern is blocked by the mask 7 and reaches the bottom surface. Not possible (electronic shading phenomenon). Therefore, the fine pattern is charged up negatively and the bottom surface is charged up positively. The charge-up due to this electron shading causes various problems in plasma etching. One of the most important problems is the occurrence of local abnormal side etching (notching) in the processing of gate polysilicon. The mechanism of occurrence of this notching is shown in FIG. Due to the positive charge-up on the bottom surface of the fine pattern due to the electron shading phenomenon, the ions 5 as etching species are repelled and enter the side surface of the pattern. Ions incident on this side surface are notched at the interface between the polysilicon layer 8 and the underlying silicon oxide film layer 9.
Generates 0.

In addition, the charge-up caused by electronic shading is also a problem in the processing of metal wiring, which causes breakdown of the gate insulating film. The mechanism of occurrence of this gate insulating film breakdown is shown in FIG. Positive charges generated by electron shading are collected in the floating gate 12 connected to the metal wiring 11,
A strong electric field is generated in the gate insulating film 14 between the floating gate 12 and the substrate silicon 13 to cause dielectric breakdown.

In addition to this, the charge-up due to the electron shading phenomenon is also a problem in the etching of fine holes such as trenches and contact holes, which causes abnormal shapes such as sub-trench and bowing. This mechanism is shown in FIG. As in the case of polysilicon etching, electron shading charges up the side of the hole negatively and the bottom of the hole positively. Due to this charge-up, the ions 5 that are the etching species are bent, and the ions enter the side surface of the hole or the end of the hole bottom. Therefore, the side surface of the hole and the end of the bottom surface of the hole are etched, so that the bowing 15, the sub-trenches 16 and the like have abnormal shapes.

The present invention reduces the charge-up caused by electronic shading and solves the above-mentioned problems caused by electronic shading.

[0007]

Electron shading results from the fact that electrons are not accelerated towards the substrate. Therefore, in order to suppress charge-up due to electron shading, the substrate potential may be set higher than the plasma potential, and an electric field that accelerates electrons may be generated between the substrate and plasma. However, it was impossible to raise the substrate potential higher than the plasma potential by the conventional bias applying method.

The present invention generates an electric field for accelerating electrons on a substrate by applying a high-speed pulse voltage instead of the conventional sinusoidal bias voltage. Specifically, as shown in FIG. 9, the bias power source is replaced with a conventional sinusoidal high frequency power source, a pulse power source 17 is installed, and a rising speed of 10 ³ V / μs or more is set as a bias voltage from the pulse power source. Apply pulse voltage. With this, the maximum value of the potential of the object to be processed during the surface treatment can be made higher than the potential of the plasma. Particularly, the duty ratio of the pulse is preferably 5% or less.

[0009]

Consider a case where a high-speed pulse waveform voltage as shown in FIG. 10 is applied from the pulse power supply 17 in the apparatus of FIG. 9 as in the present invention. In this case, a bias waveform as shown in FIG. 11 appears on the substrate. While the input voltage is 0, the substrate is in a potential state called floating potential, which is about 20 V lower than the plasma potential. During this time, positive charge-up due to electronic shading occurs on the bottom surface of the fine pattern on the substrate as in the case of FIG. On the other hand, the substrate has a potential higher than the floating potential while the positive pulse voltage is applied. When the potential during the application of the pulse voltage is higher than the plasma potential, the voltage of the difference between the substrate potential and the plasma potential (hereinafter referred to as electron acceleration voltage) accelerates the electrons as shown in FIG. To do. Positive charge-up on the bottom surface of the fine pattern is neutralized. It is considered that this solves various problems caused by electronic shading such as notching.

Next, the conditions of the pulse for generating this electron acceleration voltage on the substrate will be examined. First, consider the rising speed of the pulse. When the rising speed of the pulse is slow, a voltage drop occurs in the capacitor between the sample and the power supply in FIG. 9 due to the electron current flowing from the plasma until the substrate potential reaches the plasma potential, and a positive potential is generated on the substrate. Will not do. Therefore, in order to generate the electron acceleration voltage on the substrate, the rising speed of the pulse must be higher than the speed of the voltage drop due to the electron current shown in Formula 1.

[0011]

[Equation 1]

Assuming that the electron temperature T _e is 2 eV, the plasma density n _e is 10 ¹¹ / cm ^3, and the capacitance value of the electrostatic chuck is 30 pF / cm ² , the voltage drop rate given by Equation 1 is obtained. And about 10 ³ V / μs. Therefore, it is considered that a rising speed of at least 10 ³ V / μs or more is required to generate the electron acceleration voltage on the substrate. Actually pulse width 1 μs, magnitude 100 V,
A pulse having a repetition frequency of 1 KHz was applied, and the relationship between the pulse rising speed and the electron acceleration voltage was measured. The result is shown in FIG. The electron acceleration voltage has a rising speed of 10 ³ V / μ
It occurs from s or more and has a maximum value at 5 × 10 ³ V / μs or more.

Next, the magnitude of the pulse voltage will be examined. It is assumed that there is no voltage drop of the substrate during the pulse rise and a positive voltage of the same magnitude as the pulse voltage is generated on the substrate by applying the pulse bias. A voltage having a magnitude obtained by subtracting a difference of about 20 V between the plasma potential and the floating potential from this positive voltage is the actual electron acceleration voltage. If the electron acceleration voltage has a value sufficiently larger than the lateral kinetic energy of the electron of about 3 eV, the electron can be vertically incident. Such electron accelerating voltage must be at least 10V or higher. Therefore, as a voltage actually applied to the substrate, a positive pulse voltage of at least 10V + 20V, that is, 30V or more is required.

Next, the pulse width will be examined. When the width of the positive pulse is long, the substrate potential decreases at a rate of 10 ³ V / μs due to the inflow of electrons while the positive voltage is applied, and returns to the floating potential after a certain period of time. Assuming that the magnitude of the pulse voltage is 10 ² V, the time required for the substrate potential to reach the floating potential is 0.1 μs, and the pulse width is preferably shorter than this.

Finally, the pulse repetition frequency will be considered. The relationship between the pulse repetition frequency and the substrate potential waveform was calculated by simulation. The results are shown in FIG. 14, in which the horizontal axis represents the duty ratio of the pulse (repetition frequency × pulse width) and the vertical axis represents the magnitude of the electron acceleration voltage. This result is divided into the following three areas. (A) When the repetition frequency is very small (duty ratio 0.
5% or less) In this region, the magnitude of the electron acceleration voltage generated on the surface of the substrate at the time of applying a pulse is not affected by the repetition frequency and shows a constant value. At this time, the voltage waveform appearing on the substrate surface is shown in FIG. The etching is mainly performed in a floating potential state. Positive charge-up caused by electron shading between floating potentials is mitigated by the intermittently applied positive pulse voltage. Therefore, the effect of eliminating charge-up increases as the number of pulse repetitions increases.

(B) When the repetition frequency is appropriately small (duty ratio 0.5% to 5%) In this region, the electron acceleration voltage decreases as the repetition frequency increases. The substrate surface potential waveform at this time is shown in FIG.
6 is shown. Self-bias is generated by the negative shift of the substrate potential with respect to the input voltage. In this case, since a positive voltage for accelerating the electrons is also generated at the moment of applying the pulse, both high-speed etching by self-bias and charge-up elimination by the electron acceleration voltage can be realized.

(C) When the repetition frequency is too high (duty ratio 5% or more) In this region, no electron acceleration voltage appears on the substrate surface. The waveform of the substrate surface potential at this time is shown in FIG. Since the substrate potential shifts too negatively with respect to the input voltage, the substrate potential when the pulse voltage is applied becomes smaller than the plasma potential. Therefore, there is no action for eliminating the charge-up caused by the decrease in electronic shading. From the above, it is necessary to use the repetition frequency in the region (A) or (B) in order to suppress the electron shading by applying the pulse bias. At the repetition frequency in the region (A), a large negative bias is not generated in the substrate, so that etching with high selectivity and small influence of the electron shading phenomenon is possible. On the other hand, at the frequency in the region (B), in addition to the effect of suppressing electron shading by the electron accelerating voltage, ion acceleration by self-bias can be realized, so that vertical and high-speed etching can be performed.

The operation of the present invention for various problems caused by the electronic shading phenomenon will be described below.

First, FIG. 18 shows a mechanism by which the present invention solves the problem of notching in the processing of gate polysilicon. According to the present invention, not only the ions 5 but also the electrons 6 are vertically incident on the pattern, so that the charge-up on the bottom and side surfaces of the fine pattern is eliminated. Therefore, the ions 5 as etching species are not repelled at the bottom surface of the pattern, and a vertical shape without notching is obtained.

Next, a mechanism by which the present invention solves the problem of charge-up damage in metal wiring processing is shown in FIG.
9 shows. According to the present invention, since the positive charge-up on the bottom surface of the fine pattern is eliminated, the phenomenon that the positive charges are concentrated on the floating gate 12 is eliminated, and the gate insulating film 13 between the floating gate 12 and the substrate 13 is not damaged. .

Finally, FIG. 20 shows a mechanism for suppressing the occurrence of bowing and sub-trench in the processing of fine holes such as trenches and contact holes according to the present invention. According to the present invention, charge-up due to electron shading does not occur, so that the ions 5 vertically enter the substrate. Therefore, a vertical shape without sub-trench or bowing is obtained.

[0022]

【Example】

(Embodiment 1) FIG. 21 shows an example of an apparatus in which the pulse bias of the present invention is applied to a microwave etching apparatus for processing polysilicon for gates. In this device, the magnetron 18
The microwave generated in the discharge tube 20 through the waveguide 19.
The structure is such that high density plasma can be generated by the electron cyclotron resonance of the introduced microwave and the magnetic field generated by the coil 21. In this apparatus, the plasma is grounded by the earth electrode 22 having a surface area of 4 times or more of the surface area of the sample 1 so that the potential of the plasma does not largely change by the application of the pulse.
As a sample 1 to be etched, a 6-inch S
The i-wafer was thermally oxidized to deposit a polysilicon film, and a resist mask was formed on the polysilicon film. This sample 1 is connected to a constant voltage source 24 for electrostatic attraction and a pulse power source 17 via an insulating ceramic 23 for electrostatic attraction having a capacitance of 5 nF. In order to generate a pulse voltage with a rising speed of 10 ³ V / μs or more as in the present invention, at least a rising speed of 10 ³
A pulse generation power source of V / μs or more is required. In this embodiment, a pulse power source is composed of a rising speed arbitrary waveform generator 25 and a high-speed wideband power amplifier 26 having a maximum rising speed of 5 × 10 ³ V / μsec, and a 5 V pulse signal from the arbitrary waveform generator 25. Is amplified 20 times by the high-speed broadband power amplifier 26, so that a pulse of several 100 V magnitude can be generated at a rising speed of 5 × 10 ³ V / μs. FIG. 22 shows an example of the pulse waveform generated by this power supply system. As shown in FIG. 22, when a high-speed pulse is generated, the pulse waveform does not become rectangular. Also, the rise of the pulse is not linear. Therefore, there are several ways to define the pulse width and the rising speed. In this specification, the pulse width is defined as the half-value width of the pulse. Further, the pulse rising speed is defined by the maximum value of the slope of the pulse rising portion.

With this apparatus, the polysilicon fine pattern formed on the silicon oxide film was etched using chlorine plasma. First, the pulse voltage was 100 V, the pulse width was 1 μs, the pulse repetition frequency was fixed at 1 KHz, the rising speed of the pulse was changed, and the notching magnitude was examined. The result is shown in FIG. It can be seen that the size of the notch starts to decrease at the rising speed of 10 ³ V / μs and reaches the minimum value at 5 × 10 ³ V / μs or more.

Next, the magnitude of the pulse was fixed at 100 V, the pulse width was fixed at 50 ns, which was a value of 100 ns or less, and the notch magnitude was examined by changing the pulse repetition frequency. The results are shown in FIG. 23 with the notching magnitude on the vertical axis and the duty ratio (pulse width × repetition frequency) on the horizontal axis. In the region where the duty ratio is 5% or less, that is, in the region where the pulse repetition frequency is 1 MHz or less, the notch size is reduced by increasing the pulse repetition frequency and increasing the pulse injection frequency. Therefore, it is understood that the pulse voltage application of the present invention has an effect of suppressing notching. Of these, the duty ratio is 0.5% to 5%, that is, the repetition frequency is 1
In the range of 00 MHz to 1 MHz, no notching is observed, and self-bias is generated, resulting in 1 μm.
High-speed etching of m / min or more is possible. on the other hand,
In the range of the pulse duty ratio of 0.5% or less, that is, the repetition frequency of 100 MHz or less, notching can be suppressed and high selective etching with a selectivity of 100 or more can be performed.

Using the apparatus of this embodiment, a pulse width of 50
A pulse voltage of ns and a duty ratio of 1%, that is, a repetition frequency of 200 KHz was applied to etch the fine pattern of polysilicon. FIG. 24 shows a cross-sectional electron micrograph of the polysilicon processed shape at this time, and FIG. 25 shows the processed shape when etching is performed using an RF bias for reference. Notching was observed when the RF bias was used, whereas notching disappeared and a vertically machined shape was obtained when the pulse bias of the present invention was used.

The effect of the present embodiment is not limited to the microwave etching apparatus, and the same effect can be obtained in a plasma etching apparatus using another discharge method such as an inductively coupled high frequency plasma etching apparatus and a helicon plasma etching apparatus. is there.

Example 2 Using the apparatus of Example 1, metal wiring was processed.

First, the pulse rising speed is set to 5 × 10.
^The pulse width is fixed to 50 V ns at ³ V / μs, and the pulse repetition frequency is from 10 MHz to 50 K.
The dielectric breakdown rate of the gate insulating film was examined by changing the frequency in the range of Hz. The result is shown in FIG. Duty ratio 5%
The following area, that is, pulse repetition frequency 1 MHz
In the following region, the probability of gate breakdown is reduced by increasing the pulse repetition frequency and increasing the pulse input frequency. From this, it is understood that the pulse has an effect of reducing charge-up damage.

Charge-up or notching due to electron shading is a phenomenon that occurs at the timing when the remaining film thickness of the film to be etched becomes 0, that is, during overetching after just etching. Therefore, it is not necessary to apply the pulse bias of this method from the start to the end of etching, and even if the pulse bias of this method is applied only for overetching after just etching, it is effective in reducing charge-up and notching. Therefore, in Examples 3, 4, and 5, a method of switching the bias before and after the just etching was examined.

(Embodiment 3) Using the apparatus of Embodiment 1, the polysilicon for gates was processed. In this embodiment, the rising speed of the pulse is 5 × 10 ³ V / μs and the pulse width is 50.
ns, and as shown in the timing diagram of FIG. 27, the duty ratio is reduced by reducing the pulse repetition frequency from 10 MHz to 500 KHz between the start of etching and the timing of just etching at which the remaining polysilicon film thickness becomes 0. Was changed from 50% to 1%. In overetching after just etching, the pulse duty ratio was fixed at 1% for etching. Also in this case, a vertically processed shape without notching was obtained as in FIG.

In this embodiment, the duty ratio of the pulse was fixed to 1% after just etching, but the same effect was obtained even if the duty ratio of the pulse was set to 1% before that.

Further, in the present embodiment, the duty ratio of the pulse during over-etching is fixed to 1%, but if this duty ratio is a value of 5% or less, the same effect is obtained. Furthermore, the method of this embodiment is effective not only in reducing notching in processing the gate polysilicon, but also in reducing charge-up damage in metal wiring etching.

(Example 4) Using the apparatus of Example 1, the polysilicon for gates was processed. In this embodiment, the pulse rising speed is fixed at 5 × 10 ³ V / μs and the repetition frequency is fixed at 500 KHz, and the pulse width is set to 1 from the etching start to the just etching timing as shown in the timing diagram of FIG. μs to 5
It was changed to 0 ns. In overetching after just etching, the etching was performed with the pulse width fixed at 50 ns. Also in this case, a vertically machined shape without notching was obtained as in FIG.

In this embodiment, the pulse width is fixed at 50 ns after just etching, but before that, the pulse width was 5 ns.
Similar effects were obtained even when the time was set to 0 ns.

In this embodiment, the pulse width is fixed to 50 ns after the over-etching and etching is performed. However, if the pulse width is 100 ns or less, the same effect can be obtained.

Furthermore, the method of this embodiment is effective not only in reducing notching in processing the gate polysilicon, but also in reducing charge-up damage in metal wiring etching.

(Example 5) Using the apparatus of Example 1, the polysilicon for gates was processed. In this embodiment, the pulse width is 50 ns and the pulse repetition frequency is 500 KH.
Each is fixed to z, and the rising speed of the pulse is 5 × 10 V / from the start of etching to the timing of just etching as shown in the timing diagram of FIG.
It was changed from μs to 5 × 10 ³ V / μs. In overetching after just etching, the rising speed was fixed at 5 × 10 ³ V / μs. Also in this case, a vertically machined shape without notching was obtained as in FIG.

In this embodiment, the pulse rising speed was fixed at 50 × 10 ³ V / μs after just etching, but before that, the pulse rising speed was 5 × 10 ³ V.
The same effect was obtained even if the value was set to / μs.

In this embodiment, after the over-etching, the pulse rising speed was fixed at 5 × 10 ³ V / μs and etching was performed.
The same effect can be obtained if it is 0 ³ V / μs or more.

Furthermore, the method of this embodiment is effective not only in reducing notching in processing the gate polysilicon, but also in reducing charge-up damage in metal wiring etching.

(Embodiment 6) As shown in FIG. 28, the gate polysilicon is processed using a plasma etching apparatus capable of applying a pulse voltage or a sine wave voltage as a bias. In this embodiment, it is 10 M until just etching is reached as in the timing diagram of FIG.
Etching is performed by applying a sinusoidal voltage of Hz, and the rising speed is 5 × 10 ³ V / μs in over etching.
Etching was performed by switching to a pulse voltage of 500 KHz with a pulse width of 50 ns. Also in this case, as in Example 1, a vertically processed shape without notching was obtained.

In this embodiment, the bias is switched from the sine wave to the pulse at the time of just etching, but the same effect can be obtained even if the bias is switched before just etching.

The method of this embodiment is effective not only in reducing notching in processing the gate polysilicon, but also in reducing charge-up damage in metal wiring etching.

(Embodiment 7) In the apparatus of Embodiment 1, the rising speed is 5 × 10 ³ V / μs, and the repetition frequency is 50.
A trench was etched by applying a pulse voltage of 0 KHz, a pulse width of 50 ns, and a magnitude of 100 V as a bias. FIG. 32 shows a cross section of the processed shape. For comparison, FIG. 33 shows a cross section of a processed shape when etching is performed using a normal RF bias. The bowing 15 and the sub-trench 16 observed when the RF bias was used disappeared by the application of the pulse bias of the present invention, and a vertical shape with a rounded bottom end was obtained. At the same time, the dependence of the etch rate on the pattern size, called microloading, disappeared.

In this embodiment, the processing of the trench has been described, but the same effect can be obtained in the processing of fine holes such as contact holes and the processing of fine grooves such as U grooves for isolation.

(Embodiment 8) Even if a noise waveform voltage or the like is superimposed on the pulse waveform voltage of this system, if the voltage is negligible with respect to the pulse, it is effective in reducing notching and charge-up. it is conceivable that.

Therefore, in this embodiment, the pulse generator shown in FIG. 21 generates a voltage having a waveform in which a sine wave is superimposed on a pulse as shown in FIG. 34 and applies it as a bias to etch the gate polysilicon. Also in this case, the first embodiment
Similar to the above, the effect was observed in notching suppression.

In the present embodiment, the sine wave voltage having a double cycle of the pulse is superimposed on the pulse voltage, but the same effect as that of the present embodiment can be obtained regardless of the cycle and the amplitude of the superimposed sine wave voltage.

Further, the method of this embodiment is effective not only in reducing notching in processing the gate polysilicon, but also in reducing charge-up damage in metal wiring etching and reducing bowing and sub-trench in processing fine holes such as trenches. Is.

(Embodiment 9) In the device of Embodiment 1, a pulse generator generates a voltage having a waveform in which a positive DC voltage is superposed on a pulse as shown in FIG. Etching was performed. Also in this case, as in Example 1, the effect of suppressing notching was observed. In this embodiment, the positive DC voltage is superimposed on the pulse, but the same effect as that of this embodiment can be obtained regardless of the magnitude and polarity of the superimposed DC voltage.

Further, the method of this embodiment is effective not only in reducing notching in processing the gate polysilicon, but also in reducing charge-up damage in metal wiring etching and reducing bowing and sub-trench in processing fine holes such as trenches. Is.

(Embodiment 10) Pb, which is a ferroelectric substance, is used as the material of the insulating ceramic 23 for electrostatic attraction of the device of Embodiment 1.
By using (Zr, Ti) O ₃ , the electrostatic capacity of the insulating ceramic 23 for electrostatic adsorption was increased to 3 nF / cm ² or more. By modifying this device, the rising speed and pulse width of the pulse required to eliminate the charge-up due to the electronic shading phenomenon can be reduced by two digits. Therefore, the performance required for the pulse power supply becomes smaller,
The cost of purchasing a pulse power supply can also be reduced.

Using the modified device, the polysilicon for the gate was processed. A pulse voltage having a magnitude of 100 V, a rising speed of 5 × 10 V / μs and a width of 5 μs was applied as a bias, and the processed shape was observed. As a result, as in Example 1, a vertically machined shape without notching was obtained.

In this embodiment, Pb (Zr, Ti) O ₃ is used as the insulating ceramic for electrostatic attraction, but the similar effect can be obtained when another ferroelectric substance is used. For example, (Pb, B
a) It is possible to reduce the rising speed and the pulse width, which are thresholds when Nb ₂ O ₆ is used, to 1/200 of those in the first embodiment. Moreover, in the case of using (Sr, Ba) Nb ₂ O ₆ , it is 5
To one- _third , one- _third for BaTiO ₃
In the case of PbTiO ₃ , it is 1/10 that of Bi ₄ Ti ₃ O ₁₂
In the case of, Pb (Mg, Nb) O ₃ -P
In the case of a solid solution of bTiO ₃ , it can be reduced to 1/2000, respectively.

[0055]

According to the present invention, the charge-up caused by the electron shading phenomenon is reduced, and as a result, the occurrence of notching, charge-up damage, bowing, sub-trench, etc. due to the electron shading is suppressed. It is also effective in reducing microloading.

[Brief description of drawings]

FIG. 1 is a diagram showing the relationship between the rising speed of an input pulse and the magnitude of notching.

FIG. 2 is a diagram showing a configuration of a conventional etching apparatus used for applying an RF bias.

FIG. 3 is a diagram showing a bias input voltage waveform when a conventional RF bias is applied.

FIG. 4 is a diagram showing a substrate bias waveform when a conventional RF bias is applied.

FIG. 5 is a diagram showing a local charge-up occurrence mechanism (electronic shading phenomenon).

FIG. 6 is a diagram showing a generation mechanism of a locally abnormal side-etched shape (notching) in processing a gate polysilicon.

FIG. 7 is a diagram showing a mechanism of causing damage to a gate insulating film in metal wiring processing.

FIG. 8 is a diagram showing a mechanism of generation of bowing and sub-trench in fine groove processing.

FIG. 9 is a diagram showing a configuration of a surface treatment apparatus used for applying a pulse bias according to the present invention.

FIG. 10 is a diagram showing a bias input voltage waveform in the case of applying a pulse bias according to the present invention.

FIG. 11 is a diagram showing a substrate bias waveform in the case of applying a pulse bias according to the present invention.

FIG. 12 is a diagram showing a local charge-up reduction mechanism according to the present invention.

FIG. 13 is a diagram showing the relationship between the rising speed of an input pulse and the magnitude of an electron acceleration voltage.

FIG. 14 is a diagram showing the relationship between the duty ratio of an input pulse (repetition frequency × pulse width) and the magnitude of an electron acceleration voltage.

FIG. 15 is a diagram showing a substrate bias waveform when the duty ratio of an input pulse is 0.1%.

FIG. 16 is a diagram showing a substrate bias waveform when the duty ratio of an input pulse is 1%.

FIG. 17 is a diagram showing a substrate bias waveform when the duty ratio of an input pulse is 10%.

FIG. 18 is a diagram showing a notching reduction mechanism according to the present invention.

FIG. 19 is a diagram showing a mechanism for reducing damage to a gate insulating film according to the present invention.

FIG. 20 is a diagram showing a sub-trench and bowing reduction mechanism according to the present invention.

FIG. 21 is a device configuration diagram when the present invention is applied to a microwave etching device.

FIG. 22 is a diagram showing an example of a pulse voltage waveform generated by a pulse power supply.

FIG. 23 is a diagram showing the relationship between the duty ratio of pulses and the magnitude of notching.

FIG. 24 is a view showing a processed shape of polysilicon for a gate according to the present invention.

FIG. 25 is a view showing a processed shape of polysilicon for a gate by a conventional method.

FIG. 26 is a diagram showing a relationship between a pulse duty ratio and a gate insulating film destruction rate.

FIG. 27 is a timing diagram showing changes in pulse repetition frequency during etching.

FIG. 28 is a timing diagram showing changes in pulse width during etching.

FIG. 29 is a timing diagram showing changes in the rising speed of a pulse during etching.

FIG. 30 is a microwave etching apparatus capable of switching between a pulse bias and an RF bias.

FIG. 31 is a diagram showing the timing of switching between pulse bias and RF bias.

FIG. 32 is a view showing a trench processing shape according to the present invention.

FIG. 33 is a view showing a trench processing shape by a conventional method.

FIG. 34 is a diagram showing an example of an input pulse voltage waveform of the present invention.

FIG. 35 is a diagram showing an example of an input pulse voltage waveform of the present invention.

[Explanation of symbols]

1 ... Etching sample, 2 ... Capacitor, 3 ... High frequency power supply, 4 ... Plasma, 5 ... Ion, 6 ... Electron, 7 ... Resist mask, 8 ... Polysilicon layer, 9 ... Silicon oxide film,
10 ... Notching, 11 ... Metal wiring, 12 Floating gate, 13 ... Substrate silicon, 14 ... Gate insulating film, 15 ... Boeing, 16 ... Sub trench, 17 ... Pulse power supply, 18 ... Magnetron, 19 ... Waveguide, 20 ...
Discharge tube, 21 ... Coil for magnetic field generation, 22 ... Ground electrode,
23 ... Insulating ceramics for electrostatic attraction, 24 ... Constant voltage power source for electrostatic attraction, 25 ... Arbitrary waveform generator, 26 ... High-speed broadband power amplifier.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Keizo Suzuki 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Kenichi Mizuishi 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Center

Claims (20)

[Claims] 1. A surface treatment method for treating an object to be processed by supplying plasma to the object to be treated placed in a decompression processing chamber and applying a bias voltage to the object to be treated, wherein the bias voltage rises. Speed 10 ³ V
/ Μs or more of the pulse waveform voltage is applied, the surface treatment method. 2. A dry etching method for processing an object to be processed by supplying plasma to the object to be processed placed in a decompression processing chamber and applying a bias voltage to the object to be processed, wherein the bias voltage rises. Speed 1
A dry etching method characterized by applying a voltage having a pulse waveform of 0 ³ V / μs or more. 3. The magnitude of the pulse waveform voltage according to claim 2 is 30.
A dry etching method characterized by being V or more. 4. The pulse duty ratio according to claim 3 is 5
% Or less, a dry etching method. 5. The pulse duty ratio according to claim 4 is 0.
A dry etching method characterized by being 5% or more. 6. The duty ratio of the pulse according to claim 4 is 0.
A dry etching method characterized by being 5% or less. 7. The pulse rising speed according to claim 1 is 5 ×
A surface treatment method, which is 10 ³ V / μs or more. 8. The pulse rising speed according to claim 2 is 5 ×
A dry etching method characterized by being 10 ³ V / μs or more. 9. The pulse width of claim 5 or 6 is 1
A dry etching method, which is 100 ns or less. 10. The dry etching method according to claim 5, wherein the object to be processed is a silicon oxide film. 11. A dry etching method, wherein a contact hole is processed by using the etching method according to claim 5. 12. The dry etching method according to claim 5, wherein the object to be processed is single crystal silicon. 13. A dry etching method, wherein a silicon trench is processed by using the etching method according to claim 5. 14. An etching method for processing an object to be processed by supplying plasma to the object to be processed placed in a decompression processing chamber and applying a bias voltage to the object to be processed, wherein a rising speed is used as the bias voltage. 10 ³
A dry etching method comprising applying a voltage having a waveform in which a sine waveform voltage is superimposed on a pulse waveform voltage of V / μs or more. 15. An etching method for processing an object to be processed by supplying plasma to the object to be processed placed in a decompression processing chamber and applying a bias voltage to the object to be processed, wherein a rising speed is used as the bias voltage. 10 ³
A dry etching method characterized by applying a voltage having a waveform in which a DC voltage is superimposed on a voltage having a pulse waveform of V / μs or more. 16. An etching method for processing an object to be processed by supplying plasma to the object to be processed placed in a decompression processing chamber and applying a bias voltage to the object to be processed, wherein the bias voltage is 10 ³ A dry etching method, characterized in that a voltage having a pulse waveform of V / μs or more is applied, and a rising speed of the pulse is changed during etching. 17. A surface treatment apparatus having means for supplying plasma to an object to be processed placed in a decompression processing chamber and means for applying a bias voltage to the object to be processed, as a part of the means for applying the bias. Rising speed 10 ³ V
A surface treatment apparatus comprising a power supply capable of generating a pulse voltage of / μs or more. 18. An etching apparatus having means for supplying plasma to an object to be processed placed in a decompression processing chamber and means for applying a bias voltage to the object to be processed, rising as part of the means for applying the bias. Speed 10 ³
A dry etching apparatus comprising a power supply capable of generating a pulse voltage of V / μs or more. 19. The surface treatment apparatus according to claim 17, further comprising an earth electrode having a surface area which is four times or more the surface area of the object to be treated in the processing chamber. 20. The etching apparatus according to claim 18,
A dry etching apparatus comprising a ground electrode having a surface area that is four times or more the surface area of the object to be processed in the processing chamber.