JPH0936013A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor manufacturing method adaptable to microminiaturization of quarter micron or less by etching a material film to be etched through an etching mask having a specific range of taper angle. SOLUTION: An oxide gate film 2 is formed on an Si substrate 1 and a polysilicon film 3 is formed on the oxide gate film 2, and afterwards W-poliside film 5 is formed by forming WSix film 4. Resist pattern 6 is formed by dry- etching the W-poliside film 5. The resist pattern 6 is slightly processed by plasma through an etching mask having a taper angle θ in a range of 86 deg.<=θ<=90 deg.. This method can be adapted to microminiaturization of quarter micron or less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for minimizing a dimension conversion difference between a pattern formed in a process including a plasma etching process and an etching mask.

[0002]

2. Description of the Related Art In recent years, in the field of manufacturing highly integrated semiconductor devices such as VLSI and ULSI, the submicron level design rule is already in the stage of mass production, and in the field of research, 0.25 μm, Fine processing at a level of 0.18 μm or less, which is a quarter micron or less, is under study. Plasma, which is an important technology for this fine processing,
In etching, the required level for various characteristics such as excellent shape controllability, practical etching rate, high underlayer selectivity, high mask selectivity, low contamination and low damage has risen remarkably. , Research from all sides is being conducted.

The processing of the gate electrode of a MOS transistor is
It is an exaggeration to say that the minimum processing dimension is applied to memory-based devices such as DRAM and SRAM and logic-based devices such as gate arrays, and the accuracy determines the degree of integration of these devices. In the processing of gate electrodes after quarter micron, it is considered that a method in which a chlorine (Cl) -based or bromine (Br) -based etching gas is used and an etching reaction product having a low vapor pressure is used for sidewall protection will become the mainstream. . Although the base film for processing the gate electrode is generally a gate insulating film made of SiOx, these Cl-based and Br-based etching gases are
It is also a gas that can achieve high selectivity with respect to the gate insulating film in principle.

By the way, a general material film forming a gate electrode of a silicon device is a polysilicon film, a refractory metal silicide film, a polycide film (a two-layer film in which a refractory metal silicide film is laminated on a polysilicon film). ), A polymetal film (a high melting point metal film is laminated on a polysilicon film 2
It is a silicon-based material film such as a layer film). Typical examples of refractory metals contained in refractory metal silicides and polycide films are:
It is tungsten (W).

When these silicon-based material films are etched using a Cl-based or Br-based gas, SixCl
Depositive reaction products such as y, SixBry, WClx, WBrx can be generated. However, in this case, since the vapor pressure of the generated tungsten halide compound is too low and the etching rate decreases, in recent years, Cl ₂
A method of removing W by using a mixed gas system such as / O ₂ or HBr / O ₂ to generate tungsten oxyhalide (WClxOy or WBrxOy) having a higher vapor pressure is used. In addition, silicon oxyhalide (SiOxCly or SiOxBry) which is a deposition reaction product at this time is oxidized in the etching reaction system,
Finally, it contributes to sidewall protection in the form of SiOx.

The deposition reaction product generated in the etching reaction system is deposited on the surface of the object to be etched. At this time, since the deposited reaction products are immediately sputtered off on the horizontal surface where the ions are incident from the plasma, the reaction products can adjust the etching rate and have selectivity for the underlying material film and the etching mask. Play a role in improving. On the other hand, a reaction product is likely to deposit on a vertical surface or a surface nearly vertical to which ions are hard to enter, forming a sidewall protective film. This side wall protective film blocks lateral attack by not only ions but also radicals and contributes to shape control of the etching pattern. In plasma etching in recent years, an anisotropic shape is achieved with the ion incident energy as low as possible by positively utilizing the side wall protection effect.

[0007]

By the way, the above-mentioned deposition reaction product exhibiting the side wall protection effect is deposited not only on the side wall surface of the pattern formed by etching but also on the side wall surface of the etching mask. The problem here is the thickness of the side wall protective film. That is, the thickness of the side wall protective film changes the apparent pattern width of the etching mask, which causes the line width of the pattern formed by etching to vary.

Moreover, the thickness of the side wall protective film depends on the taper angle of the etching mask. Here, the definition of the taper angle in the present specification will be described with reference to FIG. The taper angle θ described in this specification refers to the angle obtained by measuring the inclination of the side wall surface of the mask with respect to the horizontal plane of the object to be etched inside the mask. If θ <90 °, the forward taper shown in (a) is obtained, and if θ> 90 °, the reverse taper shown in (b) is obtained. Also, in recent years,
In chemically amplified resists used for laser lithography, a mask with a skirt may be formed at the interface with the object to be etched due to the dissipation of the acid catalyst generated by exposure. Ignore the hem part,
It is defined by the inclination of the main side wall surface of the mask. (C)
The figure shows a forward tapered mask with a hem, and the figure (d) shows an inverse tapered mask with a hem. Furthermore, (e)
As shown in the figure, there may be a mask shape in which a forward taper and an inverse taper are mixed, but even in such a case, the inclination is defined as the inclination of the main side wall surface of the mask.

Next, how the line width of the pattern formed by etching changes according to the taper angle θ of the mask will be described with reference to FIG. Here, the W-polycide film 5 laminated on the Si substrate 1 with the gate oxide film 2 interposed therebetween, with the resist pattern 6 interposed therebetween,
Also, consider the case of etching using a Cl ₂ / O ₂ mixed gas. The W-polycide film 5 is formed by laminating an n ⁺ type polysilicon film 3 and a tungsten silicide (WSix) film 4 in this order from the lower layer side. Further, in FIG. 2, the subscript a attached to the reference numeral has an anisotropic shape.
(anisotropic), and the subscript t represents having a tapered shape (tapered).

First, as shown in FIG. 3A, when a forward tapered resist pattern 6 having a mask width dm is formed, a certain amount of ions are also present on the side wall surface of the resist pattern 6. Incident. Therefore, the sidewall protection effect of the depositable reaction product on the sidewall surface is not so large, and particularly, the hem portion of the resist pattern 6 is
It disappears on the way due to the sputtering action. Therefore, as shown in FIG. 6B, the pattern width dp of the finally obtained gate electrode 5a becomes smaller than the original mask width dm. Here, if the difference between the obtained pattern width dp and the initial mask width dm is defined as the dimension conversion difference ΔCD, a negative dimension conversion difference ΔCD (= dp-dm <0 in etching using a forward tapered resist pattern). ) Has occurred. Whether or not this skirt disappears as the etching progresses also depends on the space width ds. Generally, in a system in which a sedimentary reaction product is generated, the smaller the space width ds is, the smaller the absolute amount of the generated product is, and the side wall protection effect is hard to work, so that the hem is easily lost. Therefore, the negative dimension conversion difference ΔCD is likely to be large. On the other hand, as shown in FIG. 7C, when the inverse tapered resist pattern 6 having the mask width dm is formed, the deposition reaction product is first formed on the side wall surface of the mask width resist pattern 6. 7 begins to deposit. Since the incidence of ions on the side surface of the reverse taper is extremely small, this deposition is likely to occur isotropically and excessively. As a result, the pattern width dp of the gate electrode 5t becomes larger than the original mask width dm. That is, the positive dimension conversion difference ΔCD (= dp-d
m> 0) occurs.

Although the case where the resist pattern 6 has a skirt has been discussed above, this discussion can be extended to the case where the hem has no skirt. That is, for the forward tapered resist pattern, the dimension conversion difference ΔCD in FIG. (B) approaches zero, but for the reverse tapered resist pattern, the pattern width dp basically remains the same.

The above discussion was made on the assumption that a resist pattern is used, that is, the etching mask itself causes film reduction due to the ion sputtering action. However, an inorganic material film that hardly causes film reduction. Even when the pattern is used as a mask, if it has a reverse taper shape, the pattern width dp also becomes thick.

The above-mentioned dimension conversion difference ΔCD has a width of 0.35 μ
It has been experimentally confirmed that even in the formation of m line and space patterns, the order of ± 100 nm is reached. However, the technology roadmap compiled by the American Semiconductor Industry Association (SIA) until the year 2010 "The National Technology Roadmap for Semiconductors (The National Technolo
gy Roadmap for Semiconductors) ”, revised in 1994, the dimensional conversion difference allowed for a gate electrode having a line width of 0.18 μm is about 10%, which is only 18 nm. Therefore, in the process in which the dimensional conversion difference of ± 100 nm easily occurs as described above, fine processing after quarter micron becomes extremely impossible.

Therefore, the present invention provides a method of manufacturing a semiconductor device including a high-precision plasma etching process that can be applied to fine processing of quarter micron or later by minimizing the above-mentioned dimension conversion difference ΔCD. The purpose is to do.

[0015]

A method of manufacturing a semiconductor device of the present invention is proposed to achieve the above-mentioned object, and a deposition reaction product is generated along with the etching of the material film to be etched. When the plasma etching process is performed, the taper angle θ is 86 ° ≦ θ ≦
Through an etching mask in the 90 ° range.
That is, a forward tapered or vertical etching mask is used. The range of the taper angle θ is defined in this way in order to achieve a good balance between the isotropic deposition process of the depositable reaction product and the anisotropic sputter removal process. It is possible to minimize the size conversion difference between the etching mask and the etching mask. A more preferable range of the taper angle θ is 87 ° ≦ θ ≦ 8
It is 9 °.

Further, as the etching mask,
An etching mask having a constant taper angle θ in the vicinity of the interface with the material film to be etched, that is, an etching mask having no hem is suitable for suppressing the dimensional conversion difference. It is even better if the etching mask does not partially have an inverse taper portion, that is, an etching mask that does not have a constriction in cross section.

As the etching mask, any of an organic material film pattern, an inorganic material film pattern, or a conductive material film pattern may be used. Since the organic material film pattern is directly patterned by a lithography technique using exposure light or an electron beam, the taper angle θ depends on the type of resist material, the exposure amount, the pattern density, and the development conditions.

On the other hand, since the inorganic material pattern and the conductive material film pattern are indirectly patterned by plasma etching using another etching mask (typically a resist pattern), the taper angle θ is Determined by etching conditions. That is, this plasma
It is determined based on the amount of depositable products generated during etching or the amount of recession of other etching masks.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention employs a forward taper mask having a taper angle .theta. It is intended to control the etching shape of the material film to be etched by adjusting the balance between deposition and removal of the material. First, regarding the polycide gate electrode processing using a resist pattern, it was experimentally investigated how the correlation between the occurrence state of the dimension conversion difference ΔCD and the space width ds changes depending on the taper angle θ of the resist pattern. investigated.

The sample wafer used is as shown in FIG.
(A) of FIG. Here, the gate oxide film 2 on the Si substrate 1 having a diameter of 5 inches is formed to have a thickness of 10 nm by pyrogenic oxidation at 850 ° C. Further, W- polycide film 5, after forming the n ⁺ -type polysilicon film 3 having a thickness of about 100μm by a low pressure CVD method using SiH ₄ as a raw material gas, WF ₆ / SiC
It was formed by laminating a WSix film 4 having a thickness of about 100 μm by a low pressure CVD method using a mixed gas of l ₂ H ₂ as a source gas.

The resist pattern 6 was formed with a chemically amplified positive type photoresist to a pattern width dm of 0.35 μm through KrF excimer laser lithography and development processing. However, this pattern width d
About m? % Is occupied by the foot. The taper angle θ of the resist pattern 6 was changed in the range of 86 ° to 94 °, and this change was achieved by controlling the exposure amount and the developing conditions.

In the dry etching, a magnetic field microwave plasma etching apparatus is used and the following conditions are given as an example: Cl ₂ flow rate 75 SCCM O ₂ flow rate 5 SCCM pressure 0.5 Pa microwave power 850 W (2.45 GHz) ) RF bias power 70 W (2 MHz) Wafer temperature 20 ° C.

FIG. 3 shows the results. In this figure, the horizontal axis represents the space width ds (μm), and the vertical axis represents the dimension conversion difference ΔCD (nm).
The black plots represent the taper angle θ ≧ 90 ° (vertical or inverse tapered), and the white plots represent the taper angle θ <90 ° (forward tapered).

Looking at this figure, in the case of the inverse taper shape,
It can be seen that a positive dimensional conversion difference ΔCD occurs even when the space width ds is small and the amount of sedimentary reaction products is essentially small. In the region (b) surrounded by the solid line in the figure, the tendency that the obtained pattern width becomes thick is particularly remarkable due to the large space width ds.

On the other hand, in the case of the forward taper shape, a negative dimensional conversion difference ΔCD occurs due to the narrow space width ds in the area (a) surrounded by the solid line, but the deposition reaction reaction is generated. In the region of the wide space width ds where the objects tend to be excessive, the dimensional conversion difference ΔCD is not so large.

When the taper angle θ = 90 °, an intermediate tendency between the two appears, and the variation in the dimension conversion difference ΔCD is the largest in both positive and negative. It is considered that this is because the influence of the etching conditions is sensitively reflected, such as the film reduction due to the ion-sputtering action that may occur even in the resist pattern having an anisotropic shape.

The above is the tendency for the rough dimension conversion difference ΔCD to occur. More specifically, the taper angle θ = 88.
The most excellent effect of suppressing the dimensional conversion difference ΔCD appears in the case of °. In particular, the accumulation of sedimentary reaction products is the highest,
Space width ds that can be regarded as an isolated pattern in the integrated circuit
= 6 μm, the dimension conversion difference ΔCD is 20 to
It is worth noting that it is suppressed to the range of 30 nm. That is, at this angle, it means that the deposition reaction product deposited on the side wall surface of the mask and the removal thereof by ion incidence are in the best balance. When the taper angle θ = 90 °, the dimensional conversion difference ΔCD varies greatly as described above, and when the taper angle θ = 86 °, the space width ds.
Considering that the negative dimensional conversion difference ΔCD becomes large when N is narrow, the most preferable range of the taper angle θ is 87 ° ≦
It can be determined that θ ≦ 89 °.

However, if the resist pattern 6 does not have a hem, the negative dimension conversion difference ΔCD tends to be eliminated as a whole, so that the taper angle θ falls within the range of 86 ° ≦ θ ≦ 90 °. For example, it is possible to control the shape to some extent. This is the basis for the regulation regarding the range of the taper angle θ in the present invention.

It is considered that the dimension conversion difference ΔCD is naturally proportional to the film thickness of the material film to be etched within the range of certain conditions. The data shown in FIG. 3 was obtained for a W-polycide film having a film thickness of 200 nm. However, the W-polycide film used for future generation gate electrodes is much thinner than this, for example, 64M DRAM.
Is about 100 μm (polysilicon film 50 μm + WSix film 50 μm). That is, the above-mentioned data was obtained under conditions severer than those of future mass-production processes, and there is no problem in processing a thinner W-polycide film based on this data.

Further, although a positive photoresist material was used in the above examination, this is a natural choice in view of the resolution and development characteristics of ordinary photoresists. However, even in the case of a negative photoresist, which is generally easy to exhibit an inverse taper shape (taper angle θ> 90 °), it is possible to achieve the taper angle θ = 90 ° by optimizing the exposure and development conditions. .

The following examples are based on the above results and describe individual cases with different etching masks.

[0032]

EXAMPLE 1 In this example, an example in which the present invention is applied to processing a polycide gate electrode of a MOS transistor will be described with reference to FIGS. 4 and 5.

The sample wafer used in this embodiment is shown in FIG.
Shown in The method for producing this wafer is almost the same as that described in FIG. 2, but the thickness of the W-polycide film 5 is about 10
It was set to 0 nm. In addition, the resist pattern 6 of this embodiment
Has no hem. The resist pattern 6 is
Even if a chemically amplified positive photoresist material is used, it can be formed by optimizing the exposure / development conditions. Here, a light oxygen plasma treatment is applied to the resist pattern 6 having the hem as described above. The hem was removed by performing (discum treatment). Taper angle θ is 8
8 ゜. The space width ds was 6.0 μm.

In this state, the W-polycide film 5 was dry-etched under the etching conditions described in the description of FIG. In this step, some ions were incident on the side wall surface of the resist pattern 6, while SiClxOy was mainly generated as a deposition reaction product. However, due to the balance between the ion incidence and the deposition process, Both recession and excessive deposition were effectively suppressed. As a result, the gate electrode 5a having an anisotropic shape can be formed as shown in FIG.
It could be suppressed to within 0 nm.

Embodiment 2 In this embodiment, an example in which an offset SiOx film is used as an etching mask in processing a polycide gate electrode of a MOS transistor will be described with reference to FIGS. 6 to 8. In these figures, the same reference numerals are used in part as in FIGS. 4 and 5 described above.

In the etching sample used in this embodiment, as shown in FIG. 6, an offset SiOx film 8 having a thickness of about 80 nm is further formed on the W-polycide film 5, and the taper angle is further formed thereon. θ = 90 °, that is, the resist pattern 9 having an anisotropic shape is formed. The offset SiOx film 8 is a film used in a so-called self-aligned contact process, and plays a role of ensuring insulation between the wiring pattern immediately below and the pattern on the upper layer side. This wafer is set in a magnetron RIE apparatus, and the above-mentioned offset SiOx film 8 is first used as an example under the following conditions: CHF ₃ flow rate 40 SCCM CO flow rate 200 SCCM pressure 1.0 Pa RF power 1000 W (13.56 MHz) wafer temperature 0 Dry etching was performed at ℃.

Dry etching of a SiOx film is usually performed.
Since the condition of high ion incident energy is adopted to break the Si—O bond having a large interatomic bond energy, the resist pattern 9 is sputtered by the ions in the plasma and its angle is lowered, and the taper and the film decrease gradually. Cause On the other hand, a fluorocarbon polymer is generated due to the decomposition of the etching gas, and this is deposited on the sidewall surface of the resist pattern 9. Due to the competition between the film reduction and the deposition, an offset SiOx film pattern 8t having a taper angle θ = 88 ° was formed as shown in FIG.

Then, the resist pattern 9 is removed by ashing, and the offset SiOx film pattern 8 is formed.
The W-polycide film 5 was etched using t as a mask by using a magnetic field microwave plasma etching apparatus. The etching conditions at this time are as described above in the description relating to FIG. As a result, the gate electrode 5a having an anisotropic shape could be formed as shown in FIG.

Embodiment 3 In this embodiment, in processing the gate electrode of EPROM,
The floating gate electrode was processed by using the polycide control gate electrode formed through the resist pattern as a mask together with the resist pattern. The process of this embodiment will be described with reference to FIGS. 9 to 11. In these figures, the same reference numerals are used in part as in FIGS. 4 and 5 described above.

The etching samples used in this example, as shown in FIG. 9, on the gate oxide film 2 formed by the pyrogenic oxidation of the Si substrate 1, a thickness of about 50 nm n ⁺ -type poly A silicon film 10 is formed, a W-polycide film 14 is formed on the silicon film 10 via an ONO film 11, and a resist pattern 15 is further formed thereon. Here, although detailed illustration is omitted, the ONO film 11 is made of Si having a thickness of 4 nm in order from the lower layer side.
Ox film, 6 nm thick SixNy film, 2 nm thick Si
It is a stack of Ox films. The W-polycide film 14 is composed of an n ⁺ -type polysilicon film 12 having a thickness of about 50 nm and a WSix film 13 having a thickness of about 50 nm in this order from the lower layer side.
And are laminated. Resist pattern 1 above
The taper angle θ of No. 5 was 86 °.

This wafer is loaded with a magnetic field microwave plasma
It is set in an etching apparatus and, as an example, the following conditions: Cl ₂ flow rate 75 SCCM O ₂ flow rate 5 SCCM pressure 0.5 Pa microwave power 850 W (2.45 GHz) RF bias power 80 W (2 MHz) wafer temperature 20 The W-polycide film 14 was dry-etched at ℃.

In this case, since the taper angle θ of the resist pattern 15 is set smaller than that of the first embodiment, the retreat of the mask progresses, and the control gate 14t having the taper angle θ = 88 ° is formed. Subsequently, the wafer is transferred to a magnetron RIE apparatus, and the above-mentioned offset Si
The ONO film 11 was etched under the same conditions as the etching of the Ox film.

Further, the wafer was returned to the magnetic field microwave plasma etching apparatus, and as an example, the following conditions HBr flow rate 120 SCCM O ₂ flow rate 2 SCCM pressure 0.6 Pa microwave power 850 W (2.45 GHz) RF bias The power of 60 W (2 MHz) and the wafer temperature of 20 ° C. were used to dry-etch the n ⁺ type polysilicon film 10.

In this etching, both the control gate electrode 14t and the resist pattern 15 function as an etching mask, and SiBrxOy is generated as a deposition reaction product. However, etching
Since each of the masks had a forward taper shape, excessive deposition was not caused to increase the apparent mask width. As a result, as shown in FIG. 11, the floating gate electrode 10a having an anisotropic shape can be formed, and the dimensional conversion difference ΔCD can be suppressed within 10 nm.

Although three examples have been described above, the present invention is not limited to these examples. That is,
The structure of the sample wafer, the method of forming the film forming the wafer, the dimensions of each part, the dry etching apparatus used, and the dry etching conditions can be appropriately changed and selected. In particular, regarding the etching gas for the silicon-based material film, it is possible to use iodine (I) -based gas instead of the above Cl-based or Br-based gas. In the second embodiment, the offset SiOx film 8 is replaced by a SixNy film or a Si film.
An OxNy film may be adopted.

[0046]

As is apparent from the above description, according to the present invention, the dimensional conversion difference ΔCD from the etching mask is increased.
It is possible to provide a method for manufacturing a semiconductor device, which enables dry etching with a minimum of the above, and which can very well cope with fine processing of quarter micron or later. Therefore, the present invention greatly contributes to miniaturization, high integration, and high performance of semiconductor devices.

[Brief description of drawings]

FIG. 1 is a schematic diagram for explaining the definition of a taper angle of an etching mask.

FIG. 2 is a schematic cross-sectional view comparing generation of a dimension conversion difference ΔCD in processing a polycide gate electrode for each shape of a resist pattern, and (a) before etching when a forward tapered resist pattern is used. State, (b)
Indicates that a negative dimension conversion difference has occurred after etching,
(C) shows a state before etching when an inverse tapered resist pattern is used, and (d) shows a state where a positive dimensional conversion difference occurs after etching.

FIG. 3 is a graph showing a space width ds dependency of a dimension conversion difference ΔCD in processing a polycide gate electrode.

FIG. 4 is a diagram showing a process example in which a polycide / gate electrode of a MOS transistor is processed by applying the present invention.
It is a typical sectional view showing the state where resist patterning was performed on the polycide film and silicon.

FIG. 5 shows W-using the resist pattern of FIG. 4 as a mask.
FIG. 3 is a schematic cross-sectional view showing a state in which a polycide film is anisotropically etched.

FIG. 6 shows another process example in which the present invention is applied to process a polycide gate electrode of a MOS transistor,
It is a typical sectional view showing the state where resist patterning was performed on the offset SiOx film.

7 is a schematic cross-sectional view showing a state where the offset SiOx film is etched in a forward tapered shape by using the resist pattern of FIG. 6 as a mask and the resist pattern is removed.

8 is a schematic cross-sectional view showing a state in which the W-polycide film is anisotropically etched using the offset SiOx film pattern of FIG. 7 as a mask.

FIG. 9 is a schematic cross-sectional view showing a state where resist patterning is performed on a W-polycide film in a process example of processing a gate electrode of a nonvolatile memory to which the present invention is applied.

FIG. 10 is a graph showing W using the resist pattern of FIG. 9 as a mask.
-A schematic cross-sectional view showing a state in which a control gate electrode is formed by anisotropically etching a polysilicon film.

FIG. 11 is a schematic cross-sectional view showing a state where a floating gate electrode is formed by anisotropically etching a polysilicon film using the control gate electrode of FIG. 10 together with a resist pattern as a mask.

[Explanation of symbols]

5,14 W-polycide film 5a (having an anisotropic shape) gate electrode 6,9,15 resist pattern 7 deposition reaction product 8t (tapered) offset SiOx film pattern 10 n ⁺ type polysilicon film 10a floating・ Gate electrode 14t Control gate electrode

Claims (13)

[Claims] 1. A method for manufacturing a semiconductor device including a plasma etching step in which a depositable reaction product is generated along with etching of a material film to be etched, wherein the etching has a taper angle θ of 86 ° ≦ θ ≦ 90 °. A method of manufacturing a semiconductor device through an etching mask in the range of. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the taper angle θ is set within a range of 87 ° ≦ θ ≦ 89 °. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the etching mask has a constant taper angle θ at least in the vicinity of the interface with the material film to be etched. 4. The silicon-based material film is etched in the plasma etching step using an etching gas that generates at least one of chlorine-based chemical species, bromine-based chemical species, and iodine-based chemical species. Of manufacturing a semiconductor device of. 5. The method of manufacturing a semiconductor device according to claim 1, wherein an organic material film pattern is used as the etching mask. 6. The method of manufacturing a semiconductor device according to claim 1, wherein an inorganic material film pattern is used as the etching mask. 7. The inorganic material film pattern is formed by plasma etching through another etching mask, and the taper angle θ of the inorganic material film pattern is the plasma etching rate.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the method is controlled on the basis of the amount of depositable deposits generated during etching. 8. The inorganic material film pattern is composed of at least one of a silicon oxide based material, a silicon nitride based material, and a silicon oxynitride based material, and the depositable product is a carbon based polymer. Manufacturing method of semiconductor device. 9. The inorganic material film pattern is formed by plasma etching through another etching mask, and a taper angle θ of the inorganic material film pattern is controlled based on a receding amount of the other etching mask. Claim 6
The manufacturing method of the semiconductor device described in the above. 10. The method of manufacturing a semiconductor device according to claim 1, wherein at least a conductive material film pattern is used as the etching mask. 11. The conductive material film pattern is formed by plasma etching through another etching mask, and the taper angle θ of the conductive material film pattern is a deposition reaction product generated during the plasma etching. The method of manufacturing a semiconductor device according to claim 10, wherein the method is controlled based on the amount of deposition. 12. The method of manufacturing a semiconductor device according to claim 11, wherein the conductive material film pattern is composed of a silicon-based material film. 13. The conductive material film pattern is formed by plasma etching through another etching mask, and the taper angle θ of the conductive material film pattern is controlled based on the receding amount of the other etching mask. The method for manufacturing a semiconductor device according to claim 10,