JP2004165675A - Method for producing semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent size valuation due to difference in a mask pattern layout when a linear pattern of a gate electrode/wiring or metal-wiring of a MOS transistor. <P>SOLUTION: In a method for producing a semiconductor integrated circuit device, when a plurality of semiconductor integrated circuit devices, in which a circuit pattern having a linear pattern is provided and at least a part of production process is common, is produced, dry etching is performed to a film for processing with controlling dry etching conditions depending on circumferential length per unit area of the linear pattern in each of the semiconductor integrated circuit devices. <P>COPYRIGHT: (C)2004,JPO

Description

  The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a gate electrode and wiring of a MOS transistor in a system LSI in which an element group having a fine repetitive pattern such as a DRAM (Dynamic Random Access Memory) can be mixedly mounted. Also, the present invention relates to a technique for forming a linear pattern such as a metal wiring.

  2. Description of the Related Art In recent years, for example, as a semiconductor integrated circuit device in which a DRAM is embedded, a system LSI having a mounted DRAM capacity exceeding 20 megabits is being mass-produced.

  Also, the mounting rate of a memory circuit such as a DRAM, an SRAM (Static Random Access Memory) or a ROM (Read Only Memory) on one semiconductor chip (the ratio of the area of the memory circuit to the area of the entire chip: hereinafter, the occupied area ratio) In the manufacturing process of a semiconductor integrated circuit device such as a system LSI that differs depending on the application or specification, not only the unit circuits are simply arranged repeatedly but also a mask pattern having various layouts. Processing is required.

  Conventionally, the shape or dimension of a pattern (hereinafter referred to as a processing pattern) obtained by etching a film to be processed using a mask pattern varies depending on the mask pattern layout, that is, the arrangement of element patterns. The phenomenon of doing is known.

  As an example, there is a pattern proximity effect generated when a resist pattern is formed in a photolithography process. This means that even if the pattern has the same design shape and design dimensions, how close the pattern and other patterns adjacent to it are, or what shape other adjacent patterns take This is a phenomenon in which the processed shape or processed size of the pattern differs depending on whether the pattern is used.

  Another example is a loading effect or a micro-loading effect in a dry etching process. The loading effect is a phenomenon in which the etching rate changes depending on the size of the entire area to be etched on the semiconductor chip, which may slightly affect the pattern size. The microloading effect is a phenomenon in which, when a pattern laid out in the same semiconductor chip has unevenness in arrangement depending on the location, the etching rate is locally different depending on the unevenness. That is, even if the patterns are exactly the same, the etching rate is different between a portion where the patterns are sparsely arranged and a portion where the patterns are densely arranged, and this also has an indirect effect on variations in pattern dimensions.

  Conventionally, with respect to the above-described problem of variation in pattern size depending on the mask pattern layout, the pattern size is limited only in a mask portion where the pattern size is considered to significantly vary depending on the mask pattern layout due to the proximity effect or the loading effect. Design rules were added to compensate for dimensional variations.

  Further, in the manufacture of a system LSI in which a DRAM can be mixed, the same processing method or processing condition is used regardless of the presence or absence of the DRAM or the DRAM occupation area ratio (the ratio of the area of the DRAM to the area of the entire chip). Was.

  However, with the progress of miniaturization of LSI, specifically, with the progress of miniaturization of integrated circuit pattern dimensions of 0.25 μm or less, particularly 0.15 μm or less, higher precision dimensional control is required. As a result, the dimensional variation caused by the difference in the mask pattern layout cannot be ignored.

  FIG. 8 shows a semiconductor integrated circuit device on which a 24-megabit DRAM is mounted (hereinafter, referred to as a DRAM mounted type) and a semiconductor integrated circuit device on which a DRAM is not mounted (hereinafter, referred to as a non-DRAM mounted type). FIG. 9 shows a frequency distribution of CD (critical dimension) loss, which is a difference between the dimension of a resist pattern before etching and the dimension of a completed gate electrode when a gate electrode is formed by dry etching using a resist pattern as a mask in manufacturing. . Note that the results shown in FIG. 8 are obtained by employing the same gate electrode processing process in the manufacture of the DRAM-mounted product and the non-DRAM-mounted product. The method of calculating the CD loss is (dimension of resist pattern before etching)-(dimension of completed gate electrode).

  As shown in FIG. 8, although the same gate electrode processing process is used for each product, the pattern dimension has a dependency on the mask pattern layout.

  That is, in the conventional method of manufacturing a semiconductor integrated circuit device, even if the same gate electrode processing process is employed, gate electrode dimensions vary due to differences in mask pattern layout due to differences in product types. In other words, the gate electrode dimensions are dependent on the type. As a result, in a specific type of semiconductor integrated circuit device manufactured using a specific mask, there is a problem that the characteristics of the MOS transistor deviate from the design specifications and the operation margin is narrowed. Such a problem cannot be ignored especially when the design rule is 0.18 μm or less.

  In view of the above, an object of the present invention is to prevent a dimensional variation due to a difference in a mask pattern layout when a linear pattern such as a gate electrode / wiring or a metal wiring of a MOS transistor is formed. And

  In order to achieve the above object, the present inventors have studied the causes of dimensional variations due to differences in mask pattern layout.

  As a result, in a semiconductor integrated circuit device in which a logic circuit composed of a CMOS (Complementaly Metal-Oxide Semiconductor) is mounted and a memory circuit such as a DRAM in which gate electrodes and wirings are densely arranged is mounted. It has been found that the pattern size varies depending on the occupied area ratio of the circuit.

  In addition, it has been found that the phenomenon that the dimensional variation occurs due to the difference in the mask pattern layout is different from the above-described loading effect that occurs depending on the size of the area to be etched, that is, the size of the pattern area. Further, as is apparent from FIG. 8, this phenomenon differs from the microloading effect that occurs depending on the local density of the pattern inside the chip, and is a phenomenon of a novel property that the pattern dimension fluctuates over the entire chip. I found that there was.

By the way, as described above, the kind dependence on the processing dimensions such as the gate electrode dimensions occurs due to the CD loss. On the other hand, in the current dry etching process, in order to prevent side etching and achieve anisotropic dry etching, an etching gas having a sidewall protection effect (hereinafter, referred to as a deposition gas) is used or has a sidewall protection effect. An etching reaction product is formed. For example, when dry etching is performed on a polysilicon film to form a gate electrode, a chlorine-containing gas is used as an etching gas and an HBr gas is often used as a deposition gas. This forms a low-volatility sidewall protection film made of SiBr ₄ which is a reaction product of HBr and polysilicon on the sidewall of the polysilicon film. When dry etching is performed on an aluminum film to form an aluminum wiring, recently, CHF ₃ gas is often used as a deposition gas. Here, the CHF ₃ gas, which is a fluorine-containing gas, is a deposition gas added for forming the sidewall protective film, but does not contribute to the etching of the aluminum film.

  If the same gate electrode processing process is used irrespective of the mask pattern layout and the processed shape of the film to be etched is controlled by the side wall protection effect, the unit area increases as the area of the side wall of the film to be protected increases. The present inventors have found that the side wall protection effect per area decreases, thereby increasing CD loss.

  FIG. 9 shows the relationship between the peripheral edge length of the gate electrode (the length of the peripheral portion of the gate electrode) per unit area and the DRAM occupation area ratio in the products having various DRAM occupation area ratios including the products without DRAM. I have. In the graph of FIG. 9, the “perimeter of the gate electrode per unit area” on the vertical axis is a value obtained by dividing the total perimeter of the gate electrode on a predetermined circuit region by the area of the predetermined circuit region. means. Here, the predetermined circuit area may be the entire chip.

  As shown in FIG. 9, the peripheral edge length of the gate electrode per unit area increases as the area occupied by the DRAM increases.

  FIG. 10 shows the relationship between the gate electrode peripheral length per unit area and the CD loss in various types.

  As shown in FIG. 10, when the peripheral edge length of the gate electrode per unit area increases, the gate electrode dimension decreases (the CD loss becomes positive), while when the peripheral length of the gate electrode per unit area decreases, the gate electrode dimension increases ( CD loss becomes negative). This is because, as the peripheral edge length of the gate electrode per unit area increases, the area of the side wall to be protected increases, whereby the effect of protecting the side wall per unit area decreases.

  The inventors of the present application focused on the fact that the CD loss monotonously changes from a negative value to a positive value as the peripheral length of the gate electrode per unit area increases (see FIG. 10), and Regardless of the difference in the mask pattern layout, the gate electrode peripheral length per unit area is set within a predetermined range, or the process conditions are adjusted according to the difference in the gate electrode peripheral length per unit area for each type. Has been found to prevent a situation in which dimensional variation is caused by the above.

  More specifically, the first method for manufacturing a semiconductor integrated circuit device according to the present invention includes the step of manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a linear pattern and having at least a part of the manufacturing process common. Assuming a method of manufacturing a semiconductor integrated circuit device, a process of manufacturing each semiconductor integrated circuit device is performed on a film to be processed while adjusting a dry etching condition according to a peripheral length per unit area of a linear pattern. The method includes a step of performing dry etching.

  According to the first method for manufacturing a semiconductor integrated circuit device, dry etching is performed on a film to be processed while adjusting dry etching conditions in accordance with the peripheral length per unit area of the linear pattern. Even when the mask pattern layout greatly differs depending on the type, the dimension of the line pattern can always be equal to a predetermined value. Therefore, even in a system LSI in which the mounting ratio of a DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode or the metal wiring can be made constant irrespective of the mask pattern layout. The device can be realized.

  In the first method for manufacturing a semiconductor integrated circuit device, the step of adjusting the dry etching condition includes the step of setting one dry etching condition when the peripheral edge length per unit area of the linear pattern is within one range. It is preferred to include.

  This makes it possible to easily adjust the dry etching conditions.

  According to a second method of manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor integrated circuit for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a linear pattern and having at least a part of a manufacturing process common. Assuming a circuit device manufacturing method, a manufacturing process of each semiconductor integrated circuit device forms a resist pattern corresponding to a linear pattern while adjusting its dimension according to the peripheral length per unit area of the linear pattern. Process.

  According to the second method for manufacturing a semiconductor integrated circuit device, the resist pattern corresponding to the linear pattern is formed while adjusting its dimension according to the peripheral length per unit area of the linear pattern. Even when the mask pattern layout greatly differs depending on the type, the dimension of the line pattern can always be equal to a predetermined value. Therefore, even in a system LSI in which the mounting ratio of a DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode or the metal wiring can be made constant irrespective of the mask pattern layout. The device can be realized.

  A third method of manufacturing a semiconductor integrated circuit device according to the present invention includes a semiconductor integrated circuit for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a linear pattern and having at least a part of a manufacturing process common. Assuming a method of manufacturing a circuit device, the manufacturing process of each semiconductor integrated circuit device includes a first step of forming a resist pattern corresponding to a linear pattern on a film to be processed, and a step of forming a film to be processed using the resist pattern as a mask. And a second step of performing dry etching on the substrate, wherein the second step uses an etching gas having a side wall protection effect of protecting a side wall formed on the film to be processed by the etching, or has a side wall protection effect. Including a step of forming an etching reaction product having, a processing method in at least one of the first step and the second step, or The physical condition, the area of the element groups and having a repeating pattern is included in the circuit pattern, adjusted in accordance with the ratio to the area of the arrangement region of the circuit pattern.

  According to the third method for manufacturing a semiconductor integrated circuit device, the first step of forming a resist pattern corresponding to the linear pattern or the second step of performing dry etching on a film to be processed using the resist pattern as a mask In the process, the processing method or the processing condition is changed according to the ratio of the area of the element group having the repetitive pattern to the area of the arrangement region of the circuit pattern (hereinafter, referred to as an element group occupied area ratio). For this reason, even when the area of the side wall formed on the film to be processed by the etching is different due to the difference in the element group occupation area ratio, that is, the difference in the mask pattern layout, the side wall protection effect per unit area in the second step can be improved. The size of the resist pattern can be adjusted in the first step so as to cancel the difference, or the etching conditions can be adjusted in the second step so as to obtain a desired sidewall protection effect per unit area. . Therefore, when a circuit pattern is formed by a lithography technique and a dry etching technique, it is possible to prevent a situation in which a dimensional variation is caused due to a difference in a mask pattern layout, thereby performing accurate gate electrode processing or wiring processing. Can be.

  In the third method for manufacturing a semiconductor integrated circuit device, the element group may be a memory such as a DRAM.

  In the third method of manufacturing a semiconductor integrated circuit device, the first step preferably includes a step of increasing the size of the resist pattern as the element group occupation area ratio increases.

  In this case, even when the area of the side wall formed on the film to be processed by the etching increases due to an increase in the area occupied by the element group, the side wall protection effect per unit area in the second step is reduced. Since the decrease in the side wall protection effect can be compensated for, the dimensional variation of the components can be reliably suppressed.

  In the third method of manufacturing a semiconductor integrated circuit device, it is preferable that the second step includes a step of setting etching conditions so that the side wall protection effect increases as the element group occupation area ratio increases.

  In this way, even when the area of the side wall formed on the film to be processed by etching increases due to an increase in the area occupied by the element group, a desired side wall protection effect per unit area can be obtained in the second step. Therefore, the dimensional variation of the components can be reliably suppressed.

  According to the present invention, even when the mask pattern layout greatly differs depending on the type of the semiconductor integrated circuit device, it is possible to prevent the dimensional variation in the line-shaped pattern due to the difference in the mask pattern layout. Therefore, even in a system LSI in which the mounting ratio of a DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode or the metal wiring can be made constant irrespective of the mask pattern layout. The device can be realized.

(1st Embodiment)
Hereinafter, a semiconductor integrated circuit device according to a first embodiment of the present invention and a method for manufacturing the same will be described with reference to the drawings. Note that the method for manufacturing a semiconductor integrated circuit device according to the first embodiment includes a circuit pattern having a linear pattern, and is used for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of a manufacturing process common. A method for manufacturing a semiconductor integrated circuit device is assumed.

  A feature of the first embodiment is that a dummy pattern is inserted in an arrangement area of a circuit pattern having a linear pattern, whereby the total peripheral length of the linear pattern and the dummy pattern per unit area is within a predetermined range. It is set to.

  FIG. 1 shows an example of a circuit pattern layout before inserting a dummy pattern in the semiconductor integrated circuit device according to the first embodiment. FIG. 2 shows a dummy pattern in the semiconductor integrated circuit device according to the first embodiment. 5 shows an example of a layout of a circuit pattern after insertion. Although FIGS. 1 and 2 show circuit patterns of a logic circuit, in the first embodiment, a memory circuit such as a RAM or a ROM may be mounted on a chip in addition to the logic circuit. Good.

  As shown in FIG. 1, the circuit pattern is composed of an active region pattern 1 and a gate electrode pattern 2 of a MOS transistor. As shown in FIG. 2, a strip-shaped or linear gate-electrode dummy pattern 4 is inserted into the empty region 3 where the active region pattern 1 and the gate electrode pattern 2 are not provided.

In this case, the peripheral length of the gate electrode can be increased without increasing the chip area. Specifically, the circuit pattern before the dummy pattern insertion shown in FIG. 1 has a gate electrode peripheral edge length of 500 mm / mm ² per unit area, whereas the circuit pattern after the dummy pattern insertion shown in FIG. In, the peripheral edge length of the gate electrode per unit area is increased to 1600 mm / mm ² . That is, in the first embodiment, the result of the small occupation area ratio of the DRAM or ROM or the like where the gate electrode patterns are dense (or the result of not mounting the DRAM or ROM or the like) before the insertion of the dummy pattern is obtained. ), The peripheral length of the gate electrode per unit area was as small as 500 mm / mm ² . In order to make the peripheral length of the gate electrode per unit area of the gate electrode pattern 2 in the circuit pattern shown in FIG. 1 closer to the peripheral length of the gate electrode per unit area in another type having a large DRAM or ROM mounting rate, FIG. As shown in (1), by inserting a large amount of the gate electrode dummy pattern 4, the total gate electrode peripheral length per unit area of the gate electrode pattern 2 and the gate electrode dummy pattern 4 is greatly increased to 1600 mm / mm ^2. ing.

By the way, the variation of CD loss caused by the gate electrode processing process (specifically, gate electrode etching) due to the difference of the peripheral length of the gate electrode per unit area for each product is determined by the error range associated with dimension measurement or reticle manufacturing. In order to suppress this to 0 to 0.003 μm, it is necessary to suppress the difference in the peripheral length of the gate electrode per unit area for each product type to a range of about 500 mm / mm ² (see FIG. 10).

On the other hand, in a system LSI, the mounting rate of a DRAM or a ROM or the like in which gate electrode patterns are densely varies greatly depending on the type, and as a result, the peripheral length of the gate electrode per unit area varies greatly depending on the type. Here, the maximum peripheral edge length of the gate electrode per unit area is a general-purpose DRAM having a DRAM cell with the most dense gate electrode pattern, and its value is about 2500 mm / mm ² .

Therefore, in order to suppress the difference by varieties of the gate electrode periphery length per unit area in the range of about 500 mm / mm ^2, the standard range (predetermined range) may be set with 2000~2500mm / mm ² approximately . However, depending on the layout before the dummy pattern is inserted, there may be a product type in which the dummy pattern cannot be inserted so as to satisfy the gate electrode peripheral length of 2000 mm / mm ² per unit area. In reality, it can be assumed that a system LSI equipped with a DRAM with an occupied area ratio of 70% or more does not occur. Therefore, in the present embodiment, 2000 mm / mm ^2, which corresponds to a case where the DRAM occupation area ratio is 80%, is set as the upper limit of the standard range of the gate electrode peripheral edge length per unit area, and 1600 to 2000 mm / mm ² is set as the unit area. It was set as a standard range of the perimeter of the gate electrode per contact.

  According to the first embodiment, by inserting the gate electrode dummy pattern 4, the peripheral edge length of the gate electrode per unit area in the entire chip, that is, the total gate per unit area of the gate electrode pattern 2 and the gate electrode dummy pattern 4 The electrode peripheral length (the gate electrode peripheral length per unit area including other gate electrode patterns included in the case where a memory circuit not shown is mounted) can be set to a predetermined range. Specifically, it is desirable to assume, as the predetermined range, the gate electrode peripheral length per unit area of the memory circuit, that is, 70 to 100% of the largest gate electrode peripheral length per unit area. At this time, in order to satisfy the standard, the peripheral length per unit area of the inserted gate electrode dummy pattern 4 (for example, a value obtained by dividing the peripheral length of the gate electrode dummy pattern 4 by the area of the empty region 3). ) Needs to be 70% or more of the peripheral length of the gate electrode per unit area of the memory circuit. In this manner, even when the mask pattern layout greatly differs depending on the type of the semiconductor integrated circuit device, the peripheral edge length of the gate electrode per unit area in the entire chip can be reliably set within a predetermined range. For example, a specific circuit such as a memory circuit has a large gate electrode peripheral length per unit area, and thus greatly affects the gate electrode peripheral length per unit area in the entire chip. Also, even when the occupied area ratio of such a specific circuit in a chip varies depending on the product type, the dummy pattern is used as described above to suppress variations in the gate electrode peripheral length per unit area in the entire chip. it can. As a result, it is possible to prevent the occurrence of dimensional variation due to the difference in the mask pattern layout. That is, the gate electrode pattern 2 can always be etched to a fixed size with high accuracy. Therefore, even in a system LSI in which the mounting ratio of a DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode pattern 2 can be made constant regardless of the mask pattern layout. realizable.

In the first embodiment, the method of processing the gate electrode pattern 2 is not particularly limited. For example, a parallel plate type RIE (reactive ion etching) apparatus is used, and a main dry etching is performed. By etching the polysilicon film by setting the flow rate of Cl ₂ gas to 0.04 SLM (Standard Litter per Minute), the flow rate of HBr gas to 0.08 SLM, the pressure to 20 Pa, and the RF power to 300 W, The gate electrode pattern 2 may be formed.

  Further, in the first embodiment, the peripheral length per unit area of the linear pattern constituting the circuit pattern, such as the gate electrode pattern, may be set to a predetermined range without using the dummy pattern.

  In the first embodiment, the processing of the gate electrode is described. However, the present invention is not limited to this, and the processing of a layer having another linear pattern, for example, the processing of a metal wiring made of aluminum or copper or the like is performed. Can achieve the same high processing accuracy.

(Second embodiment)
Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the second embodiment of the present invention will be described with reference to the drawings. The method for manufacturing a semiconductor integrated circuit device according to the second embodiment includes a circuit pattern having a linear pattern, and is used for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of the manufacturing process common. A method for manufacturing a semiconductor integrated circuit device is assumed.

  The feature of the second embodiment is that the ratio of the number of exposure shots for transferring a circuit pattern having a linear pattern to the number of exposure shots for transferring a dummy pattern on a wafer to be exposed is adjusted. By doing so, the total peripheral length per unit area of all the linear patterns to be transferred and all the dummy patterns to be transferred is set in a predetermined range.

  FIG. 3A shows an example of a pattern exposure shot map in a lithography step for forming a polysilicon gate electrode pattern in the method for manufacturing a semiconductor integrated circuit device according to the second embodiment. (B) shows an example of a dummy pattern used in the lithography step.

  In the method for manufacturing a semiconductor integrated circuit device according to the second embodiment, as shown in FIG. 3A, the number of first exposure regions 11 to which circuit patterns are respectively transferred (that is, the number of And the number of the second exposure regions 12 to which the dummy patterns are respectively transferred (that is, the number of exposure shots for transferring the dummy patterns) are adjusted on the wafer 10. Further, in each second exposure region 12, as shown in FIG. 3B, a strip-shaped dummy pattern 13 composed of, for example, a line having a width of 0.2 μm and a space having a width of 0.2 μm is simply spread. Is transferred as follows.

  Thereby, for example, the gate electrode peripheral length per unit area on the wafer 10, that is, the total per unit area of the gate electrode pattern included in all the transferred circuit patterns and all the dummy patterns 13 to be transferred. The peripheral edge length of the gate electrode can be suppressed to a certain range independent of the mask pattern layout of the semiconductor integrated circuit device, that is, the mask pattern layout corresponding to the circuit pattern.

  Specifically, in the present embodiment, a dummy reticle mask for transferring the dummy pattern 13 is used separately from the reticle mask for forming the circuit pattern, and therefore, as compared with the first embodiment, the entire wafer 10 is used. Can be further increased per unit area of the gate electrode.

Further, in the present embodiment, the second exposure region 12 is formed on the wafer 10 in order to set the peripheral edge length of the gate electrode per unit area of the entire wafer 10 in the range of 1600 to 2000 mm / mm ² , for example, as in the first embodiment. The area ratio A occupied on 10 can be calculated as follows. However, the peripheral length per unit area of the dummy pattern transferred to each second exposure area 12 is, for example, 5000 mm / mm ² , and the gate per unit area in the circuit pattern transferred to each first exposure area 11 It is assumed that the electrode peripheral length is, for example, 500 mm / mm ² .

That is,
1600 ≦ 5000 × A + 500 × (1-A) ≦ 2000
Holds, so that
0.244 ≦ A ≦ 0.333
It becomes. As a result, it is necessary to set the number of exposure shots for transferring the dummy pattern so that the area ratio of the second exposure region 12 on the wafer 10 is about 24.5% or more. More specifically, in the present embodiment, as shown in FIG. 3A, a first exposure region 11 for transferring a circuit pattern is provided in an area of ／ (75%) on the wafer 10. A second exposure area 12 for transferring a dummy pattern is provided in the remaining area of 1/4 (25%) on the wafer 10.

  According to the second embodiment, the ratio between the number of exposure shots for circuit pattern transfer and the number of exposure shots for dummy pattern transfer is set so that the peripheral length of the gate electrode per unit area of the entire wafer 10 is set within a predetermined range. adjust. Therefore, even when the mask pattern layout greatly differs depending on the type of the semiconductor integrated circuit device, it is possible to prevent the dimensional variation in the gate electrode pattern due to the difference in the mask pattern layout. Therefore, even in a system LSI in which the mounting ratio of a DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode pattern can be fixed independently of the mask pattern layout, thereby realizing a semiconductor integrated circuit device in which the variation in the operation margin is eliminated. it can.

  In the second embodiment, the peripheral length of the dummy pattern per unit area is preferably at least 70% of the peripheral length of the gate electrode per unit area in the memory circuit mounted on the semiconductor integrated circuit device.

  Further, in the second embodiment, the circuit pattern is transferred such that the gate electrode peripheral length per unit area in the entire wafer is set to 70 to 100% of the gate electrode peripheral length per unit area in the memory circuit. It is preferable to adjust the ratio between the number of exposure shots for the transfer and the number of exposure shots for transferring the dummy pattern.

  Further, in the second embodiment, the gate electrode processing is targeted, but the present invention is not limited to this, and is directed to fine processing of a layer having another linear pattern, for example, processing of a metal wiring made of aluminum or copper or the like. Can achieve the same high processing accuracy.

(Third embodiment)
Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the third embodiment of the present invention will be described with reference to the drawings. The method of manufacturing a semiconductor integrated circuit device according to the third embodiment includes a circuit pattern having a linear pattern, and is used for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of a common manufacturing process. A method for manufacturing a semiconductor integrated circuit device is assumed.

  A feature of the third embodiment is that dry etching is performed on a film to be processed while adjusting dry etching conditions according to the peripheral length per unit area of a linear pattern constituting a circuit pattern. Hereinafter, an example will be described in which the dry etching conditions for forming the gate electrode pattern are selected to suppress the dimensional dependence of the gate electrode pattern on the mask pattern layout of the semiconductor integrated circuit device.

FIG. 4 is a graph showing a relationship between a gate electrode peripheral length per unit area on a chip and a parameter (when a polysilicon gate electrode pattern is formed by dry etching in the manufacture of a plurality of types of semiconductor integrated circuit devices in which circuits of various layouts are incorporated. parameters S1: 600mm / mm ^2, parameter S2: 1000mm / mm ^2, the parameter S3: 1400mm / mm ^2, parameter S4: 1800 mm / as mm ^2), the relationship between the CD loss of flow rate and a gate electrode pattern of the gas for dry etching Is a graph showing the results obtained by experiments. Here, the experimental results shown in FIG. 4 were obtained by using a mixed gas of HBr and Cl ₂ and a cooling gas such as He as the etching gas, and making the gas flow rate of HBr of the mixed gas variable. It was done.

  As shown in FIG. 4, even if the HBr gas flow rate is the same, if the peripheral length of the gate electrode per unit area is different, the CD loss of the gate electrode pattern also changes accordingly. On the other hand, for any value of the peripheral edge length of the gate electrode per unit area, if the HBr gas flow rate is changed, the CD loss can be made substantially zero at a specific flow rate.

  Therefore, in the method of manufacturing a semiconductor integrated circuit device according to the third embodiment, the peripheral length of the gate electrode per unit area in the circuit pattern of each semiconductor integrated circuit device is determined in advance, and at the same time, as shown in FIG. The relationship between dry etching conditions and CD loss is experimentally determined. Then, the dry etching condition (the HBr gas flow rate in FIG. 4) is such that the CD loss of the gate electrode pattern becomes substantially zero to the degree that the design allows the CD loss with respect to the determined gate electrode peripheral length per unit area. In other words, dry etching conditions are selected so that the dimensions of the gate electrode pattern become equal to the target dimensions determined in design, and dry etching is performed on the polysilicon film serving as the gate electrode.

  By the way, for example, in the manufacture of a plurality of types of semiconductor integrated circuit devices on which a memory circuit and a logic circuit are mounted, when the target dimensions of the processing patterns are the same for each type but the layout is significantly different, the method described above is used. By using, in principle, accurate pattern etching can be performed regardless of the layout. However, actually, it is not preferable in terms of mass productivity to obtain the dry etching conditions for each type of layout different, that is, to change the dry etching conditions for each type.

  Therefore, in the present embodiment, the gate electrode perimeter per unit area is divided into a plurality of ranges, and one dry etching condition is set for each of the gate electrode perimeters per unit area in each range. Is also good.

  Table 1 shows the optimum conditions of the dry etching process for each range of the gate electrode peripheral edge length per unit area when forming the polysilicon gate electrode pattern by dry etching.

［表１］に示すように、単位面積当たりのゲート電極周縁長を複数の範囲に区切って、各範囲毎に異なるドライエッチング条件（具体的には異なるＨＢｒガス流量）が適用されている。［表１］に示すドライエッチング条件を用いた場合、図４との対応関係から明らかなように、単位面積当たりのゲート電極周縁長の各範囲（Ｓ１〜Ｓ４）に対してゲート電極パターンのＣＤロスがほぼ０±０．００２μｍ以内の小さい値に収まっている。これにより、０．１μｍ以下の設計ルールのデバイスの製造においても十分なパターン精度を得ることができる。

As shown in [Table 1], the gate electrode peripheral length per unit area is divided into a plurality of ranges, and different dry etching conditions (specifically, different HBr gas flow rates) are applied to each range. When the dry etching conditions shown in [Table 1] are used, the CD of the gate electrode pattern for each range (S1 to S4) of the peripheral length of the gate electrode per unit area is apparent from the correspondence with FIG. The loss is within a small value of approximately 0 ± 0.002 μm. As a result, sufficient pattern accuracy can be obtained even in the manufacture of a device having a design rule of 0.1 μm or less.

  That is, according to the third embodiment, the dry etching is performed on the polysilicon film while adjusting the conditions of the dry etching on the polysilicon film serving as the gate electrode according to the peripheral length of the gate electrode per unit area. Even when the mask pattern layout greatly differs depending on the type of the semiconductor integrated circuit device, the dimension of the gate electrode pattern can always be equal to a predetermined value. Therefore, even in a system LSI in which the mounting rate of a DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode can be made constant irrespective of the mask pattern layout, so that it is possible to realize a semiconductor integrated circuit device in which a variation in an operation margin is eliminated. .

  Further, according to the third embodiment, the peripheral edge length of the gate electrode per unit area is divided into a plurality of ranges, and one dry etching condition is set for each range. Adjustment of dry etching conditions can be easily performed as compared with the case of changing.

  In the third embodiment, the CD loss of the gate electrode pattern is controlled by adjusting the flow rate of the HBr gas in the dry etching for forming the polysilicon gate electrode. Optimal dry etching conditions can also be set by adjusting the flow rate, the etching gas pressure, the RF power of the dry etching apparatus, and the like.

  Further, in the third embodiment, for example, when an organic coating film serving as a light reflection preventing film is formed on a polysilicon film serving as a gate electrode in a lithography process, or a hard mask is formed by a CVD (Chemical Vapor Deposition) method, for example. In the case where a silicon oxide film or the like to be formed on a polysilicon film to be a gate electrode is used, the etching conditions for the organic coating film or the CVD silicon oxide film or the like are adjusted instead of the etching conditions for the polysilicon film. May be.

  In the third embodiment, the processing of the gate electrode is targeted, but the present invention is not limited to this. For example, fine processing of a layer having another linear pattern, for example, etching of a metal wiring, or formation of a groove for a buried wiring is performed. The same high processing accuracy can be achieved also for the etching processing of the insulating film to be performed.

(Fourth embodiment)
Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the fourth embodiment of the present invention will be described with reference to the drawings. The method for manufacturing a semiconductor integrated circuit device according to the fourth embodiment includes a circuit pattern having a linear pattern, and is used for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of the manufacturing process common. A method for manufacturing a semiconductor integrated circuit device is assumed.

  In the third embodiment, the dry etching conditions are adjusted according to the peripheral length per unit area of the linear pattern forming the circuit pattern. On the other hand, the feature of the fourth embodiment is that a resist pattern corresponding to a line pattern constituting a circuit pattern is formed while adjusting its dimension according to the peripheral length per unit area of the line pattern. It is. Hereinafter, a case will be described as an example in which the dimension dependence of the gate electrode pattern on the mask pattern layout of the semiconductor integrated circuit device is suppressed by adjusting the dimension of the resist pattern corresponding to the gate electrode pattern.

Specifically, in the fourth embodiment, when a polysilicon gate electrode pattern is formed by dry etching in the manufacture of a plurality of types of semiconductor integrated circuit devices incorporating circuits of various layouts, HBr is used as an etching gas. And a mixed gas of Cl ₂ and a cooling gas such as He, and a gas flow rate of HBr in the mixed gas is fixed at 0.07 SLM. That is, in the fourth embodiment, the dry etching conditions are set to the recipe No. shown in [Table 1] of the third embodiment. It is fixed to the dry etching condition (standard condition) of PS3. When the dry etching conditions are fixed in this way, for example, as shown in FIG. 4 of the third embodiment, the value of the CD loss of the gate electrode pattern differs depending on the mask pattern layout.

  Therefore, in the method of manufacturing the semiconductor integrated circuit device according to the fourth embodiment, first, the relationship between the peripheral edge length of the gate electrode per unit area in the circuit pattern of each semiconductor integrated circuit device and the CD loss of the gate electrode pattern is determined. deep. Then, the size of the resist pattern serving as a dry etching mask is changed, for example, by a photo- It is adjusted according to the lithography conditions.

  Table 2 shows the relationship between the gate electrode pattern and each range of the gate electrode peripheral length per unit area when a resist pattern corresponding to the polysilicon gate electrode pattern is formed and dry etching is performed using the resist pattern. 3 shows a CD loss (A), a target dimension (B) in a photolithography process, and a design dimension (C) of a gate electrode pattern after dry etching.

［表２］において、ＣＤロス（Ａ）は［表１］に示すレシピＮｏ．ＰＳ３のドライエッチング条件を用いた場合の値である。また、目標寸法（Ｂ）は、前述のようにＣＤロス（Ａ）の大きさを考慮して調整されたレジストパターンの最適寸法である。また、本実施形態においては、設計寸法（Ｃ）を０．１５０μｍとしている。

In [Table 2], the CD loss (A) is the recipe No. shown in [Table 1]. This is a value when the dry etching condition of PS3 is used. The target dimension (B) is the optimum dimension of the resist pattern adjusted in consideration of the CD loss (A) as described above. In the present embodiment, the design dimension (C) is 0.150 μm.

here,
Target dimension (B) = CD loss (A) + design dimension (C)
Since the following relational expression is satisfied, the target dimension (B), that is, the value of the optimum dimension of the resist pattern, as shown in [Table 2], can be specifically set by using the relational expression. Conversely, by adjusting the target dimension (B) in the photolithography process, it is possible to offset the adjustment and the CD loss (A).

  In the present embodiment, the design dimension (C) is 0.150 μm, and the dry etching conditions are the recipe No. shown in [Table 1]. Paying attention to PS3 (HBr gas flow rate: 0.07 SLM), for example, when the HBr gas flow rate is 0.07 SLM in FIG. 4, each range of the gate electrode peripheral edge length per unit area (S1 to S4) By reading the CD loss corresponding to the above, the target dimension (B) in the photolithography process can be easily set. In this embodiment, the recipe No. shown in [Table 1] is used as the dry etching condition. The reason for using PS3 is as follows. That is, as is clear from [Table 2], the recipe No. When the PS3 is used, the amount of adjustment of the target dimension (B) corresponding to the magnitude of the CD loss (A) is the most relative to the gate electrode peripheral length per unit area realized in each type of semiconductor integrated circuit device. This is because it becomes smaller.

  As described above, according to the fourth embodiment, since the resist pattern corresponding to the gate electrode pattern is formed while adjusting its size according to the gate electrode peripheral length per unit area, the semiconductor integrated circuit device The size of the gate electrode pattern can always be equal to a predetermined value even when the mask pattern layout greatly differs depending on the product type. Therefore, even in a system LSI in which the mounting rate of a DRAM or the like differs depending on the application or specification, the processing dimensions of the gate electrode can be made constant irrespective of the mask pattern layout, so that it is possible to realize a semiconductor integrated circuit device in which a variation in an operation margin is eliminated. .

  In the fourth embodiment, the adjustment of the target dimension in the photolithography process, that is, the adjustment of the dimension of the resist pattern corresponding to the gate electrode pattern is most preferably performed by, for example, increasing or decreasing the exposure amount in exposing the resist film. It is simple. Further, the dimensions of a light-shielding pattern (for example, a chrome pattern) on the photomask may be corrected. In this case, there is no need to increase or decrease the amount of exposure, which is advantageous in the operation of the manufacturing process.

  Further, in the fourth embodiment, the gate electrode processing is targeted, but the present invention is not limited to this, and may be directed to fine processing of a layer having another linear pattern, for example, processing of a metal wiring made of aluminum or copper or the like. Can achieve the same high processing accuracy.

(Fifth embodiment)
Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment of the present invention will be described with reference to the drawings. The method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment includes a circuit pattern having a linear pattern, and is used for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of the manufacturing process common. A method for manufacturing a semiconductor integrated circuit device is assumed. In the following description, a method of forming a gate electrode in a system LSI in which a memory having a repetitive pattern such as a DRAM can be mixedly mounted will be described as an example.

  FIGS. 5A to 5D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment.

  First, as shown in FIG. 5A, after a silicon oxide film 22 having a thickness of about 5 nm serving as a gate insulating film is formed on a silicon substrate 21, a thickness serving as a gate electrode is formed on the silicon oxide film 22. A polysilicon film 23 having a thickness of about 200 nm is formed, and then an organic coating film 24 having a thickness of about 100 nm serving as a light reflection preventing film in a lithography step (see FIG. 5B) is formed on the polysilicon film 23. .

  Next, as shown in FIG. 5B, the minimum line width (gate) corresponding to the gate electrode 26 having a linear pattern (see FIG. 5D) is formed on the organic coating film 24 by using a lithography technique. A resist pattern 25 (target electrode dimensions) of 0.15 μm (having a thickness of about 600 nm) is formed.

  Next, as shown in FIG. 5C, dry etching is performed on the organic coating film 24 using the resist pattern 25 as a mask.

In this case, when the semiconductor integrated circuit device is a DRAM not mounted varieties, for example, into the chamber the pressure is set to 10 Pa, an etching gas comprising a mixed gas of SO ₂ gas and O ₂ gas, the SO ₂ gas At a flow rate of 20 cc / min and a flow rate of O ₂ gas of 20 cc / min, dry etching is performed by applying a high frequency power (RF power) of 200 W to the sample stage. Further, when the semiconductor integrated circuit device is a DRAM-mounted type, for example, an etching gas composed of a mixed gas of SO ₂ gas and O ₂ gas is placed in a chamber set at a pressure of 10 Pa, and a flow rate of SO ₂ gas: At a flow rate of 25 cc / min and a flow rate of O ₂ gas of 20 cc / min, dry etching is performed by applying a high-frequency power of 200 W to the sample stage. In the present embodiment, the gas flow rate is represented using the flow rate per minute in the standard state (0 ° C., 1 atm).

That is, in the dry etching process for the organic coating film 24, the etching conditions are changed depending on whether or not the DRAM is mounted. Specifically, in the case of a DRAM-mounted product, the flow rate of SO ₂ gas having an effect of protecting the side wall formed on the organic coating film 24 by etching is reduced from 20 cc / min to 25 cc / min in the case of a DRAM-free product. And increase. Thereby, even when the area of the side wall of the organic coating film 24 is increased by mounting the DRAM, a desired side wall protection effect per unit area can be obtained. Can be patterned to have a desired dimension (0.15 μm).

  Next, after the polysilicon film 23 is dry-etched using the resist pattern 25 or the patterned organic coating film 24 as a mask, as shown in FIG. 24 is removed by ashing to form a gate electrode 26 made of the polysilicon film 23. At this time, since the organic coating film 24 is patterned so as to have a desired size regardless of whether or not the DRAM is mounted, the occurrence of CD loss is prevented and the gate electrode 26 having a desired size (0.15 μm) is prevented. Can be formed.

In the dry etching process for the polysilicon film 23, for example, regardless of whether the product is a product without a DRAM or a product with a DRAM, for example, a Cl ₂ gas and an HBr gas are placed in a chamber set at a pressure of 20 Pa. An etching gas composed of a mixed gas is introduced at a flow ratio of Cl ₂ gas: 40 cc / min, HBr gas: 80 cc / min, and high-frequency power of 300 W is applied to the sample stage to perform dry etching. . That is, in the dry etching process for each of the polysilicon film 23 and the organic coating film 24, different facilities and conditions are used.

As described above, according to the fifth embodiment, in the step of performing dry etching on the organic coating film 24 using the resist pattern 25 corresponding to the gate electrode 26 having a linear pattern as a mask, whether or not a DRAM is mounted The etching conditions are changed according to. More specifically, the flow rate of SO ₂ gas having the effect of protecting the side wall formed on the organic coating film 24 by etching is increased in the case of the DRAM-mounted type, as compared with the case of the DRAM non-mounted type. For this reason, even if the area of the side wall of the organic coating film 24 is increased by mounting the DRAM, a desired side wall protection effect per unit area can be obtained, so that the organic coating film 24 has a desired size. Can be patterned. Therefore, by performing dry etching on the polysilicon film 23 using the patterned organic coating film 24 as a mask, the gate electrode 26 having desired dimensions can be formed. That is, the dimensional variation of the gate electrode 26 due to the difference in the mask pattern layout depending on the presence or absence of the DRAM can be reliably suppressed, and the gate electrode can be processed with high accuracy.

  FIG. 6 shows a CD loss (resist before etching) in a case where a variety of products having various DRAM occupying area ratios including a variety of products without a DRAM are manufactured using the method of manufacturing a semiconductor integrated circuit device according to the fifth embodiment. The figure shows the relationship between the dimension of the pattern minus the dimension of the completed gate electrode) and the DRAM occupation area ratio.

  As shown in FIG. 6, according to the fifth embodiment, regardless of the presence or absence of a DRAM, the occurrence of CD loss was suppressed and a desired gate electrode dimension of 0.15 μm was realized.

  FIG. 7 shows, as a comparative example, CD loss and DRAM occupied area ratio in the case where products having various DRAM occupied area ratios including products without DRAM are manufactured using the same etching conditions regardless of whether or not DRAM is installed. The relationship is shown.

  As shown in FIG. 7, according to the comparative example, it is possible to suppress the occurrence of CD loss in the product without DRAM, but to generate the CD loss of about +0.013 μm on average in the product with DRAM.

In the fifth embodiment, the etching condition of the organic coating film 24 (specifically, the flow rate of SO ₂ gas having an effect of protecting the side wall of the organic coating film 24) is changed depending on whether or not the DRAM is mounted. The etching conditions for the polysilicon film 23 were made common regardless of the presence or absence of the DRAM. Instead, the etching conditions for the organic coating film 24 were made common regardless of the presence or absence of the DRAM. May be changed according to the conditions. At this time, for example, the flow rate of the HBr gas for forming an etching reaction product (such as SiBr ₄ ) having an effect of protecting the side wall of the polysilicon film 23 as the side wall protection film is changed depending on whether or not the DRAM is mounted. Is also good. When a structure in which a silicon oxide film or the like is formed on a polysilicon film is adopted as the gate electrode structure, the etching conditions of the silicon oxide film are changed to change the gate electrode due to the presence or absence of the DRAM. May be suppressed.

  Further, in the fifth embodiment, the etching conditions are changed depending on whether or not the DRAM is mounted. Alternatively, the etching conditions may be finely changed according to the DRAM occupation area ratio.

  In the fifth embodiment, the gate electrode is formed. However, the present invention is not limited to this, and another line pattern, for example, a metal wiring may be formed.

  The fifth embodiment is directed to a system LSI on which a memory such as a DRAM can be mounted. However, the present invention is not limited to this. Another element group in which a plurality of semiconductor elements are arranged to have a repetitive pattern It may be a system LSI capable of mounting.

(Sixth embodiment)
Hereinafter, a method for manufacturing a semiconductor integrated circuit device according to the sixth embodiment of the present invention will be described with reference to the drawings. The method for manufacturing a semiconductor integrated circuit device according to the sixth embodiment includes a circuit pattern having a linear pattern, and is used for manufacturing a plurality of semiconductor integrated circuit devices having at least a part of the manufacturing process common. A method for manufacturing a semiconductor integrated circuit device is assumed. In the following description, a method of forming a gate electrode in a system LSI in which a memory having a repetitive pattern such as a DRAM can be mixedly mounted will be described as an example. FIGS. 5A to 5D are cross-sectional views showing each step of the method for manufacturing a semiconductor integrated circuit device according to the sixth embodiment, similarly to the fifth embodiment.

  The differences between the sixth embodiment and the fifth embodiment are as follows. That is, in the fifth embodiment, a step of performing dry etching on the organic coating film 24 using the resist pattern 25 corresponding to the gate electrode 26 having a linear pattern as a mask (see FIGS. 5C and 5D). , The etching conditions were changed depending on whether or not the DRAM was mounted. On the other hand, in the sixth embodiment, in the step of forming the resist pattern 25 (see FIG. 5B), the dimensions of the resist pattern 25 are changed according to the area occupied by the DRAM.

Specifically, in the sixth embodiment, for example, as shown in FIG. 7, the CD loss (the value obtained by subtracting the size of the completed gate electrode from the size of the resist pattern before etching) and the DRAM occupation area ratio are as shown in FIG. By acquiring the relationship in advance, for example, the following formula (size of resist pattern)
= (DRAM occupation area ratio and corresponding CD loss predicted value)
+ (Target size of gate electrode)
Is used to set the dimensions of the resist pattern.

  As shown in FIG. 7, since the CD loss increases as the DRAM occupation area ratio increases, according to the above equation, the dimension of the resist pattern 25 increases as the DRAM occupation area ratio increases. By doing so, the following effects can be obtained in the sixth embodiment. In other words, the area of the side wall formed on the polysilicon film 23 or the organic coating film 24 by the etching using the resist pattern 25 as a mask increases due to an increase in the area occupied by the DRAM, and the side wall protection effect per unit area decreases. In this case, the decrease in the side wall protection effect can be compensated for by adjusting the dimensions of the resist pattern 25. Therefore, the dimensional variation of the gate electrode 26 due to the difference in the mask pattern layout due to the difference in the DRAM occupation area ratio can be reliably suppressed, and the gate electrode can be processed with high accuracy.

  [Table 3] shows target dimensions of 0.15 μm in the case of using the method of manufacturing a semiconductor integrated circuit device according to the sixth embodiment to manufacture products having various DRAM occupying area ratios, including products without a DRAM. Of the resist pattern for forming the gate electrode of FIG. In Table 3, the predicted values of the CD loss corresponding to the respective DRAM occupied area ratios are shown for reference.

レジストパターン２５の寸法を［表３］に示すように設定することによって、第６の実施形態において、ＤＲＡＭ占有面積率に関わらず、所望のゲート電極寸法である０．１５μｍを実現することができた。

By setting the dimensions of the resist pattern 25 as shown in [Table 3], in the sixth embodiment, a desired gate electrode dimension of 0.15 μm can be realized regardless of the DRAM occupation area ratio. Was.

  In the sixth embodiment, the dimensions of the resist pattern 25 are changed in accordance with the area occupied by the DRAM. However, the dimensions of the resist pattern 25 may be roughly changed in accordance with the presence or absence of the DRAM. .

  Further, in the sixth embodiment, as a specific method of adjusting the dimension of the resist pattern 25, for example, a method of adjusting an exposure amount, a method of adjusting a mask pattern dimension on a reticle, or the like may be used.

  Further, in the sixth embodiment, the formation of the gate electrode is targeted, but the invention is not limited to this, and the formation of another line pattern, for example, a metal wiring or the like may be targeted.

  The sixth embodiment is directed to a system LSI on which a memory such as a DRAM can be mounted. However, the present invention is not limited to this. Another element group in which a plurality of semiconductor elements are arranged to have a repetitive pattern It may be a system LSI capable of mounting.

  The present invention relates to a method of manufacturing a semiconductor integrated circuit device, which is applied to the formation of a linear pattern such as a gate electrode of a MOS transistor in a system LSI in which an element group having a fine repetitive pattern such as a DRAM can be mounted. Especially useful.

FIG. 2 is a diagram illustrating an example of a circuit pattern layout before inserting a dummy pattern in the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating an example of a circuit pattern layout after inserting a dummy pattern in the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 7A is a diagram illustrating an example of a pattern exposure shot map in a lithography step for forming a polysilicon gate electrode pattern in a method for manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention; (b) is a diagram showing an example of a dummy pattern used in the lithography step. When a polysilicon gate electrode pattern is formed by dry etching in the manufacture of a plurality of types of semiconductor integrated circuit devices, the flow rate of the dry etching gas and the CD of the gate electrode pattern are determined by using the peripheral length of the gate electrode per unit area on the chip as a parameter. It is a figure showing the result of having calculated the relation with loss by experiment. (A)-(d) is sectional drawing which shows each process of the manufacturing method of the semiconductor integrated circuit device which concerns on 5th or 6th embodiment of this invention. The CD loss and the DRAM occupation area ratio when products having various DRAM occupied area ratios, including products without a DRAM, are manufactured using the method for manufacturing a semiconductor integrated circuit device according to the fifth embodiment of the present invention. FIG. As a comparative example, the relationship between the CD loss and the DRAM occupation area ratio when products having various DRAM occupied area ratios, including products without a DRAM, were manufactured using the same etching conditions regardless of whether or not a DRAM was installed. FIG. FIG. 7 is a diagram showing a frequency distribution of CD loss in a case where a DRAM-mounted product on which a DRAM is mounted and a DRAM-free product are manufactured using the same gate electrode processing process. FIG. 9 is a diagram showing a relationship between a peripheral edge length of a gate electrode per unit area and a DRAM occupation area ratio in products having various DRAM occupying area ratios, including products without a DRAM. FIG. 7 is a diagram showing a relationship between a gate electrode peripheral length per unit area and CD loss in various types.

Explanation of reference numerals

Reference Signs List 1 active region pattern 2 gate electrode pattern 3 free region 4 gate electrode dummy pattern 10 wafer 11 first exposure region 12 second exposure region 13 dummy pattern 21 silicon substrate 22 silicon oxide film 23 polysilicon film 24 organic coating film 25 resist Pattern 26 Gate electrode

Claims (8)

A method for manufacturing a semiconductor integrated circuit device for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a line-shaped pattern and at least a part of a manufacturing process being common,
The manufacturing process of each of the semiconductor integrated circuit devices includes:
A method of manufacturing a semiconductor integrated circuit device, comprising a step of performing dry etching on a film to be processed while adjusting dry etching conditions according to a peripheral length per unit area of the linear pattern.   The method according to claim 1, wherein the step of adjusting the dry etching condition includes a step of setting one dry etching condition when a peripheral edge length per unit area of the linear pattern is within one range. The manufacturing method of the semiconductor integrated circuit device described in the above. A method for manufacturing a semiconductor integrated circuit device for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a line-shaped pattern and at least a part of a manufacturing process being common,
The manufacturing process of each of the semiconductor integrated circuit devices includes:
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a resist pattern corresponding to the line-shaped pattern while adjusting its dimension according to a peripheral length per unit area of the line-shaped pattern. A method for manufacturing a semiconductor integrated circuit device for manufacturing a plurality of semiconductor integrated circuit devices having a circuit pattern having a line-shaped pattern and at least a part of a manufacturing process being common,
The manufacturing process of each of the semiconductor integrated circuit devices includes:
A first step of forming a resist pattern corresponding to the line-shaped pattern on a film to be processed;
A second step of performing dry etching on the film to be processed using the resist pattern as a mask,
The second step uses an etching gas having a side wall protection effect of protecting a side wall formed on the film to be processed by etching, or includes a step of forming an etching reaction product having the side wall protection effect,
A processing method or a processing condition in at least one of the first step and the second step, wherein the area of an element group having a repetitive pattern included in the circuit pattern has an area where the circuit pattern is arranged. A method of manufacturing the semiconductor integrated circuit device, wherein the method is adjusted according to a ratio of the area to the area of the semiconductor integrated circuit device.   5. The method according to claim 4, wherein the element group is a memory.   6. The method according to claim 5, wherein the memory is a DRAM.   5. The method according to claim 4, wherein the first step includes a step of increasing the size of the resist pattern as the ratio increases.   5. The method according to claim 4, wherein the second step includes a step of setting an etching condition so that the side wall protection effect increases as the ratio increases.

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