JPH0934808A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data processing system by which information of a recoverable or unrecoverable fault of a host interface bus is collected quickly and surely and informed to a host device without incurring increase in the manufacture cost. SOLUTION: On the occurrence of a fault in a host interface bus 2-1, a fault information control section 34 of a peripheral controller 3-1 receiving a fault occurrence notice from a host device 1 or via a peripheral controller 3-2 and a subordinate interface bus 4 edits fault information. The edited fault information is saved in a peripheral equipment, e.g. 5-1 and reported to the host device 1 via the peripheral controller 3-2 or directly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system, and more particularly to an improvement in a method for collecting fault information.

[0002]

2. Description of the Related Art As a data processing system, a host device,
There is a configuration in which a peripheral control device and a peripheral device are configured as three layers, a higher-level device and a peripheral control device are connected by a higher-level interface bus, and a peripheral control device and the peripheral device are connected by a lower-level interface bus.

In the above-described conventional method of collecting fault information in the data processing system, when a fault occurs in a certain upper interface bus, if the fault can be recovered, the fault information is temporarily stored in the peripheral control device. However, when the upper interface bus recovers, the failure information is reported to the upper device.

Another conventional method for collecting fault information has been performed by providing a dedicated microprocessor for collecting fault information in a peripheral control device (see Japanese Patent Application Laid-Open No. 58-64556). .

[0005]

However, the former method for collecting fault information described above has a problem that when a fixed fault that cannot be recovered from the higher-level interface bus occurs, fault information cannot be collected from the higher-level device. is there.
In addition, since the fault information collected after the recovery of the upper interface bus is collected using the upper interface bus having a history of occurrence of a fault in the past, there is also a problem that the fault information is not reliable.

Further, the latter method of collecting fault information has a problem that if a dedicated microprocessor for collecting fault information is not connected, even if the fault occurs, the fault cannot be analyzed immediately. . In addition, hardware for providing a dedicated microprocessor for collecting fault information is also required, which causes an increase in manufacturing cost.

Accordingly, it is an object of the present invention to provide a method for quickly and reliably recovering or unrecoverable failure of an upper interface bus without increasing manufacturing costs.
It is an object of the present invention to provide a data processing system that can collect and report the collected data to a host device.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a host device, a plurality of peripheral control devices connected to the host device through respective host interface buses, and a peripheral control device. A data processing system comprising a peripheral device commonly connected via a lower interface bus, wherein each peripheral control device receives a failure occurrence notification from a higher-level device or a failure occurrence notification from another peripheral control device. Editing means for editing the fault information of the corresponding upper interface bus, saving means for saving the edited fault information to one of the peripheral devices via the lower interface bus, and the other peripheral control device described above. Reporting means for reporting fault information evacuated to a peripheral device to a higher-level device via another peripheral control device. Alternatively,
Means are provided for directly reporting the edited fault information to the higher-level device via the above-mentioned other peripheral control device without saving the information to the peripheral device.

[0009]

According to the above-described means, not only at the time of occurrence of a recoverable failure but also at the time of the occurrence of an unrecoverable failure, failure information is collected and reported to a higher-level device.

[0010]

FIG. 1 is a block circuit diagram showing an embodiment of a data processing system according to the present invention. In FIG. 1, 1
Is a host device, 2-1 and 2-2 are host interface buses, and the host device 1 and peripheral control devices 3-1 and 3-2
And connect. The peripheral control devices 3-1 and 3-2 are commonly connected to peripheral devices (for example, disk devices) 5-1 to 5-6 via the lower interface bus 4. The higher-level devices connected to the higher-level interface buses 2-1 and 2-2 need not be the same, but may be different.

The peripheral controller 3-1 (3-2) includes a higher-level interface controller 31 (31 ') for performing protocol control with the higher-level interface bus 2-1 (2-2).
Lower interface controller 32 (32 ') for performing protocol control with the lower interface bus 4, CPU3
3 (33 '), a failure information control unit 34 (34') composed of firmware, and an internal bus 35 (35 ') interconnecting them. Hereinafter, the circuit operation when a failure occurs in the upper interface bus 2-1 will be described with reference to FIG.

FIGS. 2 and 3 are sequence diagrams showing a first operation example. First, referring to FIG. 2, the occurrence of a failure is notified from the upper device 1 to the CPU 33 of the peripheral control device 3-1 via the upper interface bus 2-1. As a result, the CPU 33 notifies the failure information control unit 34 that a failure has occurred. Next, the failure information control unit 34 edits the failure information from the internal information of the CPU 33.

When the editing is completed, the fault information control unit 34 instructs the fault information to be saved to a peripheral device. At this time, the failure information control unit 34 notifies the CPU 33 of the selection of the peripheral device designated in advance by the higher-level device 1 such as 5-1 and the storage position and data length of the failure information. Next, the CPU 33
Notifies the peripheral device 5-1 of the failure information write command via the lower interface bus 4. As a result, the failure information is transferred from the failure information control unit 34 to the peripheral device 5-1. This completes saving the fault information to the peripheral device 5-1.

When the evacuation of the fault information is completed, the peripheral device 5
-1 indicates the failure information reception notification to the lower interface bus 4
To the CPU 33 via. Next, the CPU 33 sends a transfer completion notification to the failure information control unit 34.

Next, the fault information control unit 34 instructs the CPU 33 to select the peripheral control device 3-2. As a result, the CPU 33 selects the peripheral control device 3-2 via the lower interface bus 4 in the same manner as the selection of the peripheral device.

When the selection of the peripheral control device 3-2 is successful,
The CPU 33 of the peripheral control device 3-1 sends the peripheral device 5-1 storing the fault information and a fault information collection instruction accompanied by its storage position and data length to the CPU 3 of the peripheral control device 3-2.
Send to 3 '.

Next, referring to FIG.
-2 CPU 33 'is the upper interface bus 2-2
Is activated, and the peripheral device 5-1 is selected via the lower interface bus 4 and a failure information read command is transmitted. As a result, the fault information saved in the peripheral device 5-1 is transferred to the lower interface bus 4, the peripheral controller 3-
2 and the upper device 1 via the upper interface bus 2-2. As described above, in the first operation example, it is possible to collect fault information of another system using the lower interface bus 4.

FIGS. 4 and 5 are sequence diagrams showing a second operation example. First, referring to FIG. 4, the occurrence of a failure is notified from the higher-level device 1 to the CPU 33 'of the peripheral control device 3-2 via the higher-level interface bus 2-2. As a result, the CPU 33 'selects the peripheral control device 3-1 via the lower interface bus 4, similarly to the selection of the peripheral device. When the selection of the peripheral control device 3-1 is completed, the CPU 33 'of the peripheral control device 3-2 instructs the failure information to be saved to the peripheral device. At this time, the CPU 33 of the peripheral control device 3-1 is notified of the selection of the peripheral device designated in advance by the higher-level device 1, for example, 5-1 and the storage position and data length of the fault information.

Next, referring to FIG.
At -1, the CPU 33 notifies the failure information control unit 34 of the occurrence of the failure. Next, the failure information control unit 34
The fault information is edited from the internal information of No. 3.

When the editing is completed, the fault information control unit 34 instructs the fault information to be saved in the peripheral device. At this time, the selection of the peripheral device 5-1 designated by the above-mentioned higher-level device 1 and the storage position and data length of the failure information are determined by the failure information control unit 34.
Is notified to the CPU 33. Next, the CPU 33 notifies the peripheral device 5-1 of a failure information write command via the lower interface bus 4. As a result, the failure information is transferred from the failure information control unit 34 to the peripheral device 5-1. This completes saving the fault information to the peripheral device 5-1.

When the evacuation of the fault information is completed, the peripheral device 5
-1 indicates the failure information reception notification to the lower interface bus 4
To the CPU 33 via. Next, the CPU 33 sends a transfer completion notification to the failure information control unit 34.

Next, the fault information control unit 34 sends a notification to the peripheral control device 3-2 so as to report the completion of the evacuation of the fault information.
Instruct U33.

Returning to FIG. 4, the CPU 33 reports to the peripheral controller 3-2 via the lower interface bus 4 that the saving of the fault information has been completed.

Next, the CPU 33 'of the peripheral control device 3-2.
Activates the upper interface bus 2-2,
The peripheral device 5-1 is selected via the lower interface bus 4 and a failure information read command is transmitted. As a result, the fault information saved in the peripheral device 5-1 is transferred to the upper device 1 via the lower interface bus 4, the peripheral controller 3-2, and the upper interface bus 2-2. Thus, also in the second operation example, it is possible to collect fault information of another system using the lower interface bus 4.

FIG. 16 is a sequence diagram showing a third operation example. First, the occurrence of a failure from the higher-level device 1 via the higher-level interface bus 2-2 is detected by the CP of the peripheral controller 3-2.
U33 'will be notified. As a result, the CPU 33 'selects the peripheral control device 3-1 via the lower interface bus 4, similarly to the selection of the peripheral device. Peripheral control device 3-
1 is completed, the CPU 3 of the peripheral control device 3-2
3 'instructs collection of fault information. At this time, the peripheral control device 3-2 is designated as the transfer destination of the failure information.

Next, in the peripheral control device 3-1, the CP
U33 notifies the failure information control unit 34 of the failure occurrence. Next, the failure information control unit 34 edits the failure information from the internal information of the CPU 33.

When the editing is completed, the trouble information control unit 34 sends a trouble information transfer command to the CPU 33. In response to this, the CPU 33 issues a fault information write command via the lower interface bus 4 to the CPU 3 of the peripheral control device 3-2.
Notify 3 '. As a result, the fault information is transferred from the fault information control unit 34 to the peripheral control device 3-2. Next, the CPU 33 'of the peripheral control device 3-2 activates the upper interface bus 2-2, and the failure information is transferred to the upper device 1 via the upper interface bus 2-2. As described above, also in the third operation example, it is possible to collect fault information of another system using the lower interface bus 4.

As described above, according to the present description, recoverable or unrecoverable failures of the upper interface bus are promptly and reliably collected without increasing the manufacturing cost, and reported to the upper device. it can.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing one embodiment of a data processing system according to the present invention.

FIG. 2 is a sequence diagram showing a first operation example of FIG. 1;

FIG. 3 is a sequence diagram showing a first operation example of FIG. 1;

FIG. 4 is a sequence diagram showing a second operation example of FIG. 1;

FIG. 5 is a sequence diagram showing a second operation example of FIG. 1;

FIG. 6 is a sequence diagram showing a third operation example of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Upper device 2-1 and 2-2 ... Upper interface bus 3-1 and 3-2 ... Peripheral controller 4 ... Lower interface bus 5-1 and 5-6 ... Peripheral device

Claims (4)

[Claims] 1. A host device (1) and a plurality of peripheral control devices (3-1, 3-2) connected to the host device via respective host interface buses (2-1, 2-2). A peripheral device (5-1, 5-2, ...) Commonly connected to each of the peripheral control devices via a lower interface bus (4). Includes an editing means for editing the failure information of the corresponding upper interface bus, a saving means for saving the edited failure information to one of the peripheral devices via the lower interface bus, and another peripheral control device. A data processing system comprising: a reporting unit that reports failure information selected and saved in the peripheral device to the host device via the other peripheral control device. 2. The data processing apparatus according to claim 1, wherein the editing unit edits the failure information by directly receiving a failure occurrence notification from the host apparatus. 3. The data processing system according to claim 1, wherein the editing means edits the failure information by receiving a failure occurrence notification from the other peripheral control device via the lower interface bus. 4. A host device (1) and a plurality of peripheral control devices (3-1, 3-2) connected to the host device via respective host interface buses (2-1, 2-2). A data processing system comprising: peripheral devices (5-1, 5-2, ...) Commonly connected to the peripheral control devices via a lower interface bus (4), Means for receiving a fault occurrence notification from another peripheral control device via the lower interface bus, and editing the fault information of the corresponding upper interface bus; and the edited fault information via the lower interface bus. And a means for reporting to the higher-level device via another peripheral control device.