JPH0934649A - Method and device for error correction, reproducing device, and recording and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the method and device for error correction which improve the correction capability as the whole while preventing the rise of the erroneous correction rate with respect to error correction of data. SOLUTION: An error position and error pattern operation circuit 302 obtains the error position of a reception word and its error pattern and stores them in an error position register 303 and an error pattern register 304 respectively. An uncorrectability discriminator 311 checks the number of generated burst errors stored in the error pattern register 304 and the error length of each burst error and changes the limit of the error correction range in accordance with the result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ECC control system and apparatus suitable for error processing in reading data from a storage medium (in particular, a disk type storage medium), and a recording apparatus equipped with the same.

[0002]

2. Description of the Related Art When reading and transferring data from a magnetic disk, an error may occur in the data due to various factors. Therefore, in order to improve the reliability of data transfer, redundant bits have been added to data for recording. A magnetic disk controller (hereinafter referred to as "H") provided between the magnetic disk device and the computer.
Called "DC") by using this redundant bit,
It is possible to check and correct an error in the read data. For example, when the Reed-Solomon code is used as the error correction code, the symbol length is n bits, and the redundant part of h symbols is added to the data part, error correction of at most h / 2 symbols is possible. A device of this kind is described in, for example, US Pat. Nos. 4,494,234 and 4,504,948.

By the way, when performing error correction, it is necessary to consider the problem of erroneous correction. Here, "erroneous correction" means that an error that exceeds the limit of the correction capability has occurred, and when a certain code word happens to be garbled into a code sequence within the correction range of the code word that is different from that apparently, This means that the codeword should be treated as uncorrectable but erroneous error correction is performed.

The principle of occurrence of this erroneous correction will be described with reference to FIG.

Consider a case where an error occurs in the signal transmission path and a certain code word A (80) becomes a different code sequence from this. The area 86 represents a set of code sequences that can be corrected to the codeword A (80) by the error correction means. For example, a code sequence i (8
8), the error correction means can correct the erroneous code into codeword A. Code word A
When (80) is received as an erroneous code sequence j (89), this erroneous code sequence j (89) is out of the correctable range by the error correction means, and is therefore an uncorrectable error. To be detected. However, the code word A
When (80) is received as an erroneous code sequence k (90), this code sequence k (90) is included in the area 85 to be corrected to a different code word D (91) by the error correction means. Therefore, the code sequence k (90) is erroneously corrected to the code word D (91). In this way, erroneous correction occurs.

As is clear from FIG. 13, the wider the correctable range for each code, the higher the probability that erroneous correction will occur. The erroneous correction rate (probability of erroneous correction) Pmc can be expressed by Equation 1 below.

[0007]

[Equation 1]

Generally, in order to improve the erroneous correction rate, a method of limiting the correction capability while applying the redundancy is applied. That is, after the error correction calculation of the correction limit is performed, the following or the following limit is applied to the result.

A burst length limit is set for the correction limit burst length.

A correction burst number limit is set for the correction limit burst number.

If the value exceeds this set value, it is determined that it cannot be corrected. By limiting the correction range (correction capability) with these methods, the target erroneous correction rate can be satisfied.

[0012]

The number of burst errors occurring in a code and the pattern thereof are different from each other. Nevertheless, conventionally, the correctable burst length setting is fixed. Therefore, the error correction capability is unnecessarily degraded depending on the error generation pattern.

It is an object of the present invention to provide a method and apparatus for flexibly giving an optimum error correction range limitation corresponding to various actual error patterns.

[0014]

According to the present invention, the number of burst errors that are actually occurring is investigated after the error correction calculation by the symbol, and the correction range is limited based on the examination result. Alternatively, the number of burst errors that have occurred is counted in parallel with the execution of the error correction operation using symbols, and after the error correction operation using symbols is completed, the error correction range is optimized based on the count result. To limit the correction range. As a method of limiting the error correction range, there are a method of limiting the error bit length of the burst error to be corrected and a method of limiting the error symbol length of the burst error to be corrected. These functions may be realized by either hardware or software. It may be realized by a system in which hardware and software are mixed.

By doing so, an error correction range limitation suitable for each of various error patterns can be given. Therefore, the correction capability is not deteriorated more than necessary.

The configuration of the present invention will be described in more detail below.

According to a first aspect of the present invention, in a reproducing device for a storage medium in which data obtained by adding an error correction code to target information data is recorded, data is read from the storage medium according to an instruction from a host. Reading means for performing the above, buffer means for temporarily storing the data read from the storage medium, and detection means for detecting an error occurring in the data read from the storage medium,
When an error is detected by the detection means, a correction means for correcting the error of the information data included in the data using the error correction code included in the data, and the correction means The output means for outputting the information data after being output to the outside, the correction means examines the number of burst errors occurring in the data, and in accordance with the result, an error to be corrected. Is provided for changing the maximum length of the playback device.

It is preferable that the maximum length of the error to be corrected is changed in bit units or symbol units.

It is preferable that the correction means treats errors existing within consecutive i symbols as one burst error to perform the correction.
In this case, the correction means investigates the number of errors for each interleave, and determines the maximum number of burst errors to be corrected in the unit for determining whether or not to correct the maximum error of the investigation result. More preferably, it is changed according to.

The error correction code is preferably a Reed-Solomon code or BCH code.

According to a second aspect of the present invention, in a recording / reproducing apparatus of a storage medium in which data obtained by adding an error correction code to target information data is recorded, the data is recorded from the storage medium in accordance with a command from a host. Reading means for reading, buffer means for temporarily storing the data read from the storage medium, detection means for detecting an error occurring in the data read from the storage medium, and error detection by the detection means If the error correction code included in the data is used, the correction means for correcting the error of the information data included in the data and the information data after being corrected by the correction means are used. , Output means for outputting to the outside, and adding an error correction code to the information data instructed to be written by the host E
A CC generating means and a writing means for writing data created by adding an error correction code to the information data by the ECC generating means to the storage medium, wherein the correcting means includes a burst error generated in the data. Is provided, and the maximum length of the burst error to be corrected is changed according to the result.

According to a third aspect of the present invention, in a data error correction device configured by adding an error correction code to information data, a detection means for detecting an error occurring in the data to be error-corrected. And a correction means for correcting an error of information data included in the data when an error is detected by the detection means, using an error correction code included in the data, and the correction means. Output means for outputting the information data after being corrected by the external means, the correcting means checks the number of burst errors occurring in the data, and determines whether to correct the information according to the result. The error correction device is characterized in that the maximum length of the burst error is changed.

A fourth aspect of the present invention is characterized in that the number of burst errors occurring in data is investigated, and the maximum length of error to be corrected is changed according to the result. Error correction method is provided.

[0024]

Operation: The reading means, according to the command from the host,
Data is read from the storage medium. The read data is temporarily stored in the buffer means.

The detecting means detects an error occurring in the data read from the storage medium. When an error is detected by the detection means, the correction means uses the error correction code (for example, Reed-Solomon code, BCH code) included in the data to detect the information data included in the data. Correct the error.

In this case, the correction means checks the number of burst errors occurring in the data and changes the maximum length of the error to be corrected according to the result.

The change of the maximum length can be performed in bit units or symbol units.

When the data has an interleaved structure, the correction means treats the errors existing within consecutive i symbols as one burst error and performs the above correction. In this case, the correction means investigates the number of errors for each interleave and determines the maximum number of burst errors to be corrected in the unit for determining whether or not to perform the correction according to the maximum value of the investigation result. Change.

The output means outputs the information data corrected by the correction means to the outside.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The application of the data error correction method and device according to the present invention to a magnetic disk device will be described below as a first embodiment.

FIG. 1 shows the overall construction of the magnetic disk of this embodiment. In FIG. 1, a magnetic disk 1
Reference numeral 0 denotes a disk type storage medium in which data is recorded or reproduced by the magnetic head 11 and is housed in the housing.
The magnetic head 11 is connected to an encoder / decoder 13 via a read / write control circuit 12. Also,
The magnetic disk 10 and the magnetic head 11 are controlled in rotation and position by the output signal of the servo control circuit 14. The servo control circuit 14 sends and receives bidirectional signals to and from a central processing unit (CPU) 15,
The magnetic disk 10 and the magnetic head 11 are controlled according to an instruction from the PU 15.

This CPU 15, encoder / decoder 1
3 and the data buffer 16 are connected to a hard disk controller (HDC) 17, respectively.

The HDC 17 is a part for controlling the overall recording and reading of data on the magnetic disk 10. In this embodiment, the HDC 17 is composed of an integrated circuit (IC).

The HDC 17 includes a buffer controller 18
And a CPU input / output control unit 19, a drive control unit 20, a host interface control unit 25, and the like.

The buffer controller 18 has a bidirectional bus 27.
It is connected to the data buffer 16 via. CPU
The input / output control unit 19 controls input / output with the CPU 15. Host interface control unit 25
Are connected to a host (not shown) via the host interface 26. The drive control unit 20 is for adding ECC to data, error correction, and the like.

By operating these circuits, the reliability of data recording and reproduction can be improved. That is,
When recording data on the magnetic disk 10, the drive control unit 20 attaches an ECC to the data from the host so that the data is efficiently recorded on the magnetic disk 10. When the data recorded on the magnetic disk 10 is reproduced, the drive control unit 20 performs error correction using ECC, so that highly reliable data transfer to the host is possible.

This HDC 17 (in particular, the drive control unit 2
0) is a part that constitutes an essential part of this embodiment, and will be described in more detail later.

Next, the error correction coding in this embodiment will be described.

FIG. 2 shows the configuration of the code adopted in this embodiment for one sector data. One sector data of 512 bytes is represented by a Reed-Solomon code of Galois field GF (2 ^ 8) in a structure of 3 interleaves. The maximum code length that can be obtained by the Reed-Solomon code of the Galois field GF (2 ^ 8) is 255 bytes. However, in this embodiment, the maximum code length including the redundant part is set to 765 bytes by adopting the three-stage interleaved structure. Thereby, the data of one sector (512 bytes) can be encoded.

Further, by adding a 6-byte redundant section 202 for each interleave to the 512-byte data section 201, a maximum of 3 burst errors (however, the burst length is 3 symbols or less in succession per sector). It has a correction ability.

Table 1 shows the relationship between the number of burst errors to be corrected, the burst length and the error correction rate under the conditions.

[0042]

[Table 1]

Here, it is assumed that the error correction rate is 10-18 or less. The specific value of the erroneous correction rate is assumed in consideration of the set value of the erroneous correction rate in the conventional magnetic disk.

Assuming such specifications, as shown in Table 1, when the number of corrected bursts is 3 and the burst length limit is 3 symbols, this specification is not satisfied. Therefore, if the symbol limit for burst error is fixed, one of the following specifications 1 and 2 must be selected.

Specification 1: Corrected only when the length of one burst error (burst length) is 2 symbols or less in succession and the number of burst errors generated is 3 or less.

Specification 2: Corrected only when the length of one burst error (burst length) is 3 symbols or less in succession and the number of burst errors generated is 2 or less.

However, in the present invention, the error correction rate is suppressed by flexibly changing the burst error limit without sacrificing the correction capability originally possessed by the code. That is, in the present invention, the actual number of burst error occurrences is investigated, and the limit is changed according to the number of occurrences.

When the number of burst errors generated is two or less, the error is corrected when the length of one burst error is three consecutive symbols or less.

When the number of burst errors generated is 3, correction is performed only when the length of one burst error is two consecutive symbols or less. If even one burst error with a length exceeding 2 symbols is included, it cannot be corrected.

Next, how the drive control unit 20 of this embodiment realizes the error correction taking into account the error correction limitation of the above-mentioned specifications will be described with reference to FIGS. 3, 4, and 5. .

The drive control unit 20 internally has an ECC detection circuit 21, an ECC correction circuit 22, and an ECC generation circuit 2.
3, the sequencer 24 is provided.

The ECC detection circuit 21 calculates the error syndrome of data. The ECC detection circuit 21 transfers the obtained error syndrome to the error position / error pattern calculation circuit 302 through the data bus 301.

The ECC correction circuit 22 includes an error position / error pattern calculation circuit 302, an error position register 303, an error pattern register 304, a buffer data correction circuit 306, an uncorrectable determination circuit 311, and
Consists of

The error position and error pattern calculation circuit 302 is for obtaining an error position and an error pattern for the input data. In this embodiment, a circuit using the Peterson method algorithm is adopted. There is. This circuit sequentially evaluates whether the error position is an error position from the first symbol position of the received word to the last symbol position one symbol at a time. For the position determined to be the error position, the position and the error pattern are It is designed to output each time. In this embodiment, the position of the symbol evaluated as the error position is stored in the error position register 3 via the data bus 305.
03 is stored. At the same time, the three symbols following the error position are treated as one burst error, and the error patterns for the three symbols are stored in the error pattern register 304 via the data bus 307.

The "error pattern" is a bit string pattern for 1 byte (1 symbol) in which an error bit is represented by 1 in each bit of the error symbol. However, when the error syndromes are all 0, it is assumed that no error has occurred in that sector and no error correction calculation is performed.

Details of the operating principle of a circuit using the Peterson algorithm are disclosed in US Pat. Nos. 4,494,234 and 4,504,948 as a multibyte error correction system. There is.

The error position register 303 is constructed so as to be able to store error positions for three places. The error pattern register 304 is configured to be able to store error patterns of burst errors having a burst length of 3 symbols or less for three burst errors. Error pattern register 3
The specific configuration of 04 is also related to the configuration of the uncorrectable circuit 311 described later. Therefore, the error pattern register 30
4 will be described later together with the uncorrectable circuit 311 with reference to FIG.

Note that the capacity of both registers 303 and 304 is set to three (three places), which is determined according to the correction capability of the correction code adopted in this embodiment.

The buffer data correction circuit 306 is for correcting an error in the received data stored in the data buffer 16. Information about error positions and error patterns necessary for correction (that is, the contents of the error position register 303 and the error pattern register 304) is transmitted to the buffer data correction circuit 306 through the data bus 308 and the data bus 309. Has been done.

The uncorrectable determination circuit 311 is to limit the correction range on the basis of the contents of the error pattern register 304 and evaluate correctable / uncorrectable. The uncorrectable determination circuit 311 is configured to acquire the contents of the error pattern register 304 via the bus 320. Details of the uncorrectable determination circuit 311 will be described later with reference to FIG.

The ECC generating circuit 23 in FIG. 1 is for generating an ECC to be added to the data. The sequencer 24 controls each part of the drive control section 20 and instructs each of the above parts to operate.

The error correction operation in the drive controller 20 will be described with reference to FIGS. 3 and 4.

In this embodiment, the error position / error pattern calculation circuit 302 calculates the error information for three burst errors for the time being, and stores the information in the error position register 303 and the error pattern register 304. Thereafter, the uncorrectable determination circuit 311 limits the correction range and determines whether or not the correction is actually performed. Hereinafter, each step will be described.

The received word from the disk is the data bus 6
2. Transferred to the buffer 16 via the buffer controller 18 and the data bus 27.

At this time, the ECC detection circuit 21 calculates the error syndrome for this data. And
The obtained error syndrome is transferred to the error position and error pattern calculation circuit 302 through the data bus 301.

The error position / error pattern calculation circuit 302 evaluates, from the first symbol of the sector data to be subjected to error correction, one symbol at a time to determine whether or not the error position exists (steps 401 to 406).

That is, the error position and error pattern calculation circuit 302 makes an error determination at the current symbol position (steps 401 and 402). Step 4
If it is determined that the error position is not the error position in 02, the error position and error pattern calculation circuit 302 determines the position of the symbol to be determined (error determination symbol position).
Is shifted by 1 (step 405).

On the other hand, when it is determined in step 402 that the error determination symbol position at that time is the error position, the error position and error pattern calculation circuit 3
02 then calculates the position of the error symbol and the error pattern using the error syndrome. Then, the position of the symbol evaluated as the error position is stored in the error position register 303 through the data bus 305. Further, three symbols from the error position are regarded as one burst error, and the error pattern of the burst error is stored in the error pattern register 304 through the data bus 307 (step 403). Then, the error position and error pattern calculation circuit 302 determines the position of the symbol to be judged (error judgment symbol position) by 3
Shift (step 404).

Here, of the three symbols forming each burst error, an error always occurs in the first symbol. However, the remaining two symbols are not always in error. [00000000] is stored as an error pattern in the register corresponding to the symbol in which no error has occurred in each burst error.

After step 404 (or 405), it is determined whether the error determination symbol position exceeds the last symbol of the sector (step 406). If it does not exceed, the process returns to step 402 and the same determination process is repeated.

If it is determined in step 406 that the final symbol is exceeded, that is, if the error position determination has been completed up to the final symbol, the uncorrectable determination circuit 311 is used.
Uses the error pattern stored in the error pattern register 304 to determine whether or not the burst error found at this time is uncorrectable (step 40).
7-step 410).

That is, the uncorrectable determination circuit 311 examines the number of burst errors generated and each burst length in symbol units (step 407). Then, based on the investigation result, the number of occurrences of burst error is 2
It is determined whether the number is less than or equal to the number (step 408). Further, it is determined whether or not all burst error lengths are 2 symbols or less (step 410). As a result, when the number of burst errors generated is more than two and one burst error has a length exceeding 2 symbols, the uncorrectable determination circuit 311 determines that the error cannot be corrected, and the abnormal termination is performed. It is determined to do so (step 412).

On the other hand, if the number of burst errors generated is 2 or less, the number of burst errors generated is 2 or less.
If the length of the burst error is two symbols or less even if the number is more than the number, the uncorrectability determination circuit 311 causes the buffer data correction circuit 306 to correct the burst error (step 411). The buffer data correction circuit 306 performs the correction as follows.

The buffer data correction circuit 306 reads out the contents of the error position from the received data stored in the data buffer 16 so as to read out the data bus 31.
2 to the buffer control unit 18. Upon receiving this request, the buffer control unit 18 reads out the requested content from the data buffer 16 via the data bus 27. Then, the read data is transmitted to the buffer data correction circuit 306 through the data bus 312. The buffer correction circuit 306 corrects an erroneous data pattern into a normal data pattern by taking the EOR of the error pattern and the data pattern including an error corresponding to the position. Then, the corrected data is transferred to the data bus 312, the buffer controller 18 and the data bus 27.
Through the data buffer 16. This is 1
Correction of sectors is completed.

Next, the details of the uncorrectable determination circuit 311 and the error pattern register 304 described above will be described with reference to FIG.

To hold error patterns for one burst (three consecutive symbols) for three locations, 9 (= 3 symbols x
(3 places) A byte is required. Therefore, the error pattern register 304 has nine registers 501, 502, 503, 504, 50 each having a capacity of 1 byte.
5, 506, 507, 508, 509.

The registers 501, 502, 503 are for storing the error pattern of the burst error found first. The error patterns are configured to be stored in order from the front. Therefore, the error pattern of the first symbol of the burst error is stored in the register 501, the error pattern of the second symbol is stored in the register 502, and the error pattern of the third symbol is stored in the register 503. ing.

Similarly, the registers 504, 505, 506
Is for storing the error pattern of the second discovered burst error. Registers 507 and 50
Reference numeral 8,509 is for storing the error pattern of the third found burst error. The same applies to the storage order for each symbol.

The content of the register in which no error is found and the error pattern is not stored is always 0.

The uncorrectable judgment circuit 311 judges whether or not the above correction is possible by performing a logical operation on a predetermined portion of the contents stored in the error pattern register 304. There is. Specifically, the uncorrectable circuit 311 includes a logic element (OR) 51.
3, logic element (OR) 516, logic element (AND) 51
Consists of nine.

The logic element (OR) 513 is the register 50.
The contents of 3, 506 and 509 (that is, the error pattern of the third symbol of the symbols forming each burst error) are ORed. Therefore, based on the output of the logic element (OR) 513, it is possible to know whether or not even one burst error having a length of 3 symbols or more has occurred. If even one burst error with a length of 3 symbols or more has occurred, a logical element (OR)
513 outputs “true” to the data bus 514.

The logic element (OR) 516 takes the OR of the bits of the contents of the register 507. When only two burst errors have occurred, the content of the register 507 is [00000000]. Therefore, based on the output of this logic element (OR) 516,
It is possible to know whether or not three burst errors have occurred. When three or more burst errors occur, the logic element (O
R) 516 outputs “true” to the data bus 517.

The logic element (AND) 519 is the AN of the output of the logic element 513 and the output of the logic element 516.
I am taking D. Therefore, it is determined whether or not three or more burst errors have occurred and at least one burst error having a length of 3 symbols or more has occurred.
It is known based on the output of 519. When three or more burst errors occur and at least one burst error having a length of three symbols or more occurs, a logical element (AND)
519 outputs “true” to the data bus 518.

As described above, the uncorrectable circuit 311 of the present embodiment shown in FIG. 5 can judge whether the error can be corrected or not only by the contents of the error pattern register 304.

In this embodiment, the Reed-Solomon code is used as the error correction code, but other code (for example, BCH code) may be used.

The "reading means" and "writing means" referred to in the claims refer to the magnetic head 11, the read / write control circuit 12, the encoder / decoder 13, the servo control circuit 14, the CPU 15 and the like in this embodiment. It is equivalent.

The "buffer means" means the data buffer 1
This corresponds to 6. The “detection means” corresponds to the drive control unit 20 (in particular, the ECC detection circuit 21, the error position and error pattern calculation circuit 302. The “correction means” means the ECC correction circuit 22 (uncorrectable determination circuit). 311, buffer data correction circuit 306, error position register 303, error pattern register 30
It corresponds to 4). The output means corresponds to the buffer controller 18, the host interface controller 25, the data bus, and the like. However, the above-mentioned units operate in close cooperation with each other, and the correspondence relationship described here is not strict.

Next, a second embodiment of the present invention will be described.

In the second embodiment, the drive control unit 20
The configuration of (in particular, the ECC correction circuit 22) is different from that of the first embodiment described above. Other points, for example, the entire configuration (see FIG. 1) and the ECC specifications are the same as those in the first embodiment. Therefore, in the following, the ECC correction circuit 2
Only 0 will be described.

ECC correction circuit 2 in the second embodiment
The configuration of No. 2 is shown in FIG.

The ECC correction circuit 22 includes an error position / error pattern calculation circuit 615, a buffer data correction circuit 611, and an uncorrectable determination circuit 608. Also, buses 603, 610 that connect these to each other,
614 is provided.

The error position / error pattern calculation circuit 615 is for obtaining the error position and its error pattern. Error position and error pattern calculation circuit 6
The reference numeral 15 outputs the error determination result at that time to the uncorrectable determination circuit 608 through the control line 603. The output is "true" when the symbol position that is the object of error determination at that time is an error position, and vice versa.
If it is not the error position, "false" is output. In addition to this, the error position and error pattern calculation circuit 615 uses the obtained error position as the data bus 61.
4 to the buffer data correction circuit 611. Similarly, the obtained error pattern is output to the buffer data correction circuit 611 through the data bus 610.

The buffer data correction circuit 611 corrects the error in the data in the buffer. In particular, the buffer data correction circuit 611 of the present embodiment is adapted to perform the error correction on a symbol-by-symbol basis as soon as an error is detected by the error position and error pattern calculation circuit 615.

The uncorrectable decision circuit 608 makes an uncorrectable decision based on the number of burst errors and the length of the burst errors. The uncorrectable determination circuit 608 includes a burst error number counter 602 and a 3-symbol burst error flag 601 in order to obtain information necessary for the determination.

The uncorrectable determination circuit 608 of this embodiment is configured to make the uncorrectable determination as needed. Then, as a result, when it is determined that the correction is not possible, it is configured to determine that the abnormal end should occur at that time. It should be noted that, if the uncorrectable determination circuit 608 does not determine that it is uncorrectable, and if it is determined whether or not it is an error position up to the last symbol and error correction is performed, it is configured to end normally. The uncorrectability determination circuit 608 will be described later in detail with reference to FIG.

Next, the operation of the error correction impossible / possible judgment by the ECC correction circuit 22 will be described with reference to FIG.

The error position and error pattern operation circuit 615 evaluates whether the error position is one symbol at a time from the first symbol of the sector data to be error-corrected. The error position and error pattern calculation circuit 615 makes an error judgment at the symbol position that is the judgment target at that time (steps 701 and 70).
2). As a result, if it is not the error position, the position of the symbol to be judged (hereinafter referred to as "error judgment symbol position") is shifted by 1 (step 703). Then, it is determined whether or not the error determination symbol position exceeds the last symbol of the received word (step 704). If the number of symbols exceeds the final symbol, it is determined that the correction of symbols in all one sector is completed, and the process ends normally (step 7).
11). If it does not exceed the final symbol, the process returns to step 702 to repeat the error position determination.

If it is determined in step 702 that the position is the error position, the error position and error pattern calculation circuit 615 sets the error determination symbol position at that time as the error occurrence position and calculates the error pattern. Then, the detected error position and its error pattern are transmitted to the buffer data correction circuit 611 (step 705).

Then, the buffer data correction circuit 611.
Of the received data stored in the data buffer 16, the error symbol data corresponding to the error found at this time is immediately corrected on the spot using the error pattern (step 706). The burst error number counter 602 of the uncorrectable determination circuit 608 counts the number of burst errors by referring to the error position and the error determination result for each symbol obtained by the error pattern calculation circuit 615 (step 7).
07).

Further, the uncorrectable judgment circuit 608 investigates the length of the burst error and judges whether or not the length exceeds 2 symbols (step 708). As a result, when the length of the burst error exceeds 2 symbols, the 3-symbol burst error flag 6
01 is set to 1 (true) (step 709). After this,
Go to step 710.

If the number of symbols does not exceed 2 in step 708, the process directly proceeds to step 710.

In step 710, the uncorrectable decision circuit 608 determines whether or not the burst error exceeds the error limit range based on the information of the burst error number counter 602 and the 3-symbol burst error flag 601 (here The number of burst errors exceeds 2, and the 3-symbol burst error flag 601 = 1
Is determined) (step 710).
As a result, if the error limit range is exceeded (here, the number of burst errors exceeds 2 and the 3 symbol burst error flag 601 = 1), the uncorrectable determination circuit 608 corrects the error. If it is impossible, it is determined to be abnormally terminated (step 712).

On the other hand, when the error limit range is not exceeded, the buffer data correction circuit 611 corrects the burst error (step 713) and step 703.
Return to

Next, details of the uncorrectable determination circuit 608 will be described with reference to FIG.

The uncorrectable determination circuit 608 includes a three-stage shift register 806, a logic element (AND) 812, a logic element (AND) 815, and a logic element (AND) 816.
, Logic element 817, and burst error number counter 6
02, 3 symbol burst error flag 601,
It has.

The burst error number counter 602 indicates 2
The counter is a bit register (see FIG. 9).

3-symbol burst error flag 601
Is set in the memory provided in the uncorrectable determination circuit 608. The 3-symbol burst error flag 601 = 1 indicates that the burst error corresponding to the information currently stored in the shift register 806 has a length of 3
Means that it is a symbol. The 3-symbol burst error flag 601 = 0 means that the length of the burst error is not 3 symbols.

If the error position and error pattern calculation circuit 615 has an error in the symbol at the position being judged at that time, the error position and error pattern calculation circuit 615 outputs the data through the data bus 603.
“True” is output to the three-stage shift register 806. Each stage of the shift register 806 is a 1-bit register. The shift of the three-stage shift register 806 is synchronized with the error position and the clock of the error pattern calculation circuit 615. Therefore, among the registers of the shift register 806, the leftmost register stores the symbol error determination result of the symbol at that time. Further, the error determination result of one symbol before is stored in the center register. The rightmost register stores the error determination result two symbols before.

However, when 1 is shifted to the rightmost register of the shift register 806, the value of the shift register 806 is automatically cleared.

Counting the number of burst errors and investigating the length of a burst error are performed as follows with one burst error length being a maximum of 3 symbols.

The number of burst errors depends on the logic element 81.
7, a logical element (AND) 815, and a burst error number counter 602. The principle of the counting is as follows.

Consider a case in which the error determination symbol position at that time is determined to be the error position as a result of the error determination, and no error has occurred 1 symbol before and 2 symbols before. In this case, the content of the shift register 806 is [100] from the left. Therefore, as is clear from the circuit configuration of FIG.
Outputs “true” to the data bus 605. A state in which no error has occurred in the preceding two symbols assumed here (the shift register 806 [10
0] state) means that the error newly found at that time is located at the beginning of the burst error. Therefore, the burst error number counter 602 can count the number of burst errors by counting the number of times the logic element (AND) 815 outputs “true”.

If an error is found one symbol before or two symbols before, the logic element (A
ND) 815 outputs "false". In this case,
The burst error number counter 602 does not count.

A check of the length of the burst error is performed by a logic element (AND) 816 and a 3-symbol burst error flag 601. The principle of the investigation will be described below.

As a result of the error determination, consider a case where the error-determined symbol position at that time is determined to be an error position and an error occurs two symbols before. It is assumed that the error two symbols before does not belong to another burst error. In this case, the contents of the shift register 806 are [111] or [101] from the left. Therefore, the logic element (AND) 816 outputs “true” to the data bus 604. In other states, the logic element (AND) 816 outputs "false".

By the way, the state where the register 806 is [111] or [101] means that the length of the burst error found at that time is 3 symbols. Therefore, when “true” is output to the data bus 604, the uncorrectable determination circuit 608 sets the 3-symbol burst error flag 601 to 1. On the other hand, when “false” is output to the data bus 604, the uncorrectable determination circuit 608 determines that the 3-symbol burst error flag 6
01 is set to 0.

The final judgment as to whether correction is impossible is
The logic element (AND) 812 performs this. The logic element (AN
D) The principle of determination by 812 will be described with reference to FIG.

When the number of found burst errors is 0, the value of the burst error number counter 602 is [0
0]. When the number of discovered burst errors is 1, the value of the burst error number counter 602 is [0
1]. Similarly, when the number is 2, the number is [10], and when the number is 3, the number is [11].

When the value of the burst error number counter 602 is [11] and the value of the 3-symbol error flag 601 is 1 (that is, 3 burst errors are found, and at least one of them has a length of 3 symbols) cannot be corrected, and in this case, the logic element (AND) 812 is “true” on the data bus 813.
Is output.

As described above, the uncorrectable judgment circuit 608 can make the uncorrectable judgment at any time using only the error judgment result 801.

In the second embodiment, as soon as the error position is determined, the data in the buffer is corrected as needed. Therefore, it is not necessary to store a plurality of error patterns and error positions, and there is an advantage that the register that stores the error positions and error patterns can be omitted.

Next, a third embodiment of the present invention will be described.

The third embodiment is characterized in that the length of burst error is limited in bit units. In the first and second embodiments described above, the length of burst error is limited in symbol units.

The ECC structure is the same as in the first and second embodiments. Table 2 shows the relationship between the number of burst errors, the limited number of bits, and the erroneous correction rate when the bit error is limited in the burst error correction using this code.

[0125]

[Table 2]

Here, it is assumed that the specification requires that three burst errors having a length of 17 bits or less can be corrected.

The error correction rate in the case of correcting three burst errors each having a maximum length of 17 bits is 1.6 × 10 ^ -19.
It can be seen from Table 2 that Therefore, in other cases as well, the error correction rate may be 1.6 × 10 19 or less.

Therefore, in this embodiment, when three burst errors occur, the correction is performed only when the length of each burst error is 17 bits or less. When only one or two burst errors occur, the length of each burst error is not limited.

The ECC correction circuit 22 in this embodiment is
Basically, it is the same as the first embodiment (FIG. 3). However,
The uncorrectability determination circuit 311 has a different configuration from that of the first embodiment.

First, the outline of the error correction operation by the ECC correction circuit 22 will be described with reference to FIG. The detailed configuration and operation of the uncorrectability determination circuit 311 will be described later with reference to FIGS. 11 and 12. The process of FIG. 10 is almost the same as the process of FIG. 4 (first embodiment), except that the length of the burst error is limited in bit units of 17 bits (see step 910). ).

For the time being, the error position / error pattern calculation circuit 302 calculates error information for three burst errors, and outputs that information to the error position register 303,
Stored in the error pattern register 304. After that, the uncorrectable determination circuit 311 gives a correction range limitation and determines whether or not the correction is actually performed. Hereinafter, each step will be described.

The received word from the disk is the data bus 6
2. Transferred to the data buffer 16 via the buffer controller 18 and the data bus 27.

At this time, the ECC detection circuit 21 calculates the error syndrome for this data. And
The obtained error syndrome is transferred to the error position and error pattern calculation circuit 302 through the data bus 301.

The error position and error pattern calculation circuit 302 evaluates, one symbol at a time, whether or not it is an error position from the first symbol of the sector data to be subjected to error correction (steps 901 to 906).

That is, the error position / error pattern calculation circuit 302 makes an error determination at the current symbol position (steps 901 and 902). Step 90
When it is determined that the position is not the error position in 2, the error position and error pattern calculation circuit 302 shifts the position of the symbol to be determined (error determination symbol position) by 1 (step 905).

On the other hand, when it is determined in step 902 that the error determination symbol position at that time is the error position, the error position and error pattern calculation circuit 3
02 then calculates the position of the error symbol and the error pattern using the error syndrome. Then, the position of the symbol evaluated as the error position is stored in the error position register 303 through the data bus 305. Further, 3 symbols from the error position are treated as one burst error, and the error pattern of the burst error is stored in the error pattern register 304 through the data bus 307 (step 903). Then, the error position and error pattern calculation circuit 302
Shifts the position of the symbol to be judged (error judgment symbol position) by 3 (step 904).

Here, of the three symbols forming each burst error, an error always occurs in the first symbol. However, the remaining two symbols are not always in error. [00000000] is stored in the register as an error pattern for a symbol in which no error has occurred in each burst error.

After step 904 (or 905), it is determined whether or not the error determination symbol position exceeds the last symbol of the sector (step 906). If not exceeded, the process returns to step 902 and the same determination process is repeated.

If the final symbol is exceeded in step 906, that is, if the error position determination has been completed up to the final symbol, the uncorrectability determination circuit 31.
1 uses the error pattern stored in the error pattern register 304 to determine whether or not the error cannot be corrected (steps 907 to 910).

That is, the uncorrectable determination circuit 311 checks the number of burst errors generated (step 90).
7). Then, based on the investigation result, it is determined whether or not the number of burst errors generated is 2 or less (step 908). Also, the length of the burst error is checked (step 909), and the length of all burst errors is 1
It is determined whether the number of bits is 7 bits or less (step 91).
0). As a result, when the number of burst errors generated is more than two and one burst error exceeds 17 bits in length, the uncorrectability determination circuit 311 is also included.
Determines that it cannot be corrected, and determines to terminate abnormally (step 912).

On the other hand, when the number of burst errors generated is 2 or less, the number of burst errors generated is 2 or less.
If the length of the burst error is 17 bits or more even if the number is more than the number, the uncorrectable determination circuit 311 causes the buffer data correction circuit 306 to correct the burst error (step 911). The correction by the buffer data correction circuit 306 is performed in the same manner as in the first embodiment.

Next, details of the error pattern register 304 and the uncorrectable determination circuit 311 in the third embodiment will be described with reference to FIGS. 11 and 12.

The uncorrectability determination circuit 311 of this embodiment is the first
Unlike the above embodiment, the error correction range is limited by examining and referring to the length of each burst error in bit units.

To hold an error pattern for one burst (three consecutive symbols) for three locations, 9 (= 3 symbols x
(3 places) A byte is required. Therefore, the error pattern register 304 includes nine registers 501, 502, 503, 504, 505, 50 each having 1 byte.
6, 507, 508, 509.

The registers 501, 502 and 503 are for storing the error pattern of the burst error found first. The error patterns are configured to be stored in order from the front. Therefore, the error pattern of the first symbol of the burst error is stored in the register 501, the error pattern of the second symbol is stored in the register 502, and the error pattern of the third symbol is stored in the register 503. ing.

Similarly, the registers 504, 505, 506
Is for storing the error pattern of the second discovered burst error. Registers 507 and 50
Reference numeral 8,509 is for storing the error pattern of the third found burst error.

The content of the register in which no error is found and the error pattern is not stored is always 0.

The uncorrectable determination circuit 311 determines whether or not the correction is impossible by performing a logical operation on a predetermined portion of the contents stored in the error pattern register 304. Specifically, the uncorrectable circuit 311 is provided with an error bit length check circuit 959,
966, 967, a logic element (OR) 961, a logic element (AND) 963, and a logic element (OR) 970. It also has a bus that connects them to each other.

Error bit length checking circuits 959, 966
967 checks whether the bit length of each burst error exceeds 17 bits. Then, as a result of the investigation, when the error bit length of each burst error exceeds 17 bits, the data buses 960, 965, 968 respectively.
"True" is output to. Error bit check circuit 959, 9
Details of 66 and 967 will be described later with reference to FIG.

The logic element (OR) 961 takes the OR of the outputs of the error bit checking circuits 959, 966 and 967. Therefore, the error bit check circuits 959, 966 and
If any one of the outputs of 967 is “true” (that is, if at least one error bit length of the three burst error patterns exceeds 17 bits), the logic element (OR ) 961 outputs "true" to the data bus 962.

The logic element (OR) 970 is the register 50.
The content of each bit in 7 is ORed. As described above, the contents of the register 507 are [0000000
0] only when the third burst error has not been found. Therefore, when the third burst error has occurred, the logic element (OR) 970 outputs “true” to the data bus 969.

The final judgment as to whether or not correction is impossible is
The logic element (AND) 963 performs this.

Logic element (AND) 963 makes this determination by ANDing the output of logic element (OR) 961 and the output of logic element (OR) 970.

As a result, when both outputs are "true" (that is, three burst errors occur and the bit length of at least one burst error is 17).
If it exceeds the bit), the logical element (AND) 9
The 63 outputs “true” to the data bus 964. The output of "true" to the data bus 964 means uncorrectable, and the abnormal end is determined based on the output.

In this way, the uncorrectability determination circuit 3 of this embodiment is used.
11 is characterized in that the error range is limited by the bit length.

Details of the error bit length checking circuit 959 will be described with reference to FIG. The internal configurations and operations of the error bit length checking circuits 966 and 967 are the same as those of the error bit length checking circuit 959.

As can be seen from FIG. 12, the logic element (AN
D) 981, 982, 983, 984, 985, 98
6, 987 and the like are ORed for all the combinations of each bit of the register 501 (first symbol) and each bit of the register 503 (third symbol) in which the interval between both bits exceeds 17 bits. It is designed to take If there are one or more sets of error bits at intervals exceeding 17 bits, the logic element (OR) 9
88 outputs “true” to the control line 960. The output of "true" to the control line 960 means that the error bit length exceeds 17 bits.

As described above, according to the present invention, the original correction ability of the error correction code can be utilized while preventing the error correction by changing the error correction limitation according to the error occurrence situation.

In the embodiment described above, the ECC correction circuit 22
Was realized by hardware. However, in order to reduce the circuit scale, it is possible to realize the whole or part by software.

The effect of the present invention is strongly influenced by the number of burst errors and the length of burst errors occurring in one sector. The appearance tendency of the error is the recording method on the medium,
It depends on the reading method, the signal processing circuit, the transfer path, and the like. Therefore, as an example, the effect of the invention in this embodiment when the error occurrence tendency is assumed as follows will be described.

Since the bit error rate in the storage medium deteriorates as the recording density increases, it can be predicted that the burst error length (burst error bit length) will increase. Therefore, here, it is assumed that the ratio of occurrence of three burst errors (one burst is the longest consecutive 3 symbols) among the errors occurring in one sector is 10%. Furthermore, it is assumed that 80% of the individual burst errors have an error length of 2 symbols or less. In such a case, three burst errors occur in one sector, and the probability that all the error lengths are within 2 symbols is 0.1 × (8/10) ^ 3 = 0.05.
1 (about 5.1%). Therefore, under the conditions assumed here, by correcting 3 burst errors with a burst error length of up to 2 symbols as in the above embodiment,
The error correction capability can be improved by about 5.1%.

[0162]

As described above, according to the present invention, by considering the actual number of burst error occurrences, in each error correction, an optimum limit is given as compared with the conventional one so as not to reduce the correction capability as much as possible. be able to. As a result, the correction capability can be improved as a whole and the reliability of data transfer can be improved while the setting error correction rate is still satisfied, as compared with the conventional case.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a first embodiment of the present invention.

FIG. 2 is a code configuration diagram of data in the first embodiment.

3 is a block diagram showing an internal configuration and the like of a drive control unit 20. FIG.

FIG. 4 is a flowchart showing an error correction process.

5 is a diagram showing configurations of an uncorrectable determination circuit 311 and an error pattern register 304. FIG.

FIG. 6 is a block diagram showing an internal configuration and the like of a drive control unit 20 according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing an error correction process in the second embodiment.

FIG. 8 is an uncorrectable determination circuit 608 according to the second embodiment.
It is a figure which shows the internal structure of FIG.

FIG. 9 is a configuration diagram of a main part of an uncorrectable determination circuit 608.

FIG. 10 is a flowchart showing an error correction process in the third embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration of an uncorrectable determination circuit according to a third embodiment.

FIG. 12 is a diagram showing a configuration of an error bit length check circuit.

FIG. 13 is a diagram showing a principle of occurrence of erroneous correction.

[Explanation of symbols]

Reference numeral 17 ... Hard disk controller, 20 ... Drive controller, 21 ... ECC detection circuit, 22 ... ECC correction circuit,
18 ... Buffer control unit, 16 ... Data buffer, 302
... Error position and error pattern calculation circuit, 303 ...
Error position register, 304 ... Error pattern register, 306, 611 ... Buffer correction circuit, 311, 60
8 ... Uncorrectable determination circuit, 602 ... Burst error number counter, 601 ... 3 symbol burst error flag,
959 ... Error bit length check circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shoichi Miyazawa 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Inside the Hitachi, Ltd. Systems Development Laboratory (72) Inventor Masatoshi Nishina 2880, Kozu, Odawara, Kanagawa Stock Company Hitachi Storage Systems Division (72) Inventor Katsumi Yamamoto 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo Hitachi Ltd. Semiconductor Division

Claims (8)

[Claims] 1. A reproducing device for a storage medium in which data obtained by adding an error correction code to target information data is recorded, and a reading means for reading data from the storage medium according to an instruction from a host; Buffer means for temporarily storing the data read from the medium, detection means for detecting an error occurring in the data read from the storage medium, and when an error is detected by the detection means, Correcting means for correcting an error of information data included in the data using an error correction code included in the data, and output means for outputting the information data corrected by the correcting means to the outside. And the correction means investigates the number of burst errors occurring in the data, and determines the target of correction according to the result. It is to change the maximum length of errors that, the reproducing apparatus according to claim. 2. The reproducing apparatus according to claim 1, wherein the maximum length of the error to be corrected is changed in bit units or symbol units. 3. The reproducing apparatus according to claim 1, wherein the correcting means collectively treats errors existing within consecutive i symbols as one burst error to perform the correction. . 4. The correction means examines the number of errors for each interleave, and determines the maximum number of burst errors to be corrected in a unit for determining whether or not to perform the correction. The reproducing apparatus according to claim 3, wherein the reproducing apparatus changes according to the maximum value. 5. The reproducing apparatus according to claim 1, wherein the error correcting code is a Reed Solomon code or a BCH code. 6. A recording / reproducing apparatus for a storage medium in which data in which error correction code is added to target information data is recorded, and a reading means for reading data from the storage medium according to an instruction from a host, and the storage medium. Buffer means for temporarily storing the data read from the storage medium, detection means for detecting an error occurring in the data read from the storage medium, and when the detection means detects an error, the data Correction means for correcting an error in the information data contained in the data using the error correction code included in the data, and output means for outputting the information data corrected by the correction means to the outside. , An ECC generation means for adding an error correction code to the information data instructed to be written by the host, and an ECC generation means Writing means for writing data produced by adding an error correction code to the data in the storage medium, and the correcting means investigates the number of burst errors occurring in the data and responds to the result. The recording / reproducing apparatus is characterized in that the maximum length of the burst error to be corrected is changed. 7. An error correction device for data formed by adding an error correction code to information data, and detecting means for detecting an error occurring in data to be error-corrected; If detected, the error correction code included in the data is used to correct an error in the information data included in the data, and the information data after being corrected by the correction means. And an output means for outputting to the outside, the correction means investigates the number of burst errors occurring in the data, and according to the result, determines the maximum length of the burst error to be corrected. An error correction device characterized by being changed. 8. An error correction method, comprising: checking the number of burst errors occurring in data, and changing the maximum length of the error to be corrected according to the result.