JPH09330220A - Method and system for minimizing branch penalty of processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the delay when an indirect instruction is executed by predicting the target address of the indirect branch instruction by a branching unit if the contents of a branch register can not be used yet. SOLUTION: A branch target address cache(BTAC) 54 allows the branching unit 28 to predict the target address before it is supplied with a move-to-count- register(mtctr) instruction, and subtract the calculated branch penalty of the indirect branching of a branch-to-count(brctr) instruction, etc. The branching unit 28 sends the current branch address of a branch address register 50 to the BTAC 54 when the target address depends upon the unprocessed mtctr instruction. When the brctr address matches one of the addresses stored in the BTAC 54 and its item is effective, a BTAC hit is made, and the target address of the item is read and sent to an instruction cache.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to methods and systems for improving processor performance, and more particularly to methods and systems for minimizing branch penalties associated with register dependent branch instructions.

[0002]

The instruction set of most personal computer (PC) architectures includes branch instructions. The branch instruction causes the program execution along the sequential path to become discontinuous and resumes execution at a new location in memory. This new location is called the target address of the branch.

Three types of branch instructions, relative, absolute and indirect, are used to specify the target address. The target address of the relative branch instruction is an address obtained by adding an offset to the address of the branch instruction. The target address of the absolute branch instruction is the immediate address included in the branch instruction. Indirect branch instructions are two types of register-dependent branch, namely branch-t.
Classified into o-count (branch to count) and branch-to-link (branch to link), the target address of branch-to-count is the value stored in the count register, branch-t.
The o-link target address is the value stored in the link register.

One way the count and link registers receive values is through the execution of move-to-count and move-to-link instructions. That is.
These instructions move a value, which is in the general purpose register (GPR), called an operand, into a count register or a link register. To branch to the address stored in GPR, usually move-to-count (mtct
r) instructions, followed by branch-to-count (brc
tr) execute the instruction. During the mtctr / brctr instruction sequence, the brctr instruction cannot be executed until the value of the count register resulting from the mtctr instruction is known. Such instructions are called register-dependent instructions because they cannot be executed until a particular register gets the target address of the instruction.

A read-after-write hazard exists between the mtctr and brctr instructions. A RAW hazard exists when a register is written by an instruction and then read by a later instruction. The processor needs to supply the data from the first instruction to the second instruction regardless of the order in which the two instructions are actually executed.

Dependencies between mtctr / brctr instruction sequences are problematic in pipeline architectures that try to keep hardware components up and running as much as possible by overlapping operations. To overlap operations, a typical pipeline architecture has three overlapping operations that occur during the same processor cycle: a fetch cycle that fetches an instruction from memory, a dispatch operation that sends the instruction to an execution unit. Cycles and execution cycles are included in which execution units execute instructions. The execution unit responsible for executing the branch instruction is called the branch unit.

When the branch unit cannot execute a branch because the target address cannot be obtained, the fetch cycle must be stopped (stalled) until the target address is known. Therefore, the dispatch cycle stalls in the next cycle, and the execution cycle stalls in the next cycle. Therefore, extra cycles are required to execute the mtctr instruction before it can be executed, reducing overall system performance.

The time between executing mtctr and the time the branch unit encounters the brctr instruction is defined as the calculated branch penalty. brct the mtctr instruction
By scheduling well before r, the compiler can reduce the calculated branch penalty. This is because mtctr is sent to the execution unit before the branch unit encounters brctr.
Unfortunately, due to branch dependencies, for example, mtctr
It is often the case that the compiler cannot find the instruction to schedule between a and brctr.

[0009]

Accordingly, there is a need for a system and method for minimizing delays in executing indirect branch instructions. The present invention addresses this need.

[0010]

SUMMARY OF THE INVENTION The present invention provides a system and method for minimizing branch penalties in a processor when the branch penalties are associated with a first indirect branch instruction. The system and method includes a first table for storing at least one entry containing a previous indirect branch instruction address and a previous target address. The branch unit is coupled to the first table for processing the first indirect branch instruction. The first indirect branch instruction has a specific address and causes program execution to start at a new target address. The first indirect branch instruction depends on the predecessor instruction to supply the new target address. The branch unit processes the first indirect branch instruction by comparing the address of the first indirect branch instruction with the address of the previous indirect branch instruction stored in the first table, and if they match, the previous indirect branch instruction is processed. Target address is used as the new target address, which predicts the new target address before it is supplied by the preceding instruction.

In accordance with the systems and methods disclosed herein, the present invention allows a branch unit to predict the target address of an indirect branch instruction when the contents of the branch register are not yet available. A simulation of a branch table with 8 entries showed a performance improvement of over 50% over the conventional method.

[0012]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to improving the processing of branch instructions. The following description is presented to enable any person of ordinary skill in the art to make and use the invention and is provided in connection with a patent application and its requirements. Various modifications of the preferred embodiment will be readily apparent to those skilled in the art, and the general principles herein may be applied to other embodiments. Therefore, the present invention is not limited to the illustrated embodiments, but rather should be subject to the broadest scope consistent with the principles and features disclosed herein.

Referring to FIG. 1, a processor 10 in which the present invention resides.
Is shown. The processor 10 has an instruction cache (IC).
12, instruction buffer (IB) 14, instruction address queue (IAQ) 16, second instruction address queue (CB
IAQ) 30, dispatch unit (DU) 18,
Functional units (FU) 20, 22 and 24, completion buffer (CB) 26, and branch unit (BU) 28 are included.

The processor 10 functions as follows. The instruction buffer 14 supplies the fetch address to the instruction cache 12 via the address line 32, and the instruction pointed to by the fetch address is transferred from the instruction cache 12 via the data line 34 and placed in the instruction buffer 14. At the same time, the instruction cache 12 generates the address of the instruction and sends the address to the instruction address queue 16 via the address line 36. The instruction address queue 16 is generally needed to generate branch target addresses for relative branches.

In each cycle, dispatch unit 1
8 evaluates the instruction from the instruction buffer 14 and dispatches the non-branch instruction to the functional unit 20, 22 or 24, where the instruction is queued for execution. At the same time, branch unit 28 continuously scans instruction buffer 14 for branch instructions to process. Each instruction type dispatched by dispatch unit 18 is sent to completion buffer 26 via instruction bus 38.

The completion buffer 26 stores the dispatched instructions that have not been processed in the processor 10, and
Maintain an architectural state of 0. When an instruction is dispatched by dispatch unit 18,
The address associated with that instruction is read into a second instruction address queue 30, designated CBIAQ 30, which is assigned to completion buffer 26. Completion buffer 26
Uses CBIAQ30 to save the correct address of the failing instruction.

Completion buffer 26 also controls the architected values of count register 42 and link register 44. For example, if an instruction such as a branch reaches the bottom of the completion buffer 26, then the instruction has been completely executed. The fully executed instruction is committed by the completion buffer 26, at which point the value of the architected register is updated. In this example, completion buffer 26 updates the architected count register by decrementing the value of count register 42 by one.

Branch unit 28 processes branch instructions,
The target address is supplied to the instruction cache 12 via the fetch address line 40, and the instruction cache 12 is supplied in the next cycle.
To handle the new instruction stream.

In some indirect branch instructions, count register 42 and link register 44 are used to generate the target address.
Recall that the contents of registers such as are used. For example, the brctr instruction must first cause a target address to be calculated by one of the functional units 20, 22 and 24 and then move this target address to the count register 42. The target address is then read from count register 42 and sent to instruction cache 12. For discussion purposes, we will use the brctr instruction as the primary example.

As mentioned above, the brctr instruction is register-dependent, which is until the value of the count register 42 resulting from the mtctr instruction is known.
Means the instruction cannot be executed. A processor with a deep pipeline design may experience a delay of 5 cycles or more between the start of the brctr instruction and the time when the target address becomes available.

According to the present invention, the target address of an indirect branch instruction is predicted before the target address is known by using a branch target address cache that minimizes the delay in executing an indirect branch instruction. . To more specifically illustrate the method and system for handling indirect branches according to the present invention, one of the embodiments of such a system is given.
2, which shows one of them.

FIG. 2 is a block diagram illustrating a branch unit architecture for minimizing the calculated branch penalties of indirect branch instructions. The branch unit 28 includes a branch address register 50, a branch adder 52 and a branch target address cache (BTAC) 54.

As mentioned above, the branching unit 28 is
The branch instruction is received and a target address is generated, and this target address is sent to the instruction cache 12 as the next fetch address 56. Branch instruction is dispatch unit 1
When received from 8, the address of the branch instruction is placed in branch address register 50.

If the branch instruction is a relative branch instruction or an absolute branch instruction, branch unit 28 uses branch adder 52 to generate the target address. For relative branch instructions, the target address is generated by adding the branch address and branch offset 58. In the case of an absolute branch, the target address is specified in the instruction as immediate data and the branch adder 5 is used using the branch offset 58 input.
Passed through 2.

Indirect branch instructions are processed differently than relative and absolute branch instructions. According to the present invention,
BTAC 54 reduces the calculated branch penalty for indirect branches such as brctr by allowing branch unit 28 to predict the target address before it is supplied by mtctr. BTAC54
In each item of, the address of the brctr instruction and the corresponding b
It contains the target address and valid bits last generated by rctr. Note that unlike conventional implementations, only indirect branches are placed in the BTAC.
Also, this BTAC predicts only the target address of the branch instruction, not the direction. The present invention can be extended to store multiple target addresses of a single brctr (possibly using multiple entries), such as the value of some known register or the route to this particular occurrence of a branch. , It is straightforward to use a mechanism for selecting one of the possible target addresses.

Branch unit 28 sends the current branch address of branch address register 50 to BTAC 54 when the target address depends on an outstanding mtctr instruction. The address of the indirect branch instruction is compared with the address of the BTAC 54 item. If the brctr address is BTA
If it matches one of the addresses stored in C54 and the item is valid, a BTAC hit occurs and the target address for that item is read from BTAC 54,
It is sent to the instruction cache 12 (FIG. 1).

Branch unit 28 speculatively fetches a new instruction stream when brctr actually does or is predicted to branch. When the target address becomes available in count register 42, branch unit 28 flushes or completes the speculative stream depending on whether the brctr target address was mispredicted.

If the address of brctr is not in BTAC 54 or is not valid, then a miss occurs and branch unit 28 incurs the normal calculated branch penalty.
We must wait until the execution of mtctr completes before fetching the target of brctr.

When a miss occurs in BTAC 54, branch unit 28 writes a new entry to BTAC 54 containing the address of brtr, the target address fetched and the valid bit set. In the preferred embodiment of the invention, the replacement of BTAC 54 items is done in a round-robin fashion.

The present invention is an improvement over conventional methods that use BTAC to predict target instruction addresses for relative and absolute branch instructions, but not for indirect branch instructions. Previous attempts to predict the target instruction address of an indirect branch instruction have used a combined BTAC that includes both relative branch instruction and indirect branch instruction entries. Since the prediction of the relative branch instruction is more accurate than the prediction of the indirect branch instruction, the inaccurate prediction of the indirect instruction results in the combination BT.
It was degrading the overall performance of the AC. Therefore, combination B
TAC is rarely used and most conventional methods predict only the target instruction address of relative instructions.

However, according to the present invention, the use of another BTAC 54 dedicated to indirect branch instructions allows the branch unit to predict the target address of the indirect branch instruction. By simulation of a fully associative BTAC 54 with 8 items, eg an emulator,
Performance gains of over 50% have been demonstrated for applications that make extensive use of computational branch addressing.

A method and system for minimizing the calculated branch penalty associated with indirect branch instructions has been disclosed. The invention has been described by the examples given above,
Those skilled in the art will readily appreciate that variations of this embodiment are possible and are within the spirit and scope of the invention. Therefore, one of ordinary skill in the art can make many changes without departing from the spirit and scope of the claims.

In summary, the following items are disclosed regarding the configuration of the present invention.

(1) A first table for storing at least one item containing the address of the previous indirect branch instruction and the previous target address, and a first table for processing the first indirect branch instruction. A first indirect branch instruction having a specific address and causing the program execution to start at a new target address, the first indirect branch instruction dependent on the preceding instruction to supply the new target address. Then, the branch unit processes the first indirect branch instruction by comparing the address of the first indirect branch instruction with the address of the previous indirect branch instruction stored in the first table, and if the address matches, then Target address of the first indirect branch instruction is used as a new target address before the new target address is predicted by the preceding instruction. System for branching penalty and wherein the associated, to minimize the branch penalty in processor. (2) The system according to (1) above, wherein the first table is a branch target address table, and the branch target address table includes a plurality of items. (3) The system of (2) above, wherein each of the plurality of items of the branch target address table further includes an effective bit. (4) The system according to (3) above, wherein the first indirect branch instruction is a branch-to-count instruction. (5) The system according to (4) above, wherein the preceding instruction is a move-to-count instruction. (6) The system according to (3), wherein the first indirect branch instruction is a branch-to-link instruction. (7) The system according to (6) above, wherein the preceding instruction is a move-to-link instruction. (8) (a) storing in the first table at least one item corresponding to the previous indirect branch instruction, including the address of the previous indirect branch instruction and the target address before the previous indirect branch instruction. And (b) comparing the address of the previous indirect branch instruction and the address of the first indirect branch instruction stored in the first table, and (c) the address of the first indirect branch instruction of the previous indirect branch instruction. Uses the previous target address as the new target address if it matches the address,
Predicting the new target address before it is supplied by the preceding instruction, the branch penalty being associated with the first indirect branch instruction and the first indirect branch instruction And a method for minimizing branch penalties in a processor, characterized in that program execution starts at a new target address and the first indirect branch instruction depends on a preceding instruction to supply the new target address. . (9) Step (a) further includes (a1) storing a plurality of items in the first table, and (a2) providing a valid bit in each of the plurality of items in the first table. The method of (8) above. (10) The step (c) further includes (c1) when the address of the first indirect branch instruction matches the address of the first item of the plurality of items, the first effective bit corresponding to the first item And (c2) sending a target address of the first item from the first table to the instruction cache when it is determined that a match is found. The method according to (9) above, which comprises: (11) If no match is found, step (c) further comprises: (c3) retrieving the new target address after the new target address is supplied by the preceding instruction; and (c4) the address of the first indirect branch instruction. Writing a new entry containing the fetched target address and the set valid bit into the first table. (12) Dispatch for dispatching instructions
A unit and a branch unit coupled to the dispatch unit for executing the branch instruction, the branch penalty associated with the indirect branch instruction, the first indirect branch instruction having a particular address, and a program Execution begins at the new target address, the first indirect branch instruction relies on the predecessor instruction to provide the new target address, and the branch unit is coupled to the branch address register to process the relative branch instruction. A branch adder, a branch address register, and a plurality of items, each of which is coupled to a branch address register that includes an address of a previous indirect branch instruction and a corresponding previous target address. And a branch target address table, and when the branch unit receives the first indirect branch instruction in the branch address register, Search the address of the first indirect branch instruction in the address table, and if the address of the first indirect branch instruction matches the address of one of the previous indirect branch instructions, the corresponding previous target address is updated. A system for minimizing branch penalties in a processor, characterized by being used as a target address, whereby the new target address is predicted before being supplied by the preceding instruction. (13) The system according to (12), wherein the first indirect branch instruction is a register-dependent branch instruction. (14) Register-dependent branch instruction is branch-to-count
The system according to (13) above, which is an instruction. (15) The system according to (14), wherein the preceding instruction is a move-to-count instruction. (16) The system according to (13) above, wherein the register-dependent branch instruction is a branch-to-link instruction. (17) The system according to (16) above, wherein the preceding instruction is a move-to-link instruction.

[Brief description of drawings]

FIG. 1 is a block diagram of a processor on which the present invention resides.

FIG. 2 is a block diagram illustrating a branch unit architecture for minimizing the calculated branch penalty of indirect branch instructions.

[Explanation of symbols]

 10 processor 12 instruction cache (IC) 14 instruction buffer (IB) 16 instruction address queue (IAQ) 18 dispatch unit (DU) 20 functional unit (FU) 22 functional unit (FU) 24 functional unit (FU) 26 completion buffer (CB) 28 Branch Unit (BU) 30 Instruction Address Queue (CBIAQ) 42 Count Register 44 Link Register

Front Page Continuation (72) Inventor Christopher H. Olson United States 78730 Austin, Texas Ranch Creek Drive 3649 (72) Inventor Terence M. Potter United States 78731 Austin, Texas Twin Win Ledge Cove 6107

Claims (17)

[Claims] 1. A first table for storing at least one entry containing an address of a previous indirect branch instruction and a previous target address, and a first table coupled to process the first indirect branch instruction. A branch unit, the first indirect branch instruction having a specific address and causing the program execution to start at a new target address, the first indirect branch instruction depending on the preceding instruction to supply the new target address. , The branch unit processes the first indirect branch instruction by comparing the address of the first indirect branch instruction with the address of the previous indirect branch instruction stored in the first table, and if the addresses match, then The target address is used as the new target address, which allows the new target address to be predicted and delivered to the first indirect branch instruction before the preceding target supplies the new target address. A system for minimizing branch penalties within a processor, characterized in that divergence penalties are associated. 2. The system of claim 1, wherein the first table is a branch target address table, and the branch target address table includes a plurality of items. 3. The system of claim 2, wherein each of the plurality of entries in the branch target address table further includes a valid bit. 4. The system of claim 3, wherein the first indirect branch instruction is a branch-to-count instruction. 5. The system of claim 4, wherein the predecessor instruction is a move-to-count instruction. 6. The system of claim 3, wherein the first indirect branch instruction is a branch-to-link instruction. 7. The system of claim 6, wherein the predecessor instruction is a move-to-link instruction. 8. A first table stores at least one item corresponding to a previous indirect branch instruction, including (a) an address of the previous indirect branch instruction and a target address before the previous indirect branch instruction. And (b) comparing the address of the previous indirect branch instruction stored in the first table with the address of the first indirect branch instruction, and (c) indirect branching the address of the first indirect branch instruction before. Using the previous target address as the new target address if it matches the address of the instruction, thereby predicting the new target address before it is supplied by the preceding instruction, and the branch penalty is Related to the first indirect branch instruction, the first indirect branch instruction includes a specific address and causes the program execution to start at a new target address, and the first indirect branch instruction causes the new target address to Characterized in that it depends on the preceding instruction to supply less, a method for minimizing the branch penalty in the processor. 9. Step (a) further comprises: (a1) storing a plurality of items in a first table, and (a2) providing a valid bit for each of the plurality of items in the first table. 9. The method of claim 8, characterized by: 10. The step (c) further comprises: (c1) when the address of the first indirect branch instruction matches the address of the first item of the plurality of items, by the valid bit corresponding to the first item. Determining that a match was found when the first item was shown to be valid; and (c2) sending a target address for the first item from the first table to the instruction cache when determining that a match was found. 10. The method of claim 9, comprising: 11. If no match is found, step (c) further comprises: (c3) retrieving the new target address after the new target address has been supplied by the preceding instruction, and (c4) the first indirect branch instruction. Of the new address, the target address fetched, and the valid bit set in the first table. 12. A branch penalty comprising a dispatch unit for dispatching instructions and a branch unit coupled to the dispatch unit for executing branch instructions, wherein a branch penalty is:
Related to an indirect branch instruction, the first indirect branch instruction has a specific address and causes program execution to start at a new target address, and the first indirect branch instruction depends on the preceding instruction to supply the new target address. However, the branch unit includes a branch adder coupled to the branch address register for processing relative branch instructions, a branch address register, and multiple items, each of the multiple items having a previous indirect branch. A branch target address table coupled to the branch address register containing the address of the instruction and the corresponding previous target address, the branch unit receiving a first indirect branch instruction in the branch address register; ,
Searches the address of the first indirect branch instruction in the branch target address table, and if the address of the first indirect branch instruction matches the address of one of the previous indirect branch instructions, the corresponding previous target address Is used as a new target address, whereby the new target address is predicted before the new target address is supplied by the preceding instruction, thereby minimizing the branch penalty in the processor. 13. The system of claim 12, wherein the first indirect branch instruction is a register dependent branch instruction. 14. A register-dependent branch instruction is a branch-to-co.
The system of claim 13, wherein the system is an unt instruction. 15. The system of claim 14, wherein the predecessor instruction is a move-to-count instruction. 16. A register-dependent branch instruction is a branch-to-li.
14. The system of claim 13, which is an nk instruction. 17. The system of claim 16, wherein the predecessor instruction is a move-to-link instruction.