JPH09326728A - Equalizer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quicken convergence of coefficients and to reduce the power consumption by revising the number of taps of at least an FFE section or a DFE section depending on the magnitude of an error. SOLUTION: Multiplexer blocks 1-4 of an FFE section 121 execute calculation of coefficients for 8 taps and calculation of components for 8 taps for a correction value Y1, Multiplexer blocks 5-8 of a DFE section 122 execute calculation of coefficients for 8 taps and calculation of components for 8 taps for the correction value Y1. A decision section 10 calculates an object value Y2 based on the correction value Y1 with a control section 20 and calculates an error εbased on a deviation of the correction value Y1 from the object value Y2 by an error calculation section 15. Then number of the taps is revised by making part of at least coefficients zero depending on the magnitude of the error εand number of the taps is increased as the error ε is smaller. Thus, the converging speed is quickened without deteriorating the accuracy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive equalizer suitable for digital communication, and more particularly to an improvement for quick adaptation and reduction of power consumption.

[0002]

2. Description of the Related Art FIG. 24 is a block diagram showing a structure of a conventional adaptive equalizer corresponding to data communication of a quadrature amplitude modulation system which is a background of the present invention. As shown in FIG. 24, the equalizer 351 includes an FFE unit 200 and a DF.
The E section 300 and the decision section 250 are provided. The decision unit 250 includes a control unit 251 that calculates a target value Y2 based on the correction value Y1 and an adder 252 that calculates an error ε.

The FFE unit 200 and the DFE unit 300 have the same configuration, and differ in that the FFE unit 200 inputs the input data X, whereas the DFE unit 300 inputs the target value Y2. In the FFE unit 200, 32 unit operation blocks 201 to 2 configured in the same manner as each other
32 are cascade-connected, which enables 32-tap operation. In the FFE unit 200,
Furthermore, the delay circuit unit 1254 and the sign bit extraction unit 256 are provided.

Similarly, in the DFE unit 300, 32 unit operation blocks 301 to 332 configured in the same manner as each other.
Are connected in cascade, which enables 32-tap operation. The DFE unit 300 further includes a delay circuit unit 255 and a sign bit extraction unit 25.
7 and an adder 253 are provided.

Input data X input from the external demodulator at a period T corresponding to a so-called symbol period is input to the terminal C1 of the unit operation block 232 and sent from the terminal C2 to the terminal C1 of the unit operation block 231. To be Similarly, the unit calculation block 101 is sequentially fed.

At the same time, the sign bit of the input data X is extracted by the sign bit extraction unit 256 and input to the delay circuit unit 254. In the delay circuit unit 254, 32 flip-flops FF corresponding to the number of taps are cascade-connected, and a delay of 32 times the cycle T is added to the code bit. The delayed sign bit is input to the terminal D1 of the unit operation block 232 and sent from the terminal D2 to the terminal D1 of the unit operation block 231. Similarly, the unit calculation block 201 is sequentially fed.

The flip-flops provided in this device 351 all operate in synchronization with the clock of cycle T. Therefore, in all flip-flops,
The output is delayed from the input by a period T.

The error ε output from the decision unit 250
Is input to the terminal E1 of the unit operation block 201. Then, it is sent from the terminal E2 to the terminal E1 in the next stage. Similarly, the error ε is calculated by the unit operation block 232
Is forwarded to.

In the unit operation block 201, the sign bit input from the terminal D1, the input data X input from the terminal C1, the error ε input from the terminal E1, and
Based on the initial value “0” input to terminal A, FFE
The component of the correction value Y1 corresponding to 1 tap of all 32 taps of the
02 to the terminal A.

In the unit operation block 202, a similar operation is executed to add a component corresponding to 1 tap to the component corresponding to 1 tap sent from the unit operation block 201, and a unit of the next stage from the terminal B is added. Operation block 20
Send to 3. By repeating the same operation thereafter, the correction value Y is output from the terminal B of the unit operation block 232.
Correction value SU, which is a component corresponding to 32 FFE taps of 1
MDFE is output. This correction value SUMDFE is added to the adder 253.
Is sent to one input.

In the DFE unit 300, the input data X is replaced with the target value Y2 output by the decision unit 250, and then the calculation is executed in the same procedure as the FFE unit 200. The correction value Y1 is input to the other input of the adder 253.
A component corresponding to 32 taps of DFE is supplied. The adder 253 calculates the correction value Y1 by adding these two inputs. As described above, 3 each
A correction value Y1 and a target value Y2 by 2-tap FFE and DFE are calculated.

FIG. 25 is a block diagram showing the structure of a unit operation block 201 which is representative of the unit operation blocks 201 to 232, 301 to 332. As shown in FIG. 25, the data input from the terminal C1 is input to the multiplier 264, and the delay of the period T is added by the flip-flop 271.
It is sent to the terminal C2. Similarly, the sign bit input from the terminal D1 is input to another multiplier 261 and, at the same time, is delayed by the period T by the flip-flop 272 and then sent to the terminal D2.

An error ε is input from the terminal E1.
This error ε is input to the multiplier 261 and is added to the delay of the cycle T by the flip-flop 273 and is output to the terminal E2. The multiplier 261 is
As the multiplication of the error ε and the sign bit is performed,
A minute numerical value corresponding to the so-called step number is further multiplied and then sent to one input of the adder 262.

A one-stage flip-flop 263 is connected to the output side of the adder 262, and its output is returned to the other input of the adder 262. Therefore, adder 2
At 61, the calculation result obtained by the multiplier 261 is the period T
Is added to the previous calculation result. That is, the newly updated coefficient is obtained here.

The data that has passed through the flip-flop 263, that is, the updated coefficient is also input to the multiplier 264, where the product with the data input from the terminal C1 is calculated. This product, which corresponds to the product of the updated coefficient and the input data, is input to one input of another adder 265. The result calculated by the adder 265 is added to the delay of the cycle T by the flip-flop 266 and then output to the terminal B.

At the terminal A, the product of the coefficient and the input data is 32
The calculation result calculated through the unit calculation blocks up to the preceding stage, which corresponds to a part of the total sum of taps, is input.
In the adder 265, the product of the coefficient for another tap and the input data is added to the calculation result.

Returning to FIG. 24, since there is no component that has already been calculated in the unit arithmetic block 201 at the first stage,
The value “0” is input to the terminal A. In this way, the components for one tap are sequentially added to each unit operation block, so that the terminal B of the unit operation block 232 at the last stage is added.
From, the total sum of 32 taps in the FFE unit 200 is obtained.

Similarly, from the terminal B at the last stage of the unit operation blocks 301 to 332 belonging to the DFE unit 300 (FIG. 24), the sum total of 32 taps in the DFE unit 300 is output.

[0019]

As described above, the coefficient calculation and the distortion correction (correction value Y1) performed by the conventional equalizer are performed.
Calculation) and analysis of the error amount (error ε) have always been performed under a constant number of taps and steps. Further, it is also fixed whether or not the DFE unit 300 is used together with the FFE 200, and further, the QAM method adopted when analyzing the error amount is also fixed.

As a result, there is a problem in that the number of taps and the number of steps which are not necessarily suitable for the magnitude of the error amount are used for the calculation, and the coefficient may be converged, that is, the adaptation may be performed inefficiently. It was Further, there is a problem that power is wasted by repeating unnecessary calculations depending on the amount of error.

The present invention has been made in order to solve the above-mentioned problems in the conventional device, and an object thereof is to provide an equalizer capable of realizing adaptation in a short time and reducing power consumption. .

[0022]

According to a first aspect of the present invention, in an adaptive equalizer for removing transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, the symbol is arranged for each symbol period. Input as data into
A series of first constants of this data is multiplied by a series of coefficients of the first constant to generate a series of multiplication values, and the sum of the series of multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so that the error converges to zero for each symbol period, and a target value is input as data for each symbol period, and a second constant in which this data is continuous is input. The column of minutes is multiplied by the column of coefficients for the second constant to generate a column of multiplication values, and the sum of the columns of multiplication values is calculated and output, and the error is set to zero for each symbol period. The second to converge to
A DFE unit that updates a sequence of constant coefficients, an adder that obtains a correction value by adding the outputs of the FFE unit and the DFE unit, the target value is determined based on the correction value, and the correction is performed. A decision unit for updating the error based on a deviation of the value from the target value, wherein the decision unit is at least one of the FFE unit or the DFE unit according to the magnitude of the error. , By setting the value of at least part of the coefficient column to zero, the number of taps is controlled so as to be changed within the range of the first or second constant, and the smaller the error, the more It is characterized by controlling so as to increase the number.

The apparatus of the second invention is the equalizer of the first invention, wherein the decision unit controls the number of taps of both the FFE unit and the DFE unit to be changed based on the error, and The range in which the number of taps of the DFE unit is changed includes zero.

According to a third aspect of the invention, in an adaptive equalizer for removing transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, the symbol is input as data for each symbol period, A series of first constants of this data is multiplied by a series of coefficients of the first constant to generate a series of multiplication values, and the sum of the series of multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so that the error converges to zero for each symbol period, and a target value is input as data for each symbol period, and a second continuous data of this data is input.
The column of constants is multiplied by each column of coefficients of the second constant to generate a column of multiplication values, and the sum of the columns of multiplication values is calculated and output. A DFE unit for updating the sequence of coefficients for the second constant so as to converge to zero, the FFE unit, and the DFE
An adder that obtains a correction value by adding the outputs of the sections, and a decision section that determines the target value based on the correction value and updates the error based on the deviation of the correction value from the target value. And the FFE unit calculates a row of update widths for a first constant, each containing the number of steps and the error as a factor, and adds the row of update widths to the row of coefficients, respectively. The coefficient column is updated, and the DFE unit calculates a column of an update width for a second constant each including the step number and the error as a factor, and the column of the coefficient is updated with the update width. The coefficient column is updated by adding columns, and the decision unit changes the number of steps for both the FFE unit and the DFE unit according to the magnitude of the error. And controlled so, moreover, the more the larger the error, and controls so as to reduce the number of the steps.

According to a fourth aspect of the invention, in an adaptive equalizer for removing transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, the symbol is input as data for each symbol period, A series of first constants of this data is multiplied by a series of coefficients of the first constant to generate a series of multiplication values, and the sum of the series of multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so that the error converges to zero for each symbol period, and a target value is input as data for each symbol period, and a second continuous data of this data is input.
The column of constants is multiplied by each column of coefficients of the second constant to generate a column of multiplication values, and the sum of the columns of multiplication values is calculated and output. A DFE unit for updating the sequence of coefficients for the second constant so as to converge to zero, the FFE unit, and the DFE
An adder that obtains a correction value by adding the outputs of the sections, and a decision section that determines the target value based on the correction value and updates the error based on the deviation of the correction value from the target value. And the decision unit selects the target value from a plurality of quadrature amplitude modulation systems having different levels according to the magnitude relation between at least one reference value and the error, and The lower the quadrature amplitude modulation method is selected as the error is larger than the quadrature amplitude modulation method for the received data.

The apparatus of the fifth invention is an adaptive equalizer for removing transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, and inputting the symbol as data for each symbol period, A series of first constants of this data is multiplied by a series of coefficients of the first constant to generate a series of multiplication values, and the sum of the series of multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so that the error converges to zero for each symbol period, and a target value is input as data for each symbol period, and a second continuous data of this data is input.
The column of constants is multiplied by each column of coefficients of the second constant to generate a column of multiplication values, and the sum of the columns of multiplication values is calculated and output. A DFE unit for updating the sequence of coefficients for the second constant so as to converge to zero, the FFE unit, and the DFE
An adder that obtains a correction value by adding the outputs of the sections, and a decision section that determines the target value based on the correction value and updates the error based on the deviation of the correction value from the target value. , And at least one of the FFE unit or the DFE unit holds P consecutive data strings in the data string of the first or second constant, respectively, and at least 1 / of the symbol period A first register group that outputs a value held in a cycle of P times, one by one,
A second register group that holds P columns of the coefficients corresponding to the P columns of data and outputs them one by one at a period of 1 / P times the symbol period, and the first and second A multiplier for sequentially performing multiplication between the P data strings and the P coefficient strings that the register groups output one by one, and the adder is a first adder, and one input has the multiplication A second adder connected so that the output of the adder is input and the output of the adder is returned and input to the other input.

The apparatus of the sixth invention is the equalizer of the fifth invention, wherein the FFE section is a sequence of update widths for a first constant, each of which has a step number, the error, and a function of the data as factors. And updating the column of coefficients by adding the column of this update width to the column of coefficients, respectively, and the DFE unit determines the number of steps, the error, and the predetermined function of the data. A column having an update width corresponding to a second constant whose factor is, and updating the column of the coefficient by adding the column having the update width to the column of the coefficient, and updating the column of the coefficient by the FFE unit or the DFE unit. At least one of the first and second constants holds P consecutive columns of the columns of the predetermined function, respectively, and outputs them one by one at a period of 1 / P times the symbol period. 3 register group , The multiplier is a first multiplier, and a multiplication is performed step by step between each of the P predetermined function sequences output by the third register group, the error, and the step number. The P second multipliers for calculating the update width, and one output to which the output of the second multiplier is input, and the other input to the second register to be output to the first multiplier. A third adder that updates the value of the coefficient held by the second register one by one by sequentially inputting a sequence of P coefficients, calculating the sum of them, and outputting the sum to the second register group And are further provided.

According to a seventh aspect of the present invention, in an adaptive equalizer for removing transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, the symbol is input as data for each symbol period, A series of first constants of this data is multiplied by a series of coefficients of the first constant to generate a series of multiplication values, and the sum of the series of multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so that the error converges to zero for each symbol period, and a target value is input as data for each symbol period, and a second continuous data of this data is input.
The column of constants is multiplied by each column of coefficients of the second constant to generate a column of multiplication values, and the sum of the columns of multiplication values is calculated and output. A DFE unit for updating the sequence of coefficients for the second constant so as to converge to zero, the FFE unit, and the DFE
An adder that obtains a correction value by adding the outputs of the sections, and a decision section that determines the target value based on the correction value and updates the error based on the deviation of the correction value from the target value. And the FFE unit calculates a column of update widths for a first constant, each of which is a factor of the number of steps, the error, and the function of the data, and the column of update widths is added to the column of coefficients. The coefficient column is updated by adding each, and the DFE unit calculates a column having an update width for a second constant, each of which is a factor of the number of steps, the error, and a predetermined function of the data. Then, the column of the coefficient is updated by adding the column of the update width to the column of the coefficient, and the decision unit, when the error becomes equal to or less than a reference value, the column of the coefficient is updated. Stop updating As to, and controls the FFE portion and the DFE unit.

An apparatus according to an eighth invention is the equalizer according to the seventh invention, wherein each of the FFE section and the DFE section holds a first register which holds the predetermined function while updating the predetermined function for each symbol period. A second register that holds the error while updating it for each symbol period; a third register that holds the coefficient; the predetermined function that the first register holds; the error that the second register holds; And a multiplier for performing the multiplication between the step numbers to calculate the update width, the adder as a first adder, and the update output by the multiplier to the coefficient held in the third register. A second adder that adds the widths and outputs the sum to the third register to update the coefficient held by the third register, the first and second registers, and the control In response to the control signal, the multiplier fixes the value of at least one input to zero in response to the control signal, and the second adder controls the control signal. In response to, by fixing the value of the input on the multiplier side to zero, the coefficient held in the third register is output as it is, and the decision unit
The control signal is transmitted when the error becomes equal to or less than the reference value.

A ninth aspect of the invention is the equalizer of any of the sixth to eighth aspects of the invention, wherein the predetermined function is the code of the data.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION

<1. Principle of Embodiment> First, the basic principle of the equalizer of the embodiment will be described. Among the modulation methods adopted when transmitting digital signals to a transmission line such as a telephone line, as a method with the lowest code error rate and high transmission efficiency (transmission signal amount per unit time), Quadrature amplitude modulation (QAM) is known. QAM is realized by amplitude-modulating two baseband signals generated independently of each other with two orthogonal carrier waves and adding them. That is,
The QAM signal: y (t) sent to the transmission line after modulation is
It is represented by {y (t) = I · cosωt + Q · sinωt}. Here, I is an in-phase component and Q is a quadrature component.

Both the in-phase component I and the quadrature component Q are signals corresponding to digital signals, and their values are discrete. For example, as shown in the graph of FIG. 2 in which the in-phase component I is taken as an example, the in-phase component I and the quadrature component Q are discrete value signals transmitted at intervals of a constant period (referred to as “symbol period”) T. (Referred to as “symbol”). A binary signal to be transmitted is represented by a combination of discrete values of the in-phase component I and the quadrature component Q.

The QAM has 4Q in accordance with the number of bits of a binary signal that can be represented by a combination of the in-phase component I and the quadrature component Q.
There are methods such as AM, 16QAM, 64QAM and 256QAM. A typical arrangement example of these signal points is shown in FIG. FIGS. 3A, 3B, and 3C respectively show
It is a typical example of signal constellation of 16QAM, 64QAM, and 256QAM.

As shown in FIG. 3 (a), in 16QAM, 16 types of numerical values, that is, 4-bit binary signals are expressed by the combination of the in-phase component I and the quadrature component Q. That is, in 16QAM, a 4-bit binary signal is transmitted at one time (in one cycle T). Similarly, 64-QAM represents a 5-bit binary signal and 256QAM represents a 6-bit binary signal. Therefore, under the same period T, the higher the QAM, the higher the transmission efficiency.

In 4QAM, each of the in-phase component I and the quadrature component Q is binary, and the 4-phase phase modulation system (QPS
K).

In order to receive the QAM signal and take out the original in-phase component I and quadrature component Q, the receiving apparatus shown in the block diagram of FIG. 4 is used. The receiver includes a demodulator 99 and an equalizer (equalizer) 100. The demodulator 99 demodulates the input QAM signal: y (t) to extract the in-phase component I0 and the quadrature component Q0. These in-phase component I0 and quadrature component Q0
Does not necessarily match the in-phase component I and the quadrature component Q at the time of transmission.

As schematically shown in the graph of FIG. 5, the in-phase component I (t) and the quadrature component Q (t) included in the QAM signal: y (t) input to the receiver (solid line in the figure). Generally has a distorted waveform that does not match the original in-phase component I and quadrature component Q (dotted line in the figure) due to reflection and other factors in the process of transmission. Therefore, the in-phase component I (t) and the quadrature component Q (t)
Also, the in-phase component I0 and the quadrature component Q0 (white circle symbols in the figure) obtained by sampling at the period T generally have values deviated from the original in-phase component I and the quadrature component Q.

Therefore, the in-phase component I0 and the quadrature component Q0 extracted by the demodulator 99 are further equalized by the equalizer 10 at the subsequent stage.
Then, the distortion component is removed by the equalizer 100. That is, in FIG. 5, the in-phase component I0,
A process for removing distortion, that is, a correction is added to the quadrature component Q0, so that the original in-phase component I and the quadrature component Q are obtained.
The in-phase component I2 and the quadrature component Q2 (black circle symbols in the figure) that match

Returning to FIG. 4, in the equalizer 100, the input data X as a complex number having the in-phase component I0 and the quadrature component Q0 as a component is subjected to a complex operation, so that the in-phase component I2 and the quadrature component Q2 are added. Output data as a complex number (called "target value" as described later)
Y2 is output. The complex operation is performed by using the in-phase component I0 and the quadrature component Q0, as illustrated in FIG.
(FIG. 6A) is subjected to, for example, rotation and extension (or contraction) processing, and the in-phase component I2 and the quadrature component Q2
(FIG. 6B) is obtained. The transmitted binary data is reproduced by encoding the in-phase component I2 and the quadrature component Q2 output from the equalizer 100 into a binary signal using an encoder.

The correction processing by the equalizer 100 must be appropriately performed according to the distortion of the received QAM signal. In a general subscription type communication system, which is the most common communication mode, the transmission line is not constant, and therefore the transmission line distortion is different for each communication. Further, the characteristics of the transmission line may fluctuate due to external causes even during the period in which communication is performed on the fixed transmission line. Therefore, the adaptive equalizer, which adaptively executes the correction processing in accordance with the characteristic variation of the transmission line, is most useful. The equalizer of the embodiments described below is an adaptive equalizer.

Similar to the filter, the adaptive equalizer stores a sequence of input data X (I0, Q0) for a certain period of time, and performs arithmetic processing on the stored data sequence to obtain a certain time point. Output data Y2 (I2, Q2) at (called "center tap") is obtained.
The number of input data X stored at the same time, that is, the value obtained by dividing the above-described fixed period by the period T is called the number of taps. The larger the number of taps, the more accurate the correction becomes.

The equalizer has an FFE (Feed Forward Equalizer) for exclusively removing a distortion component (called "precursor") appearing before the center tap.
And a DFE (Decision Feedback Equalizer) that exclusively removes a distortion component (called “postcursor”) that appears after the center tap.
Moreover, an equalizer (decision feedback equalizer in a narrow sense) having both of these is general.

In an apparatus equipped with FFE, DFE, or both, the coefficient Ci is determined so that the expected value of the variable J given by equation 1, that is, the error ε, is a minute value below a certain level. . In Equation 1, i is a sampling point, L is the number of taps, _XLk is an input data string as a complex number, Y1 is a corrected value, and Y2 is a target value. This target value Y2 is output as output data. Although the target value Y2 is generally multivalued, the correction value Y1
Based on the above, it is set as a temporary target value. In Expression 1, the symbol E represents an expected value. FFE, D
Generally, the number of taps L may be different between FEs.

[0044]

[Equation 1]

The operation of minimizing the variable J according to the equation 1 is practically performed by executing the simpler equation 2. In Expression 2, Δ is a small positive constant called a step number, X _Lk ^* is a conjugate complex number of X _Lk , and sgn (X _Lk ^* ) is its sign. Number of steps Δ
Defines the speed of convergence and the compactness of the coefficient C _k .

[0046]

[Equation 2]

The value of the coefficient C _k is updated according to Equation 2, and the correction value Y1 is calculated based on the updated coefficient C _k . Then, based on the correction value Y1, the target value Y2
Is set, and the error ε is calculated as the difference between them. Then, using the calculated error ε,
Based on this, the coefficient C _k is updated. The cycle of this calculation is repeatedly executed every sampling time, that is, every cycle T. By doing so, the coefficient C _k converges to an optimum value that matches the characteristics of the transmission path, and the original value without error is reproduced as the target value Y2.

<2. Embodiment> Next, an equalizer of the embodiment will be described.

<2-1. Overall Outline> FIG. 1 is a block diagram showing the configuration of the equalizer according to the embodiment. As shown in FIG. 1, the equalizer 101 includes an FFE unit 121, D
The FE unit 122 and the decision unit 10 are provided. The decision unit 10 calculates the target value Y2 and the error ε, and at the same time, the FFE unit 121 and the DFE
The operation of the unit 122 is controlled.

The input data X (I0, Q0) is digitized, and the equalizer 101 performs processing by a kind of digital signal processing method. In addition, the FFE unit 12
In both 1 and the DFE unit 122, the basic algorithm of calculation is given by the definition part of the correction value Y1 of the equation 1 and the equation 2. The difference is that the input data X is input to the FFE unit 121, whereas the target value Y2 is input to the DFE unit 122.

In the FFE unit 121, four multiplexing blocks 1 to 4 are connected in cascade. Then, each of the multiplexing blocks 1 to 4 calculates the coefficient C _k for 8 taps and the component for 8 taps of the correction value Y1. Therefore, the maximum number of taps in the entire FFE unit 121 is 32.
The FFE unit 121 further includes a delay circuit unit 11, a sign bit extraction unit 13, and a flip-flop FF.

Similarly, in the DFE unit 122, four multiplexing blocks 5 to 8 are connected in cascade. Then, each of the multiplexing blocks 5 to 8 calculates the coefficient C _k for 8 taps and the component for 8 taps of the correction value Y1. Therefore, the total number of taps in the DFE unit 122 is 32 at maximum. The DFE unit 122 further includes a delay circuit unit 12, a sign bit extraction unit 14, a flip-flop FF, and an adder 16.

As will be described later, the number of taps in the equalizer 101 is not fixed but variable. That is,
The number of taps of the FFE unit 121 and the DFE unit 122 is not fixed to 32, but is set to 32 at maximum. Also, not only the number of taps,
QAM systems such as 4QAM and 16QAM, and the number of steps Δ etc. are also variable. Moreover, they are selected according to the magnitude of the error ε.

The decision section 10 comprises a control section 20 and an error calculation section 15. The control unit 20 controls the correction value Y
The target value Y2 is calculated based on 1 and FFE is calculated.
Control signal ST to be sent to each of the units 121 and DFE unit 122
Generate EP-SIFT, SEL-TAP0-8, en1-8, FREEZE, RESET. The error calculator 15 is configured as a kind of adder, and calculates the error ε as the magnitude of the difference (distance on the complex plane) based on the correction value Y1 and the target value Y2.

The control unit 20 is further provided with a clock signal CLK, a reset signal RESET, a modulation method instruction signal MOD from the outside.
Is input, and the value of the calculated error ε is input from the error calculation unit 15. The control unit 20 generates various control signals according to these input signals. Normally,
The clock signal CLK is supplied from the demodulator 99, and the reset signal RESET and the modulation method instruction signal MOD are supplied from the receiving side system such as a computer. Control unit 20
Further sends this clock signal CLK as one of the control signals. The clock signal CLK is a pulse signal whose period is T / 8.

The input data X (I0, Q0) input from the demodulator 99 in the cycle T is the terminal C1 of the multiplexing block 4.
To the terminal C1 of the multiplexing block 3 from the terminal C2.
Sent to. Similarly, the multiplexing blocks 3, 2, 1
Is forwarded to. The input data X is also input to the sign bit extraction unit 13 at the same time. Sign bit extraction unit 1
3 is configured as a bit selector for extracting the most significant bit (MSB) of the input data X, that is, the sign bit. This sign bit is the sign sgn (X
Equivalent to _Lk ^* ).

The sign bit extracted by the sign bit extraction unit 13 is input to the delay circuit unit 11. Delay circuit section 11
In order to match the timing between the input data X and the sign bit, which are used for calculation in each of the multiplexing blocks 1 to 4, four flip-flops FF are connected in cascade. The signal en8 transmitted from the decision unit 10 is input to these flip-flops FF as a fetch (capture) enable signal. Signal en8
Is a pulse signal of cycle T, and the flip-flop FF latches the input signal at cycle T in synchronization with the signal en8, as will be described later.

That is, in the delay circuit section 11, the sign bit is delayed for a period of four times the cycle T. The sign bit output from the delay circuit unit 11 is used in the multiplexing block 4
Is input to the terminal D1 of the multiplexing block 3 from the terminal D2.
Is sent to the terminal D1. In the same manner, the blocks are sequentially sent to the multiplexing blocks 3, 2, 1.

Error ε output from the decision unit 10
Is input to the terminal E1 of the multiplexing block 1. Then, it is sent from the terminal E2 to the terminal E1 in the next stage. Similarly, the error ε is sent to the multiplex blocks 2, 3 and 4.

In the multiplexing block 1, the sign bit input from the terminal D1, the input data X input from the terminal C1, the error ε input from the terminal E1, and the terminal A
Based on the initial value “0” input to, all 3 of FFE
A component of the correction value Y1 corresponding to 8 taps out of 2 taps is calculated, and from the terminal B to the terminal A of the multiplexing block 2 of the next stage.
Sent to.

In the multiplexing block 2, by executing the same operation, the adjacent 8 taps corresponding component is further added to the 8 taps corresponding component sent from the multiplexing block 1 and the next stage from the terminal B is added. To the multiplex block 3 of. By repeating the same operation thereafter, the correction value SUMDFE, which is a component corresponding to 32 FFE taps of the correction value Y1, is output from the terminal B of the multiplexing block 4. This correction value SUMDFE is delayed by the period T by the flip-flop FF in order to match the timing and then sent to one input of the adder 16.

The DFE unit 122 replaces the input data X with the target value Y2 output by the decision unit 10, and then executes the calculation in the same procedure as the FFE unit 121. Then, the other input of the adder 16 is supplied with a component corresponding to 32 DFE taps of the correction value Y1. The adder 16 calculates the correction value Y1 by adding these two inputs. As described above, the correction value Y1 and the target value Y2 by FFE and DFE of 32 taps are calculated. The method of calculating the target value Y2 from the correction value Y1 executed by the control unit 20 is conventionally well known.

<2-2. Multiplexing Block> FIG. 7 is a block diagram showing the structure of the multiplexing block 2 representing the multiplexing blocks 2 to 8. The multiplexing blocks 2 to 8 have the same configuration. As shown in FIG. 7, the data input from the terminal C1 is sequentially fed at intervals of the cycle T by the 7-stage flip-flop FF which operates in synchronization with the control signal en8, and is output from the terminal C2. That is, the data at the terminal C2 lags behind the data at the terminal C1 by 7T.

Output data a1 of each flip-flop FF
~ G1 and eight pieces of data h1 of the terminal C1 are input to the selector 21. The selector 21 receives the eight data a1 to h1 according to the eight control signals en1 to en8.
One of them is selected and output to the multiplier 35.

FIG. 8 is a timing chart showing the waveforms of the control signals en1 to en8. As shown in FIG. 8, when the reset signal RESET is released, the control signals en1 to en8 are generated in synchronization with the clock signal CLK supplied from the outside. Then, the eight control signals en1 to en8 become active (value "0" in the example of FIG. 8) for each period of T / 8 in this order for the period of T / 8. Then, after T / 8 when the control signal en8 falls to the active state, the control signal is again set.
en1 falls. Hereinafter, this operation is repeated. Therefore, one control signal, for example, the control signal en8 falls every cycle T.

Returning to FIG. 7, the selector 21 controls the control signal.
The data a1 to h1 are selected one by one in this order according to en1 to en8. Therefore, during the period T, eight pieces of data a1 to h1 are selected one by one in this order at intervals of T / 8 and output.

Similarly, the sign bit input from the terminal D1 is forwarded at intervals of the cycle T by the 7-stage flip-flop FF which operates in synchronization with the control signal en8, and output from the terminal D2. And each flip-flop FF
Output data a2 to g2 and data h2 of the terminal D1
8 pieces of data are input to the selector 22. The selector 22 receives eight data a according to the control signals en1 to en8.
2 to h2 are selected one by one in this order and output to another multiplier 31.

The error ε is input from the terminal E1.
This error ε is input to the multiplier 31, and
It is input to one flip-flop FF. Since the flip-flop FF also operates in synchronization with the control signal en8, the error ε input from the terminal E1 is sent to the terminal E2 with a delay of the period T.

The multiplier 31 sequentially performs multiplication of the error ε and the eight code bits according to the equation 2 during the period T. The multiplication result is sequentially sent to the bit shifter 32. The bit shifter 32 bit-shifts the multiplication result in the LSB direction. A control signal STEP-SIFT is input to the bit shifter 32, and this control signal STEP-SIFT is input.
According to the above, two kinds of bit shift amounts of N bits and M bits are selected.

The N and M bit shifts executed by the bit shifter 32 are equivalent to multiplications of 2 ^-N times and 2 ^-M times, respectively. That is, in the bit shifter 32, the multiplication of the step number Δ = 2 ^−N or 2 ^−M is executed according to the equation 2. These bit shift amounts N and M are the number of steps Δ
Is conventionally set in the range of 2 ^{-8 to} 2 ^-14 , so that it is set in the range of 8 ≦ M <N ≦ 14.

The operation result of the bit shifter 32 is input to one input of the adder 33. The output side of the adder 33 has eight cascaded flip-flops FF0-FF0.
The FF7 is connected, and the outputs of these final stage flip-flops FF0 are returned to the other input of the adder 33.

Although not shown, the flip-flops FF0 to FF7 are supplied with a clock signal CLK having a T / 8 cycle. Therefore, the eight-stage flip-flops FF0 to FF0
The FF 7 sequentially feeds the data U2 sequentially input from the adder 33 at a cycle of T / 8. As a result, the data U1 before the period T appears in the final stage.

Therefore, in the adder 33, the calculation result obtained by the bit shifter 32 is added to the calculation result before the period T. That is, the subtraction in Expression 2 is executed, and the coefficient C _{k, next} is obtained as the data U1.

The data U2, which is the data preceding the data U1 by the period T, is also input to the multiplier 35. The multiplier 35 calculates the product of the data a1 to h1 input to one input at T / 8 intervals and the data U1 input to the other input at T / 8 intervals, and another adder 36
Send to one input. That is, in the multiplier 35,
The product of the coefficient C _i and X _Li of the equation 1 is executed for 8 taps (8 i).

The selector 23 is connected to the other input of the adder 36.
Is input. The data of the terminal A is input to one input of the selector 23, and the data of the terminal B is input to the other input. The control signal en is sent to the selector 23.
8 is inputted as a selection signal, the data of the terminal B is selected when the control signal en8 is normal, the data of the terminal A is selected when it is active, and T / 8
It is sent to the FF 37 that operates in synchronization with the cycle clock CLK.

The result calculated by the FF 37 is sent to the terminal B and the other input of the selector 23. Therefore, the eight pieces of data sequentially input from the multiplier 35 to the FF 37 during the cycle T arrive at the other input of the adder 36 through the adder 36, the selector 23, and the FF 37. Then, one input is added to this other input. By repeating this eight times during the period T,
The products of 8 taps sent from the adder 36 are sequentially added, and the sum of 8 taps in the total sum of C _i × X _{Li shown} in Formula 1 is calculated.

Further, to the terminal A, the operation result calculated through the multiplexing blocks from the first stage to the previous stage (only the multiplexing block 1 if it is the preceding stage of the multiplexing block 2) corresponding to a part of the sum is input. It This calculation result is obtained only when the control signal en8 is active.
After passing through 3, it is input to the FF 37. Therefore,
After the sum of 7 taps is already stored in the FF 37, the multiplication result of the 8th tap by the multiplier 35 and the sum of 7 taps of the FF 37 are added at the timing of the control signal en8, and the timing of the control signal en8 is added. Is sent to terminal B.

In this way, among the sum totals of the equation 1, the sum of 8 taps is newly added to the sum calculated up to the preceding stage in this multiplexing block. Then, it is sent to the next multiplexed block. As a result, from the terminal B of the multiplexing block 4 at the final stage, 3 in the FFE unit 121 side.
The sum of 2 taps is obtained.

The above description is for the case where all the device parts operate, and the specific device parts are selectively operable / stopped by the control signal. This is intended to avoid performing unnecessary calculation depending on the size of the error ε, speed up the coefficient convergence, that is, adaptation, and save power consumption.

The above-mentioned flip-flops FF0 to FF7
A control signal SEL-TAP2 is input to. This signal is used as a switching signal for determining whether or not to execute the operation of the portion in charge of the multiplexing block 2 in the sum total of Equation 1. That is, when the control signal SEL-TAP2 is normal, the flip-flops FF0 to FF7 normally execute the original operation as described above.

On the other hand, when the control signal SEL-TAP2 becomes active, the flip-flops FF0 to FF7 fix the held value to the initial value "0". Therefore, in the multiplexing block 2, the data input from the terminal A is FF37,
After passing through the adder 36, the value is sent to the terminal B without changing the value. That is, in the multiplexing block 2, the correction addition for 8 taps is not performed on the total sum. In addition, since the data held in the flip-flops FF0 to FF7 does not change, power consumption is reduced.

Similarly, the flip-flops FF0 to FF7 belonging to the multiplexing blocks 3 to 8 also have control signals SEL-TAP3.
~ 8 are input respectively and have the same function. The control signal SEL-TAP0,1 will be described later.

Further, the selector 22, the multiplier 31, the bit shifter 32, the adder 33, the flip-flop FF interposed between the terminals E1 and E2, and the delay circuit section 1
A control signal FREEZE is input to 1 and 12 (FIG. 1).
When the control signal FREEZE is normal, these device parts perform their original operation as described above. On the other hand, when the control signal FREEZE becomes active, these device parts freeze their operation.

That is, when the control signal FREEZE is active, the selector 22 does not perform the original selection operation regardless of the control signals en1 to en8 and outputs the value "0" to the other input of the multiplier 31. To do. Further, the flip-flop FF that outputs the sign bit to the selector 22 also stops the operation of updating the output data. Further, when the active control signal FREEZE is input to the multiplier 31, one of the inputs is set to the value "0". As a result, the multiplier 31 outputs the value "
The operation is the same as when the operation was stopped while maintaining 0 ". Further, the bit shifter 32 also stops the bit shift operation.

Further, when the control signal FREEZE becomes active, the adder 33 fixes the input on the side connected to the bit shifter 32 to the value "0" and allows the data U1 to pass through as it is. Further, the flip-flop FF inserted between the terminals E1 and E2 and the flip-flops FF belonging to the delay circuit units 11 and 12 also fix the output data without updating when the control signal FREEZE becomes active. .

As described above, when the control signal FREEZE becomes active, the operation of the device portion relating to the updating of the coefficient is stopped as if it were in a frozen state. As a result, the coefficient is not updated and remains constant. That is,
It is configured to avoid unnecessary power consumption when coefficient updating is not required.

FIG. 9 is a block diagram showing the structure of the multiplexing block 1 located at the first stage of the multiplexing blocks 1-4. Since the multiplexing block 1 is in the first stage, it differs from the other multiplexing blocks 2 to 4 in part of the configuration. First, the flip-flops FF0 to FF7 include the flip-flop FF0 to which the control signal SEL-TAP0 is input and the flip-flops FF1 to FF1 to which the control signal SEL-TAP1 is input.
It is divided into two groups of FF7.

When both the control signals SEL-TAP0, 1 are normal, the flip-flops FF0-FF7 operate in the same manner as the normal operation of the multiplexing block 2 (FIG. 7). On the other hand, only the control signal SEL-TAP0 is normal, and the control signal SEL-
Flip-flop F when TAP1 is active
The data of F1 to FF7 is fixed to the initial value "0". Further, when the control signal SEL-TAP0 becomes active, the data of the flip-flop FF0 is fixed to the initial value "1".

The data of the flip-flop FF0 in the multiplexing block 1 corresponds to the center tap. As for the initial value, only the center tap has the value "1" (I =
1, Q = 0), and all other values (including flip-flops FF0 to FF7 of other multiplexing blocks) ”
It is set to 0 ".

Returning to FIG. 1, in the multiplexing block 1, since there is no sum data to be input to the terminal A from the other stages, the value "0" is input to the terminal A. Also, D
Multiplexing blocks 5 to 8 belonging to the FE unit 122 (FIG. 1)
Are configured and operate in the same manner as the multiplexing block 2. It differs from the multiplexing block 2 only in that the data input to the terminals C1 and D1 is the target value Y2 and its sign. Therefore, from the terminal B of the multiplexing block 8, a maximum of 32 on the DFE unit 122 side expressed by Equation 1 is obtained.
The total sum of taps is output.

As described above, in the FFE unit 121, 32
Calculation of the sum of taps is performed by four multiplexing blocks 1 to 4
8 taps in each of the multiplex blocks 1 to 4, and in each of the multiplexing blocks 1 to 4, multipliers 31 and 35, a bit shifter 32, and an adder 33, which are the device parts for performing multiplication and addition in Expressions 1 and 2, 36 are shared for 8 taps. In other words, these device parts are multiplexed by 8 taps. Similarly, the DFE unit 122 is also multiplexed. Therefore, there are advantages that the circuit scale is reduced, the cost is reduced, and the power consumption is reduced.

In this example, 8 taps are multiplexed, and the degree of multiplexing, that is, the degree of multiplexing P is P = 8.
However, generally, the multiplicity P can be arbitrarily set. The higher the multiplicity, the greater the effect of reducing the circuit scale and power consumption. Depending on the multiplicity P, the number of control signals en1 to en8 (P), the number of flip-flops FF placed on the input side of the selectors 21 and 22 (P-1), and the number of flip-flops FF0 to FF7 (P Individual) changes. The cycle of the clock signal CLK is T / P, and the cycle control signals en1 ...
The falling edge of enN is delayed by T / P in order.

<2-3. Operation Timing> FIG. 10 is a timing chart for explaining the operation of the multiplexing blocks 1 to 4. In FIG. 10, symbols (1) to (4) represent multiplexing blocks 1 to 4, respectively, and symbols x0 to x.
Reference numeral 31 represents the oldest input data X in this order. That is, in FIG. 10, four cycles T0 to T3 of the cycle T are shown.
As an example, the data a1 to h1 of the multiplexing blocks 1 to 4
Is being updated.

For example, in cycle T0, the data a1 to h1 of the multiplexing blocks 1 to 4 are x0 to x7, x in order.
7 to x14, x14 to x21, and x21 to x28. In the next cycle T1, those data are moved one by one, and in order, x1 to x8, x8 to x15, x15.
.About.x22, x22 to x29. Similarly, cycle T
Each time the cycle progresses to 2, T3, the data is forwarded one by one.

Then, in cycle T0, the sum of 8 taps calculated based on the data x0 to x7 in the multiplexing block 1 is the data x8 in the multiplexing block 2 in the next cycle T1. Is added to the sum of 8 taps based on x15 to obtain the sum of 16 taps. Further, the sum of 16 taps is added to the data x1 in the multiplexing block 2 in the next cycle T2.
It is added to the sum of 8 taps based on 6 to x23, and 24
You can get the sum of taps. Then, the sum of 24 taps is added to the sum of 8 taps based on the data x24 to x31 in the multiplexing block 3 in the next cycle T3, and finally the sum of 32 taps is obtained. .

FIG. 11 shows data a in particular for the multiplexing block 1 by taking the following cycles T4 to T7 as an example.
1 is a timing chart showing how 1 to h1, data a2 to h2 as code bits, an error ε, and data U1 and U2 are updated.

In cycle T4, multiplexing block 1
Data a1 to h1 are x4 to x11. On the other hand, data a2 in the same multiplexed block 1
.About.h2 are x0 to x7 (however, only the sign bit), which is delayed by 4T from that due to the function of the delay circuit section 11. In the cycle T5, the data a2 to h2 of the multiplexed block 1 become x1 to x8, and similarly, each time the cycle progresses, one code bit is sequentially fed.

Further, the error ε in the multiplexing block 1 is ε4 in the cycle T4. In the next cycle T5, the error ε4 is sent to the multiplexing block 2 and the error ε5 is sent to the multiplexing block 1. Similarly, as the cycle progresses, the error ε also becomes
The multiple blocks 1 to 4 are sequentially advanced.

In cycle T4, eight data U2
As a result, the operation result between the error ε4 and the sign bits x0 to x7 is obtained. And these eight data U2 are
In the next cycle T5, the data a1 to h1, that is, x
It is used for the calculation of 5 to x12. Hereinafter, the same operation is repeated.

<2-4. Operation of Control Unit> As described above, the control signals STEP-SIFT, SEL-TAP0-8, en sent by the control unit 20 are sent.
Control signal STEP-SIFT, en1 ~ 8, in 1 ~ 8, FREEZE, RESET
FREEZE functions as a selection signal that switches the operation mode of each part of the device. Then, the control unit 20 switches the values of these control signals STEP-SIFT, en1 to 8 and FREEZE according to the magnitude of the error ε. By doing so, an appropriate operation mode is selected according to the magnitude of the error ε.

12 to 14 are flowcharts showing the procedure of the operation mode switching operation in the control unit 20. When the operation is started, it is first determined in step S1 whether or not the operation should be ended. For example, when the communication is completed, or when the coefficient convergence is completed, it is determined that the communication should be completed, and the operation is completed. If it is determined that the processing should not be ended, the process proceeds to step S2.

In step S2, it is determined whether or not the error analysis is the first time. Only when the error analysis is the first time, in step S3, the error amount (error ε) is analyzed by the QPSK method.

Thereafter, the processing shifts to step S4,
It is determined whether the error amount is larger than the reference value A.
Note that in the example of FIG. 12, four reference values A, B, C, and D having a relationship of 0 <D <C <B <A are prepared as reference values to be compared with the error amount. There is. That is, the operation mode of the device is divided according to the magnitude relationship with these reference values.

If it is determined in step S4 that the error amount is larger than the maximum reference value A, the process of step S5 is executed. That is, the first operation mode is selected. In step S5, among the control signals SEL-TAP0 to 8, only the control signal SEL-TAP0 is turned on (normal),
The coefficient calculation, the distortion correction (calculation of the correction value Y1), and the error amount analysis in the 1-tap QPSK method are performed.

Since the control signals SEL-TAP5 to TAP8 are off (active), all the DFE units 122 are turned off. Further, the control signal FREEZE is turned off (normal; released state). Further, the control signal STEP-SIFT specifies N-bit shift, and the smaller value is selected as the step number Δ. When the process in step S5 is completed, the process returns to step S1. The loop from step S1 to returning to step S1 again is repeated every cycle T.

If the determination result is No in step S4, the process proceeds to step S6, and the error amount is compared with the reference value B which is one step smaller than the reference value A. If the determination result is Yes, the process proceeds to step S7, and the second operation mode is selected.

At step S7, the control signals SEL-TAP0-8 are selected.
Among these, only the control signal SEL-TAP0,1 is turned on, and coefficient calculation, distortion correction, and error amount analysis in the 8-tap QPSK method are performed. Also at this time, all the DFE units 122 are in the off state, and the coefficient calculation is executed only by the FFE unit 121. Further, the control signal FREEZE is turned off. Further, the control signal STEP-SIFT specifies N-bit shift. When the process in step S7 is completed, the process returns to step S1.

If the determination result is No in step S6, the process proceeds to step S8, and the error amount is compared with the reference value C which is one step smaller than the reference value B. If the error amount is larger than the reference value C, the process proceeds to step S9, and it is determined whether the modulation system is the QPSK system by referring to the modulation system instruction signal MOD. If the determination result is the QPSK method, the process proceeds to step S10, and the third operation mode is selected.

At step S10, the control signals SEL-TAP0 ...
Of the eight, only the control signal SEL-TAP0,1,7,8 is turned on,
The FFE unit 121 and the DFE unit 122 each perform coefficient calculation with 16 taps and distortion correction, and based on the results, QP
The error amount is analyzed by the SK method. Further, the control signal FREEZE is turned off, and the control signal STEP-SIFT specifies N-bit shift. When the process in step S10 is completed, the process returns to step S1.

If it is determined in step S9 that the system is not the QPSK system, the process proceeds to step S11,
The fourth operation mode is selected. In step S11,
Of the control signals SEL-TAP0 to 8, control signals SEL-TAP0,1,7,8
Only the FFE unit 121 and the DFE unit 122 perform coefficient calculation with 16 taps and distortion correction, and based on the results, the error amount is analyzed in the 16QAM system. Also, the control signal FREEZE is turned off and the control signal ST
In EP-SIFT, N-bit shift is designated. When the processing in step S11 is completed, the processing returns to step S1.

If the error amount is equal to or smaller than the reference value C in the determination in step S8, the process proceeds to step S12, and the error amount is compared with the smallest reference value D. If the error amount is larger than the reference value D, the process proceeds to step S13, and it is determined whether the modulation system is the QPSK system by referring to the modulation system instruction signal MOD. If the result of determination is that it is the QPSK system, the processing moves to step S14, and the fifth operation mode is selected.

At step S14, control signals SEL-TAP0 ...
All 8 are turned on, FFE unit 121, DFE unit 1
Coefficient calculation and distortion correction are performed with 32 taps in each of 22 and, based on the results, analysis of the error amount in the QPSK method is performed. Further, the control signal FREEZE is turned off, the control signal STEP-SIFT designates M-bit shift, and the step number Δ having a larger value is selected. Step S
When the process in 14 is completed, the process returns to step S1.

If it is determined in step S13 that the modulation system is not the QPSK system, the process proceeds to step S11, and it is determined whether the modulation system is the 16QAM system by referring to the modulation system instruction signal MOD. . If the result of determination is 16QAM, the processing moves to step S16, and the sixth operation mode is selected.

At step S16, the control signals SEL-TAP0 ...
All 8 are turned on, and coefficient calculation, distortion correction, and error amount analysis are performed in the 16-QAM system with 32 taps. Further, the control signal FREEZE is turned off, and the control signal STEP-SIFT specifies M bit shift. When the process of step S16 is completed, the process returns to step S1.

When it is determined in step S15 that the mode is not 16QAM, the process proceeds to step S17, and it is determined whether or not the modulation method is the 64QAM method. If the result of the determination is that it is the 64QAM system, the processing is step S.
Moving to 18, the seventh operation mode is selected.

At step S18, control signals SEL-TAP0 ...
All 8 are turned on, and coefficient calculation, distortion correction, and error amount analysis are performed in the 32-tap 64QAM system. Further, the control signal FREEZE is turned off, and the control signal STEP-SIFT specifies M bit shift. When the process of step S18 is completed, the process returns to step S1.

If it is determined in step S17 that the QAM is not 64QAM, the process proceeds to step S19 and the eighth
Operation mode is selected. In step S19, all of the control signals SEL-TAP0 to 8 are turned on, and coefficient calculation, distortion correction, and error amount analysis by the 32-tap 256QAM method are performed. Further, the control signal FREEZE is turned off, and the control signal STEP-SIFT specifies M bit shift. When the processing in step S19 is completed, the processing is performed in step S
Return to 1.

Next, when it is determined in step S12 that the error amount is less than or equal to the minimum reference value D, the process proceeds to step S20. In step S20, it is determined whether the modulation method is the QPSK method. If the result of the determination is that it is the QPSK method, the processing is step S2.
The process shifts to 1 and the ninth operation mode is selected.

In step S21, the control signals SEL-TAP0 ...
All 8 are turned on and coefficient calculation, distortion correction, and error amount analysis are performed in QPSK with 32 taps. Further, the control signal FREEZE is turned on (active; set state), and the control signal STEP-SIFT specifies M bit shift. When the process in step S21 is completed, the process proceeds to step S21.
Return to 1.

If it is determined in step S20 that the system is not the QPSK system, the process proceeds to step S22, and it is determined whether the modulation system is the 16QAM system. If the result of determination is that it is the 16QAM system, the processing moves to step S23, and the tenth operation mode is selected.

At step S23, the control signals SEL-TAP0 ...
All 8 are turned on, and coefficient calculation, distortion correction, and error amount analysis are performed in the 16-QAM system with 32 taps. Further, the control signal FREEZE is turned on, and the control signal STEP-SIFT specifies M bit shift. When the process of step S23 is completed, the process returns to step S1.

When it is determined in step S22 that the mode is not 16QAM, the process proceeds to step S24, and it is determined whether or not the modulation method is the 64QAM method. If the result of the determination is that it is the 64QAM system, the processing is step S.
25, and the eleventh operation mode is selected.

At step S25, the control signals SEL-TAP0 ...
All 8 are turned on, and coefficient calculation, distortion correction, and error amount analysis are performed in the 32-tap 64QAM system. Further, the control signal FREEZE is turned on, and the control signal STEP-SIFT specifies M bit shift. When the process of step S25 is completed, the process returns to step S1.

If it is determined in step S24 that it is not 64QAM, the process proceeds to step S26, where the first
The two operation modes are selected. In step S26, all of the control signals SEL-TAP0-8 are turned on, and coefficient calculation, distortion correction, and error amount analysis are performed in the 32-tap 256QAM system. Further, the control signal FREEZE is turned on, and the control signal STEP-SIFT specifies M bit shift.
When the process of step S26 is completed, the process returns to step S1.

It is generally possible to analyze the error amount of the high-order QAM system signal adopted by the above procedure using the low-order QAM system algorithm. Also, Q
For PSK, 16QAM, 64QAM, and 256QAM, the error determination is performed based on the error determination formula shown in Expression 3. For example, when Y1 = [01011],
ε (4) = [0011] and ε (16) = [111]. The error discriminant itself is well known in the art.

[0126]

(Equation 3)

As described above, in the equalizer 101, the control unit 20 follows the procedure shown in FIGS. 12 to 14, and outputs the control signal according to the magnitude of the error amount (error ε).
STEP-SIFT, en1 ~ 8, FREEZE are selectively output. Then, as the error amount decreases, that is, as the coefficient convergence progresses, the number of taps is increased and the number of QAM levels is increased from the lower level to the level of actual communication. , Perform more precise arithmetic.

Therefore, it is possible to reduce the erroneous determination (erroneous calculation of the target value Y2 and the error ε) which tends to occur when the distortion of the input data X is large. At the same time, there is an advantage that the convergence can be accelerated without deteriorating the accuracy of the convergence. In addition, the number of steps Δ is set small at the beginning when the error amount is large, and is changed to a large value as the error amount becomes small, so erroneous coefficient updating that does not result in convergence is avoided. .

Further, when the coefficient is sufficiently converged to a level where the coefficient update is no longer necessary and the error amount reaches a sufficiently small size (size equal to or smaller than the reference value D), control is performed. By turning on the signal FREEZE, the unnecessary operation of each part of the device relating to the updating of the coefficient is stopped. As a result, unnecessary power consumption is saved.

As described above, in the equalizer 101, by appropriately changing the operation mode of each part of the device according to the error amount, convergence is speeded up, erroneous processing is prevented, and power consumption is reduced. ing.

<3. Modification> Next, a modification of the above-described embodiment will be described. In the following drawings, the same parts as those of the apparatus of the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted.

(1) FIG. 15 is a block diagram showing an equalizer of the first modification. Like the equalizer 101, the equalizer 102 also includes the FFE unit 131 and the FFE unit 1.
The number of taps of each of 32 is set to 32 at maximum. In this equalizer 102, the equalizer 101
The multiplexing blocks 1 to 8 in FIG.
Replaced by ~ 58. Multiplexing blocks 51 and 52 (53 to 58) are added to the block diagrams of FIGS.
Shows the configuration of.

In the multiplexing blocks 51 to 58, the terminal E1
The multiplexing block 1 to 8 is characteristically different in that the error .epsilon. Input from the above is configured to be input to the multiplier 31 after passing through the flip-flop FF. Along with this, flip-flops FF provided in the delay circuit units 61 and 62 connected to the rear portions of the sign bit extraction units 13 and 14 in order to achieve timing matching.
The number of steps is set to 5.

Since the equalizer 102 is constructed in this way, the delay amount for the error ε is shortened. As a result, for example, the operation speed of the equalizer 101 is 10 MHz.
Then, the equalizer 102 has 20 MHz
Can be operated with.

(2) FIG. 18 is a block diagram showing the structure of the equalizer of the second modification. This equalizer 103
Then, the maximum number of taps is set to 24 taps in the FFE unit 141 and 16 taps in the DFE unit 142. Each of them is multiplexed by 8 taps, and three multiplexed blocks are provided in the FFE unit 141 and a DFE unit 142.
Two are provided in.

Furthermore, the number of flip-flops FF belonging to the delay circuit sections 66 and 67 provided behind the sign bit extraction sections 13 and 14 is set to three and two, respectively. With such a configuration, the equalizer 103 can obtain a characteristic different from that of the equalizer 101 in the distortion correction performance due to the time delay component.

Although FIG. 18 shows an example in which the FFE unit 141 is provided with three-stage multiplexing blocks 1 to 3, and the DFE unit 142 is provided with two-stage multiplexing blocks 4 and 5, generally, the multiplicity P The FFE unit may be provided with J stages and the DFE unit may be provided with K stages. At this time, the delay circuit unit 66,
The number of flip-flops FF belonging to 67 is set to J and K stages, respectively. Further, the number of taps is P × J in the FFE unit and P × K in the DFE unit.

(3) FIG. 19 is a block diagram showing the structure of the equalizer of the third modification. This equalizer 104
Is configured to incorporate the features of the equalizer 102 of the first modification into the equalizer 103 of the second modification. That is, the FFE unit 171 uses the multiplexing block 5
By including 1 to 53, a 24-tap operation is realized, and the DFE unit 152 uses the multiplexing blocks 54 and 5
By including 5, the calculation of 16 taps is realized.

Further, the multiplexing blocks 51 to 53, 54,
Since 55 is used, the number of flip-flops FF belonging to the delay circuit units 71 and 72 connected to the rear of the sign bit extraction units 13 and 14 is four, respectively.
And 3 levels are set. Since the equalizer 104 is configured in this way, the characteristics of both the equalizers 102 and 103 are realized at the same time.

FIG. 19 shows an example in which the FFE section 151 is provided with three-stage multiplexing blocks 51 to 53, and the DFE section 152 is provided with two-stage multiplexing blocks 54 and 55. Multiplexing block of J stages, D
The FE section may have K stages. At this time, the number of stages of the flip-flops FF belonging to the delay circuit units 71 and 72 is
J + 1 and K + 1 stages are set, respectively. The number of taps is P × J in the FFE section and P in the DFE section.
XK.

(4) FIG. 20 is a block diagram showing the structure of the equalizer of the fourth modification. This equalizer 105
In the FFE unit 161, only one multiplexing block 81 for multiplexing 8 taps is provided, and in the DFE unit 162, only one similar multiplexing block 82 is provided.
Accordingly, the number of flip-flops FF belonging to the delay circuit units 76 and 77 placed behind the sign bit extraction units 13 and 14 is set to one.

The structure of the multiplexing blocks 82 and 81 is shown in FIG.
1 and the block diagram of FIG. 22, respectively. That is, the multiplexing blocks 82 and 81 can be configured in the same manner as the multiplexing blocks 5 and 1, respectively.

As exemplified by the equalizer 105,
It is also possible to multiplex all the tap numbers of the FFE unit and the DFE unit. The multiplicity P described in the embodiment can be set to any size up to the number of taps in each of the FFE unit and the DFE unit.

(5) FIG. 23 is a block diagram showing the structure of the equalizer of the fifth modification. This equalizer 106
Is configured to incorporate the features of the equalizer 102 of the first modified example into the equalizer 105 of the fourth modified example. That is, the FFE unit 171 uses the multiplexing block 5
The operation of 8 taps is realized by providing only one stage of 1, and the DFE unit 172 realizes the operation of 8 taps by similarly providing only one stage of the multiplexing block 52.

Since the multiplexing blocks 51 and 52 are used, the number of flip-flops FF belonging to the delay circuit units 91 and 92 connected behind the sign bit extracting units 13 and 14 is 2 in each case. It is set to a tier. Since the equalizer 106 is configured in this way,
The characteristics of both equalizers 102 and 105 are realized together.

[0146]

In the device of the first aspect of the present invention, the number of taps is variable, and the number of taps increases as the error becomes smaller as the convergence progresses, so that the accuracy of the convergence is not deteriorated. The convergence can be accelerated. Moreover, since the number of taps is changed by selectively setting the coefficient column to zero, it is possible to avoid the adverse effect of the data before change on the change after change.

In the apparatus of the second invention, the number of taps in both the FFE section and the DFE section is changed depending on the size of the error, and the DFE section sets the number of taps to zero depending on the error value. Distortion is removed only by itself. That is, the number of taps can be changed widely, and the convergence can be performed more quickly.

In the device of the third invention, the larger the error, the smaller the number of steps is set, and the coefficient is updated with a small update width. For this reason, when the error is too large to be helpful, it is possible to avoid erroneous updating of the coefficient that does not result in convergence.

In the device of the fourth invention, the quadrature amplitude modulation system of lower rank is selected as compared with the quadrature amplitude modulation system of the received data as the error is larger. Therefore, the erroneous determination which is likely to occur when the symbol distortion is large Can be reduced.

In the device of the fifth invention, the product of the coefficient for P taps and the data is calculated by a single multiplier, and the operation for calculating the sum of the multiplied values for P taps is performed by a single multiplier. It is performed by 2 adders. That is, the data provided to the multiplier and the adder are P-multiplexed, so that these arithmetic units are shared P times. Therefore, it is possible to reduce the circuit size and power consumption.

In the apparatus of the sixth invention, the calculation of the update width of the coefficient for P taps and the update of the coefficient are performed by the single second multiplier and third adder, respectively. That is, the data provided to the multiplier and the adder are P-multiplexed, so that these arithmetic units are shared P times. Therefore, it is possible to further reduce the circuit scale and further reduce power consumption.

In the device of the seventh invention, by setting the reference value to a sufficiently small error value, the coefficient update is stopped when the error becomes so small that the coefficient update is no longer necessary. Therefore, the coefficient is stable. Further, it is possible to suppress unnecessary consumption of electric power due to unnecessary calculation.

In the device of the eighth aspect of the invention, when the error becomes equal to or less than the reference value, the operations of the register, the multiplier and the adder relating to the updating of the coefficient are effectively stopped. Therefore, it is possible to suppress wasteful consumption of electric power due to unnecessary operation of these device parts when the coefficient update is not necessary.

In the device of the ninth aspect of the invention, the function of the data, which is one of the factors of the updating width of the coefficient, is set not to the data itself but to its code, so that the scale of the device is reduced and Power consumption is reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment.

FIG. 2 is a graph of a waveform of a symbol handled by the device according to the embodiment.

FIG. 3 is a signal point arrangement diagram of symbols handled by the device according to the embodiment.

FIG. 4 is a block diagram showing an apparatus according to the embodiment and its periphery.

FIG. 5 is a graph of a waveform of a symbol handled by the device according to the embodiment.

FIG. 6 is a signal point arrangement diagram of symbols handled by the device according to the embodiment.

FIG. 7 is a block diagram of a multiplexing block according to the embodiment.

FIG. 8 is a timing chart showing the operation of the apparatus according to the embodiment.

FIG. 9 is a block diagram of a multiplexing block according to the embodiment.

FIG. 10 is a timing chart showing the operation of the apparatus according to the embodiment.

FIG. 11 is a timing chart showing the operation of the apparatus according to the embodiment.

FIG. 12 is a flowchart showing a process of a control unit according to the embodiment.

FIG. 13 is a flowchart showing processing of the control unit according to the embodiment.

FIG. 14 is a flowchart showing a process of a control unit according to the embodiment.

FIG. 15 is a block diagram of an apparatus according to a first modified example.

FIG. 16 is a block diagram of a multiplexing block of a first modified example.

FIG. 17 is a block diagram of a multiplexing block of a first modified example.

FIG. 18 is a block diagram of an apparatus of a second modified example.

FIG. 19 is a block diagram of an apparatus of a third modified example.

FIG. 20 is a block diagram of an apparatus according to a fourth modified example.

FIG. 21 is a block diagram of a multiplexing block of a fourth modified example.

FIG. 22 is a block diagram of a multiplexing block of a fourth modified example.

FIG. 23 is a block diagram of a device according to a fifth modification.

FIG. 24 is a block diagram of a conventional device.

FIG. 25 is a block diagram of a unit operation block of a conventional device.

[Explanation of symbols]

X input data, Y1 correction value, Y2 target value, ε error, CLK clock signal, 1 to 8, 51 to 58 multiplex block, 10 decision unit, 15 error calculation unit, 20 control unit, 121, 131, 141, 151 ，
161, 171 FFE section, 122, 132, 142, 1
52, 162, 172 DFE section, 101-106 equalizer.

Claims (9)

[Claims] 1. An adaptive equalizer that removes transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, wherein the symbol is input as data for each symbol period, and the continuous data of the symbol is input. The column of one constant is multiplied by the column of coefficients of the first constant to generate a column of multiplication values, and the sum of the columns of the multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so as to converge to zero, and a target value is input as data for each symbol period,
A series of the second constants of this data is multiplied by a series of coefficients of the second constant to generate a series of multiplication values, and the sum of the series of the multiplication values is calculated and output. A DFE unit that updates a sequence of coefficients for the second constant so that the error converges to zero for each symbol period; and an adder that adds outputs of the FFE unit and the DFE unit to obtain a correction value. , A decision unit for determining the target value based on the correction value, and updating the error based on a deviation from the target value of the correction value, the decision unit, the FFE unit or the DFE
For at least one of the parts, by zeroing the value of at least part of the sequence of coefficients according to the magnitude of the error, respectively in the range of the first or second constant,
The equalizer is controlled so that the number of taps is changed, and the number of taps is increased as the error is smaller. 2. The equalizer according to claim 1, wherein the decision unit controls the number of taps of both the FFE unit and the DFE unit to be changed based on the error, and further, the tap of the DFE unit is controlled. An equalizer characterized in that the changed range of numbers also includes zero. 3. An adaptive equalizer that removes transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, wherein the symbol is input as data for each symbol period, and a continuous number of this data is input. The column of one constant is multiplied by the column of coefficients of the first constant to generate a column of multiplication values, and the sum of the columns of the multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so as to converge to zero, and a target value is input as data for each symbol period,
A series of the second constants of this data is multiplied by a series of coefficients of the second constant to generate a series of multiplication values, and the sum of the series of the multiplication values is calculated and output. A DFE unit that updates a sequence of coefficients for the second constant so that the error converges to zero for each symbol period; and an adder that adds outputs of the FFE unit and the DFE unit to obtain a correction value. A decision unit that determines the target value based on the correction value and updates the error based on a deviation of the correction value from the target value.
The FE unit calculates a row of update widths for a first constant, each of which includes the number of steps and the error as a factor, and adds the row of update widths to the row of coefficients to calculate the row of the coefficient. The update is executed, and the DFE unit calculates a column of update widths corresponding to a second constant each including the step number and the error as factors, and adds the column of update widths to the column of coefficients. Updating the sequence of coefficients by means of which the decision unit comprises the FFE unit and the DFE.
Both of the parts are controlled so that the number of steps is changed according to the magnitude of the error, and further, the number of steps is controlled to be smaller as the error is larger. equalizer. 4. An adaptive equalizer that removes transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, wherein the symbol is input as data for each symbol period, and a continuous number of this data is input. The column of one constant is multiplied by the column of coefficients of the first constant to generate a column of multiplication values, and the sum of the columns of the multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so as to converge to zero, and a target value is input as data for each symbol period,
A series of the second constants of this data is multiplied by a series of coefficients of the second constant to generate a series of multiplication values, and the sum of the series of the multiplication values is calculated and output. A DFE unit that updates a sequence of coefficients for the second constant so that the error converges to zero for each symbol period; and an adder that adds outputs of the FFE unit and the DFE unit to obtain a correction value. A decision unit that determines the target value based on the correction value and updates the error based on a deviation of the correction value from the target value, the decision unit determining the target value. According to the magnitude relationship between at least one reference value and the error, the quadrature amplitude modulation method having different levels is selected. Compared to the amplitude modulation scheme, equalizer and selects the lower level quadrature amplitude modulation scheme. 5. An adaptive equalizer that removes transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, wherein the symbol is input as data for each symbol period, and the continuous data of the symbol is input. The column of one constant is multiplied by the column of coefficients of the first constant to generate a column of multiplication values, and the sum of the columns of the multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so as to converge to zero, and a target value is input as data for each symbol period,
A series of the second constants of this data is multiplied by a series of coefficients of the second constant to generate a series of multiplication values, and the sum of the series of the multiplication values is calculated and output. A DFE unit that updates a sequence of coefficients for the second constant so that the error converges to zero for each symbol period; and an adder that adds outputs of the FFE unit and the DFE unit to obtain a correction value. A decision unit that determines the target value based on the correction value and updates the error based on a deviation of the correction value from the target value, and includes at least one of the FFE unit and the DFE unit. Is the P in the sequence of the data of the first or second constant, respectively.
A first register group that holds a continuous string of data and outputs a value held at a cycle of 1 / P times the symbol cycle, and P pieces of the P registers corresponding to the P data rows. A second register group that holds a sequence of coefficients and outputs them one by one at a period of 1 / P times the symbol period, and a sequence of the P pieces of data that each of the first and second register groups outputs one by one. And a multiplier for sequentially performing multiplication between the P coefficient sequences, and the adder as a first adder, wherein the output of the multiplier is input to one input and the output is returned to the other input. A second adder connected so as to input the equalizer, and an equalizer. 6. The equalizer according to claim 5, wherein the FFE unit calculates a sequence of update widths for a first constant, each of which has a step number, the error, and a function of the data, The coefficient column is updated by adding each column of this update width to the column of coefficients, and the DFE unit each has a step number, the error, and a predetermined function of the data as factors. The column of the update width is calculated for two constants, and the column of the coefficient is updated by adding the column of the update width to the column of the coefficient, and at least one of the FFE unit or the DFE unit is executed. , Holding P consecutive columns in the sequence of the predetermined function of a first or second constant, respectively, and
A third register group that outputs them one by one in a P times cycle; each of the P predetermined function columns that the third register group outputs one by one, and the error And the number of steps described above are performed step by step to multiply by P
Second multipliers for calculating the number of update widths, and the output of the second multiplier is input to one input one by one, and the P output from the second register to the first multiplier is input to the other input. And a third adder for updating the value of the coefficient held by the second register one by one by inputting each coefficient string one by one, calculating the sum of them, and outputting the sum to the second register group one by one. An equalizer, further comprising: 7. An adaptive equalizer that removes transmission distortion of a symbol obtained by demodulating received data of a quadrature amplitude modulation system, wherein the symbol is input as data for each symbol period, and a continuous first data of this data is generated. The column of one constant is multiplied by the column of coefficients of the first constant to generate a column of multiplication values, and the sum of the columns of the multiplication values is calculated and output. An FFE unit that updates the sequence of coefficients for the first constant so as to converge to zero, and a target value is input as data for each symbol period,
A series of the second constants of this data is multiplied by a series of coefficients of the second constant to generate a series of multiplication values, and the sum of the series of the multiplication values is calculated and output. A DFE unit that updates a sequence of coefficients for the second constant so that the error converges to zero for each symbol period; and an adder that adds outputs of the FFE unit and the DFE unit to obtain a correction value. , A decision unit for determining the target value based on the correction value, and updating the error based on a deviation of the correction value from the target value, and the FFE unit, each of the number of steps, The update width column for the first constant, which is a factor of the error and the function of the data, is calculated, and the coefficient width column is updated by adding the update width column to the coefficient column, respectively. , The DFE The unit calculates a row of update widths for a second constant, each of which is a factor of the number of steps, the error, and a predetermined function of the data, and adds the row of update widths to the row of coefficients. Update the coefficient column, and the decision unit controls the FFE unit and the DFE unit to stop updating the coefficient column when the error becomes equal to or less than a reference value. Equalizer characterized by that. 8. The equalizer according to claim 7, wherein each of the FFE unit and the DFE unit holds a first register that holds the predetermined function while updating the predetermined function for each symbol cycle, and the error to the symbol. A second register that holds the coefficient while updating it every cycle; a third register that holds the coefficient; a predetermined function that the first register holds;
A multiplier for performing the multiplication between the error held by the register and the number of steps to calculate the update width, the adder as a first adder, and the coefficient held by the third register for the coefficient. A second adder that adds the update width output from the multiplier and outputs the added update width to the third register to update the coefficient held in the third register, the first and second registers Responds to the control signal by
Stop updating the value to be held, the multiplier fixes the value of at least one input thereof to zero in response to the control signal, and the second adder responds to the control signal in response to the control signal. By fixing the value of the input on the multiplier side to zero, the third
The equalizer, wherein the coefficient held in the register is output as it is, and the decision unit sends the control signal when the error becomes equal to or less than the reference value. 9. The equalizer according to claim 6, wherein the predetermined function is a code of the data.