JPH09326400A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacitance of a base and a collector by forming the first insulating layer consisting of an insulator and the second insulating layer consisting of a compound polycrystalline semiconductor in order in a parasitic collector region. SOLUTION: A high dope n-type InGaAs layer 2 is grown on a semiinsulating InP substrate 1 by molecular beam epitaxy method. Then, an Si3 N4 film 3 as a first insulating layer is piled up by chemical vapor phase piling method, and the Si3 N4 film 3 is left only in the parasitic collector region by photolithography and shock absorbing fluoric acid. Successively, compount polycrystalline 9 as a second insulating layer is stacked on the Si3 N4 film 3 left in the parasitic collector region. Hereby, the capacitance of a base and a collector can be reduced without the problem of base.collector resistance drop.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor heterojunction bipolar transistor having a high base / collector reverse breakdown voltage and a high maximum oscillation frequency, and a semiconductor device having the same.

[0002]

2. Description of the Related Art Reduction of the base-collector capacitance is effective for improving the maximum oscillation frequency of a heterojunction bipolar transistor. As a measure against this, (1) a technique of implanting ions such as oxygen into the parasitic collector region 14 (see FIG. 5) to deplete carriers in the parasitic collector region is an eye electron electron.
Device Letters Volume EDL-5 (1984) Vol. 3
Pages 10 to 312 (IEEE Electron
Device Letters EDL-5 (198
4) pp. 310-312), and (2) SiO ₂ 1 having a small relative dielectric constant in the parasitic collector region below the base electrode.
5 (see FIG. 6) is a solid state electronics volume 38 (1995) 1619.
Pages 1622 (Solid State Ele)
ctronics Vol. 38 (1995) pp.
1619-1622).

[0003]

Although the above-mentioned prior art is effective for the heterojunction bipolar transistor using GaAs for the base and collector, it is as follows for the heterojunction bipolar transistor using InGaAs for the base and collector. There was a problem. That is, in the conventional technique (1), the defects generated by the ion implantation become donors in InGaAs, and InGaA
Since s does not become an n-type and is not depleted, reduction of the base-collector capacitance cannot be realized. Further, in the prior art (2), there is a problem that a leak current is generated at the interface 16 between InGaAs and SiO ₂ (see FIG. 6) and the reverse breakdown voltage of the base / collector is deteriorated. Si ₃ N instead of SiO _{2
If 4} is used, the leakage current is reduced by one digit or more, but I
The thermal expansion coefficient of nGaAs and Si ₃ N ₄ is more than 15 times different,
Since cracks occur, the film thickness of Si ₃ N ₄ should be 100 nm.
Since the thickness cannot be increased to the above value, the base / collector capacitance cannot be sufficiently reduced.

[0004]

In order to solve the above-mentioned problems of the prior art, the present invention provides, in a parasitic collector region, a first insulating layer made of an insulator and a second insulating layer made of a compound polycrystalline semiconductor. Are formed in order to reduce the base-collector capacitance.

[0005]

DETAILED DESCRIPTION OF THE INVENTION Si deposited on a GaAs substrate.
_An n-type and p-type polycrystalline InGaAs layer (InAs molar ratio 0.53, film thickness 0.5 μm) was formed on the ₃ N ₄ film (film thickness 10-100 nm) by a molecular beam epitaxy method at a substrate temperature of 350- Deposition rate 0.01-1 μm / at 450 ° C
As a result of forming with h, the concentration of Si used as an impurity is 1 × 10 ¹⁶ cm ⁻³ or more and 2 × 10 ²⁰ cm ⁻³ or less in the case of n type, and the C concentration used as an impurity is 1 × 1 in the case of p type
It was clarified that an insulating layer having a resistivity of 1 MΩcm or more was formed regardless of the substrate temperature and the deposition rate at 0 ¹⁷ cm ^-3 or more and 5 × 10 ¹⁹ cm ^-3 or less. It was confirmed that when these films were used for the parasitic collector region, carriers in the region were depleted, which contributed to the reduction of the base-collector capacitance. In the case of an n-type polycrystalline InGaAs layer, Si
When the concentration exceeds 2 × 10 ²⁰ cm ⁻³ , the resistivity sharply decreases and exhibits conductivity. Therefore, in order to form an insulating film, the Si concentration must be 2 × 10 ²⁰ cm ⁻³ or less.
The lower limit of the i concentration does not have to be 1 × 10 ¹⁶ cm ⁻³ or more as in the above experiment, and it is easily judged that it may be lower. Similarly, in the case of the p-type polycrystalline InGaAs layer, the lower limit of the concentration may be lower than the above experimental condition. It should be noted that the upper limit of the Si ₃ N ₄ film thickness of 100 nm is the crack generation limit, and the lower limit of 10 nm is determined in consideration of the in-plane variation of the wafer during the Si ₃ N ₄ film deposition.

According to the present invention, the parasitic collector region becomes a high-resistance polycrystalline semiconductor and carriers are depleted. As a result, the base-collector capacitance can be reduced without the occurrence of leak current or cracks. A compound semiconductor heterojunction bipolar transistor having a high maximum oscillation frequency and a semiconductor device having the same can be manufactured.

Example 1 npn type InP / InGaAs which is Example 1 of the present invention
The heterojunction bipolar transistor and its manufacturing method will be described with reference to FIGS.

As shown in the longitudinal sectional view of FIG. 1, a Si ₃ N ₄ film 3 (thickness 30 nm) and a high-resistance polycrystalline semiconductor layer 9 are buried in the parasitic collector region and the external base region. Compared with no embedding of these layers,
The collector capacitance was reduced by 30% and the maximum oscillation frequency was increased by 43%, and a value exceeding 200 GHz was obtained. Further, the reverse breakdown voltage of the base / collector was as high as 10 V, which was the same as when the layers 3 and 9 were not buried.

A method of manufacturing the InP / InGaAs heterojunction bipolar transistor shown in FIG. 1 will be described below. First, a highly-doped n-type InGaAs layer (InAs molar ratio: 0.53, on a semi-insulating InP (100) substrate 1
Si concentration 2 × 10 ¹⁹ cm ^-3 , film thickness 0.5 μm 2
It was grown by molecular beam epitaxy at 0 ° C. After that, a Si ₃ N ₄ film (film thickness 30n is formed by a chemical vapor deposition method).
m) 3 was deposited and the Si ₃ N ₄ film 3 was left only in the parasitic collector region by photolithography and buffered hydrofluoric acid (see FIG. 2).

After that, the sample was reintroduced into the molecular beam epitaxy apparatus, and the highly doped n-type InGaAs layer 2 was formed at 530 ° C.
The natural oxide film on the surface was removed. Then, on the highly-doped n-type InGaAs layer 2 and the Si ₃ N ₄ film 3, the highly-doped n-type
-Type InGaAs layer (InAs molar ratio 0.53, Si concentration 2 × 10 ¹⁹ cm ⁻³ , film thickness 0.2 μm) 4, n-type InGa
As layer (InAs molar ratio 0.53, Si concentration 2 × 10 ¹⁶
cm ^-3 , film thickness 0.4 μm) 5, highly doped p-type InGaA
s layer (InAs molar ratio 0.53, C concentration 5 × 10 ¹⁹ cm
^-3 , film thickness 30 nm) 6, n-type InP layer (Si concentration 3x
10 ¹⁷ cm ⁻³ , film thickness 0.2 μm) 7, highly doped n-type In
GaAs layer (InAs molar ratio 0.53, Si concentration 2x1
0 ¹⁹ cm ⁻³ , film thickness 0.1 μm) 8 was grown. At this time, it was confirmed by reflection high-energy electron diffraction and cross-sectional electron microscope observation that a single crystal was epitaxially grown on the highly-doped n-type InGaAs layer 2 and a polycrystal 9 was deposited on the Si ₃ N ₄ film 3. (See FIG. 3). The layer 5 is inserted for the purpose of reducing the resistance at the regrowth interface, and may be omitted when cleaning the surface of the layer 2 using hydrogen radicals or the like.

After that, a WSi film (film thickness 0.3 μm) was deposited on the entire surface of the sample by the sputtering method, and the WSi emitter electrode 10 was processed by photolithography and dry etching. Highly doped n-type InGaA using methane and chlorine with this emitter electrode 10 as a mask
The s layer 8 was dry-etched and the n-type InP layer 7 was wet-etched using a hydrochloric acid aqueous solution to expose the surface of the highly-doped p-type InGaAs layer 6. afterwards,
A SiO ₂ film was deposited on the entire surface, and a SiO ₂ sidewall 11 was formed by photolithography and dry etching. Then, the base electrode (Au (100 nm) / Pt (50 n
m) / Ti (50 nm) / Pt (10 nm)) 12 by electron beam evaporation and lift-off, and the emitter electrode 10 and the base electrode 12 deposited on the SiO ₂ side wall 11 are removed by milling.
A minute alloy was performed (see FIG. 4).

Finally, as shown in FIG. 1, the base electrode 1
2 is used as a mask and the highly doped p-type InGaAs layer 6 and n-type I are used.
The nGaAs layer 5 and the highly-doped n-type InGaAs layer 4 are removed by wet etching using a mixed solution of phosphoric acid, hydrogen peroxide, and pure water, and the collector electrode (AuGe (250n
m)) 13 is deposited by resistance heating and lift-off,
Alloy at 350 ° C. for 30 minutes to perform npn type InP /
An InGaAs heterojunction bipolar transistor was produced. As a result of measuring the resistivity of the polycrystalline region, it was confirmed that the whole laminated film had a value exceeding 1 MΩcm.

According to the present embodiment, the parasitic collector region and the base electrode lead-out region (hereinafter referred to as the external base region) become a high resistance polycrystalline semiconductor, resulting in depletion of carriers. As a result, no leak current or crack occurs. Since the base-collector capacitance can be reduced, the reverse breakdown voltage of the base-collector and the maximum oscillation frequency of InP / InGa are high.
There is an effect that an As heterojunction bipolar transistor and a semiconductor device having the As heterojunction bipolar transistor can be manufactured.

Example 2 Instead of the n-type InP layer 7 in Example 1, InAl was used.
As layer (InAs molar ratio 0.52, Si concentration 3 × 10 ¹⁷
cm ^-3 , film thickness 100 nm) using npn type InAl
As / InGaAs heterojunction bipolar transistors were fabricated on a semi-insulating InP (100) substrate. As a result, the collector capacitance was reduced by 30% and the maximum oscillation frequency was increased by 43% to exceed 200 GHz, as in Example 1. The value was obtained. In addition, the reverse breakdown voltage of the base and collector is
The same high value of 10 V was obtained as in the case where the layers 3 and 9 were not embedded.

According to this embodiment, the parasitic collector region and the external base region become a high-resistance polycrystalline semiconductor and carriers are depleted. As a result, the base-collector capacitance can be reduced without the occurrence of leak current or cracks. High collector reverse breakdown voltage and high maximum oscillation frequency InAlA
s / InGaAs heterojunction bipolar transistor,
Also, there is an effect that a semiconductor device having the same can be manufactured.

[0016]

According to the present invention, the parasitic collector region becomes a high-resistance polycrystalline semiconductor and carriers are depleted. As a result, the base-collector capacitance can be reduced without the problem of lowering the base-collector breakdown voltage. It is possible to manufacture a compound semiconductor heterojunction bipolar transistor having a high power consumption and a semiconductor device having the same.

[Brief description of drawings]

FIG. 1 is a vertical sectional structural view of an InP / InGaAs heterojunction bipolar transistor according to the present invention.

FIG. 2 is a vertical sectional structural view showing a method for manufacturing an InP / InGaAs heterojunction bipolar transistor according to the present invention.

FIG. 3 is a longitudinal sectional structural view showing a step following that in FIG. 2 in the method for manufacturing an InP / InGaAs heterojunction bipolar transistor according to the present invention.

FIG. 4 is a longitudinal sectional structural view showing a step that follows the step in FIG. 3 in the method for manufacturing an InP / InGaAs heterojunction bipolar transistor according to the present invention.

FIG. 5 is a vertical sectional structural view of an InP / InGaAs heterojunction bipolar transistor according to a first conventional technique.

FIG. 6 is a vertical sectional structural view of an InP / InGaAs heterojunction bipolar transistor according to a second conventional technique.

[Explanation of symbols]

1 ... Semi-insulating InP substrate, 2, 4, 8 ... Highly doped n-type I
nGaAs, 3 ... Si ₃ N ₄ , 5 ... n-type InGaAs, 6
... highly doped p-type InGaAs, 7 ... n-type InP, 9 ... polycrystalline, 10 ... WSi, 11 ... SiO ₂ sidewall, 12 ... Au
/ Pt / Ti / Pt, 13 ... AuGe, 14 ... Oxygen ion implantation area, 15 ... SiO ₂ , 16 ... Leak current generation area.

Claims (6)

[Claims] 1. A single crystal semiconductor substrate, a first conductive type first conductive layer formed on the substrate, and a first conductive type formed on the first conductive layer and having a desired shape. A second conductive layer made of the compound single crystal semiconductor of, and on the first conductive layer,
A laminated film in which a first insulating layer made of an insulating material and a second insulating layer made of a compound polycrystalline semiconductor are sequentially formed so as to surround the periphery of the second conductive layer, and on the second conductive layer. Formed,
A third conductive layer made of a compound single crystal semiconductor having a second conductivity type opposite to the first conductivity type, and a compound single crystal formed on the third conductive layer and forming the third conductive layer A fourth conductive layer having a forbidden band width different from that of the semiconductor and made of a compound single crystal semiconductor having the first conductivity type, and connected to the first conductive layer, the third conductive layer, and the fourth conductive layer, respectively. Semiconductor device having a heterojunction bipolar transistor having a first electrode, a second electrode, and a third electrode that are formed. 2. The semiconductor device according to claim 1, wherein the first insulating layer is made of Si ₃ N ₄ . 3. The thickness of the first insulating layer is 10 nm or more 1
The semiconductor device according to claim 2, wherein the semiconductor device has a thickness of 00 nm or less. 4. The polycrystalline grain size in the second insulating layer is 1
The semiconductor device according to claim 3, wherein the thickness is 00 nm or less. 5. The second conductive layer and the second insulating layer are n
The third conductive layer is made of InGaAs having a type impurity concentration of 2 × 10 ²⁰ cm ⁻³ or less, and the p-type impurity concentration is 5 × 10 ¹⁹ cm ^−3.
The following InGaAs is comprised, It is characterized by the above-mentioned.
13. The semiconductor device according to claim 1. 6. The fourth conductive layer is InP or InA.
The semiconductor device according to claim 5, wherein the semiconductor device is made of 1As.