JPH09319725A - Eprom microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the availability of an OTP microcomputer and the user's development efficiency by using an unused area of the OTP microcomputer as a 2nd program area. SOLUTION: A program start address setting circuit 103 transfers the selected 2nd program start address to a program counter 111 of a CPU 101 and updates the address. The CPU 101 reads the program stored in a 2nd program storage area of the 2nd program start address shown by the counter 111 out of an EPROM 105 and then successively carries out the program after storing it temporarily in an instruction register 113. The programs can be written into a 1st program storage area and a 2nd program storage area (conventional unused area) of the EPROM 105 in the same way as a case where a portogram is written into an EPROM built in a conventional OTP microcomputer. Thus, an unused area of the conventional OTP microcomputer can be used as the 2nd program storage area.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an MROM (Mask R
EPROM (Erasable and Programmable ROM) that supports microcomputer program development
Regarding microcomputers.

[0002]

2. Description of the Related Art EPROM is a non-volatile memory in which all information once written can be erased by irradiating it with ultraviolet rays and can be electrically rewritten. This E
Among the microcomputers with a built-in PROM (hereinafter referred to as "EPROM microcomputers"), a plastic package without a window for erasing UV rays (a cheaper package than a package with a window)
An OTP (One TiT) that is sealed inside and can write a program that can be executed by a PROM writer etc. only once
me Program) Currently commercialized as a microcomputer.

The OT in a microcomputer with a built-in program
The role of the P-microcomputer is to have the same peripheral functions and an MROM built-in microcomputer (hereinafter, MROM built-in) which has an MROM having a program memory size equal to or smaller than that.
It is described as "MROM microcomputer". ) To support the development of programs stored in.

However, the OTP microcomputer is an MRO.
The development cost and product unit price are higher than those of the M microcomputer.
The number of products shipped is also small. Therefore, the conventional OTP microcomputer has a program memory of the largest capacity in the derivative product group, and supports the MROM microcomputer having a program memory equal to or smaller than the memory size.

14 and 15 show an example of a program storage area of the MROM microcomputer and the EPROM microcomputer supporting it.

In this derivative group, the OTP microcomputer having a program storage area of 32 Kbytes is shown in FIG.
An MROM microcomputer having a program storage area of 32 Kbytes shown in (a), a MROM microcomputer of 24 Kbytes shown in FIG. 14 (b), a MROM microcomputer of 16 Kbytes shown in FIG. 15 (c), and 12 Km shown in FIG. 15 (d). Supports the development of byte MROM microcomputers.

As is clear from FIGS. 14 and 15, the 32 Kbyte MROM microcomputer shown in FIG.
When the 2 Kbyte OTP microcomputer is used, there is no unused area in the program storage area.
8 for the 24-Kbyte MROM microcomputer shown in 4 (b)
The unused area of K bytes is 16 Kbytes of unused area in the 16-Kbyte MROM microcomputer shown in FIG. 15C, and 20 Kbytes of unused area is shown in the 12-Kbyte MROM microcomputer shown in FIG. 15D. You can see that it is occurring.

[0008]

However, when a user who develops a small-capacity program develops using an OTP microcomputer having a large-capacity program storage area, the program of the OTP microcomputer is as described above. The following problems have occurred because a large and useless unused area occurs in the storage area.

In the conventional OTP microcomputer, an executable program can be written only once. because,
It is theoretically possible to write a program in a different program storage area by changing the storage address, but in reality, is the program start address determined in advance?
Alternatively, since the program start address can be set only once, it is very difficult to execute a program having a start address that is not the program start address.

Therefore, if there is an error in the program written in the OTP microcomputer, it must be abandoned while leaving an unused area in the program storage area, which leads to an increase in development cost.

For this reason, a method has been proposed in which a different program from the originally intended content is developed in advance when the program is created and stored at the beginning of the program. However, in this method, the user needs to save the extra program. Since it is necessary to create and verify it, the burden on the user is increased, and the reliability of the entire program to be developed is reduced.

[0012] On the other hand, although it is possible for the microcomputer supplier to provide a lineup of variations according to the memory size of the MROM microcomputer, as described in the prior art, the number of OTP microcomputers used is not large. The lineup of OTP microcomputers corresponding to each memory size involves a great deal of development effort and delays the development of new microcomputer products.

In general, writing and collating data in the EPROM circuit in the EPROM built-in microcomputer is performed by
It is executed using a writing device.

FIG. 16 is a diagram for explaining writing of data to the conventional microcomputer 1000 with built-in EPROM. As shown in FIG. 16, the conventional EPROM built-in microcomputer 16
Writing data to 0 is performed by an external writing device 166.
Under the control of,
Data input / output terminal 162 and input / output data bus 165
To the EPROM built-in microcomputer 160 side in parallel via the
Write this data into 164 in parallel. afterwards,
The EPROM circuit 16 is connected via the input / output data bus 165 (that is, the bidirectional data bus) used at the time of writing.
4 outputs data in parallel (as parallel data) to the external writing device 166, collates the written data with the data written and read in the EPROM 164, and evaluates the written data. .

However, in the conventional EPROM built-in microcomputer 160, the external writing device 166 is used to
The collation of data writing to the EPROM circuit 164 has been executed via the parallel address input terminal 161 and the data input / output terminal 162. And EPRO
After the M built-in microcomputer 160 is mounted on the application board (not shown), the address input terminal 161 and the data input / output terminal 162 have the EPROM built-in microcomputer 16
This input / output port may be connected to another circuit because it is used as an input / output or control operation port different from the input / output port used when writing data to 0. Therefore, while the EPROM built-in microcomputer 160 is mounted on the application board, the address input terminal 16
EP through data via 1 and data input / output terminal 162
It cannot be transferred to ROM 164. Therefore, before mounting the EPROM built-in microcomputer 160 on the application board, there is a problem that the writing data must be collated by using the external writing device 166.

Alternatively, after the EPROM built-in microcomputer 160 is mounted on the application board, an external writing device 166 is provided.
When performing write data verification using
After the OM built-in microcomputer 160 is removed from the application board, the write data must be verified, and in this case, there is a problem that a great deal of time and man-hours are required for removal and data writing.

Further, when the external writing device 166 completes the writing of the data to the microcomputer 160 with built-in EPROM and the collation of the data, when the microcomputer 160 with built-in EPROM is mounted on the application board, it is mounted by using solder or the like. High heat is generated, and the stress of the high heat may reduce the reliability of the EPROM built-in microcomputer 160.

Further, the conventional microcomputer 1 with a built-in EPROM
In 60, data could be written to the built-in EPROM circuit 164 only once.
Before the PROM built-in microcomputer was mounted, the data writing process was performed. As a result, if the data once written is incorrect, the correct data cannot be written again and is discarded. In particular, the data was not written after the EPROM built-in microcomputer was mounted on the application board.

The present invention has been made in view of the problems of the conventional microcomputer with built-in EPROM, and its purpose is to use an unused area of the OTP microcomputer as a second program area. , OT
The program storage area of the EPROM built into the P-microcomputer is utilized as effectively as possible, thereby improving the utility value of the OTP microcomputer and the development efficiency for the user.
An object of the present invention is to provide an EPROM microcomputer that can meet the requirements of the TP microcomputer lineup.

Further, even after the microcomputer with built-in EPROM is mounted on the application board, data can be written and collated with respect to the microcomputer with built-in EPROM, so that the user's system development efficiency and system development cost can be reduced. It is to provide a built-in microcomputer.

[0021]

In order to achieve the above object, the invention according to claim 1 uses an E as a program memory.
Microcomputer with built-in EPROM (EPRO with built-in PROM)
E) used as an OTP microcomputer capable of writing a program only once.
In the PROM microcomputer, when an unused area occurs in the program storage area of the program memory, at least one program is written and executed in the unused area.

Therefore, according to the configuration of the invention described in claim 1, since the program can be written and executed in the unused area of the program memory, the program storage area of the program memory can be used to the maximum extent. You can

According to a second aspect of the present invention, there is provided an EPROM microcomputer including an EPROM as a program memory, which is used as an OTP microcomputer capable of writing a program only once. A program start address memory having an area for storing; and a selection signal generation circuit for generating a selection signal for selecting a desired program start address from a plurality of program start addresses stored in the program start address memory. If an unused area occurs in the program storage area of the program memory, at least one program is written in the unused area, and the program start address of the written program is stored in the program start address memory. Storing, selecting the program start address by generating selecting signals of the selection signal generating circuit, and executes the written program.

Therefore, according to the configuration of the invention described in claim 2, the program start address stored in the program start address memory is selected by the selection signal generated by the selection signal generation circuit described above, and the program memory is not yet stored. Since the program stored in the used area can be executed, the program storage area of the program memory can be used to the maximum extent.

According to a third aspect of the present invention, there is provided an EPROM microcomputer having an EPROM as a program memory, which stores a program start address in the EPROM microcomputer used as an OTP microcomputer capable of writing a program only once. The data storage area is divided into a plurality of blocks, and every time the program start address is written in one block, the other blocks in which the program start address has already been written are invalidated, and the program start written in the one block is started. A program start address memory circuit having a program start address memory for validating an address is provided, and when an unused area occurs in a program storage area of the program memory, at least one program is written in the unused area. The program start address of the written program is stored in the program start address memory as a valid address, and the program start address memory circuit executes the written program by setting the valid program start address. It is characterized by doing.

Therefore, according to the configuration of the invention described in claim 3, the program start address memory circuit described above sets the program start address stored in the program start address memory and stores it in the unused area of the program memory. Since the stored program can be executed, the program storage area of the program memory can be used most effectively.

According to a fourth aspect of the present invention, in the EPROM microcomputer according to the second or third aspect, the program start address of the written program is added or subtracted as a correction address with respect to the address input to the program memory. It is characterized by doing.

Therefore, according to the configuration of the invention described in claim 4, the program start address of the written program is added or subtracted as a correction address with respect to the address input to the program memory, which is different. The program can be executed in the program storage area without changing the immediate address or the like existing in the program.

According to a fifth aspect of the present invention, in the EPROM microcomputer according to the first to fourth aspects, serial address data input from an address input terminal is converted into parallel address data, and the converted parallel address data is converted into the EPROM. A first serial / parallel conversion means for supplying to the EPROM, and a second serial / parallel conversion means for converting the serial data input from the data input terminal into parallel data and supplying the converted parallel data to the EPROM. , Parallel / converting parallel data output from the EPROM into serial data
Further comprising serial conversion means and an onboard write mode determination circuit for determining whether or not the EPROM microcomputer is in an onboard write mode, and when the determination result of the onboard write mode determination circuit is the onboard write mode, The data writing operation into the EPROM is carried out via the first serial / parallel conversion means, the second serial / parallel conversion means, and the parallel / serial conversion means.

Therefore, according to the EPROM microcomputer of the fifth aspect, even after the EPROM microcomputer is mounted on the application board, the rewriting of data to the EPROM circuit can be executed by using only extremely few external terminals.

According to a sixth aspect of the present invention, in the EPROM microcomputer according to the first to fourth aspects, the serial address data input from the address / data input terminal and the serial data are converted into parallel address data and parallel data, and the conversion is performed. Third serial / parallel conversion means for supplying the parallel address data and parallel data thus generated to the EPROM, parallel / serial conversion means for converting the parallel data output from the EPROM to serial data, and the EPROM microcomputer are turned on. An on-board write mode determination circuit for determining whether or not the board write mode is provided, and when the determination result of the on-board write mode determination circuit is the on-board write mode, the third serial / parallel conversion means and the Pa Barrel / via serial converting means which comprises carrying out a data write operation into the EPROM.

Therefore, according to the EPROM microcomputer of the sixth aspect, even after the EPROM microcomputer is mounted on the application board, the rewriting of data to the EPROM circuit can be executed by using only extremely few external terminals.

According to a seventh aspect of the present invention, in the EPROM microcomputer according to the first to fourth aspects, serial address data input from an address input terminal is converted into parallel address data, and the converted parallel address data is converted into the EPROM. First serial / parallel conversion means for supplying to the first serial / parallel conversion means, and serial data and parallel data input / output from the data input / output terminal are respectively converted into parallel data and serial data, and the converted parallel data and serial data are respectively converted into the above-mentioned EPRO
M, fourth serial / parallel conversion means for supplying to the outside of the EPROM microcomputer, and an onboard write mode determination circuit for determining whether or not the EPROM microcomputer is in the onboard write mode. When the determination result of the determination circuit is the on-board write mode, a data write operation into the EPROM is performed via the first serial / parallel conversion means and the fourth serial / parallel conversion means. And

Therefore, according to the EPROM microcomputer of the seventh aspect, even after the EPROM microcomputer is mounted on the application board, rewriting of data to the EPROM circuit can be executed using only a very small number of external terminals.

According to an eighth aspect of the present invention, in the EPROM microcomputer according to the first to fourth aspects, the serial address data input from the address / data input terminal and the serial data are converted into parallel address data and parallel data, and the conversion is performed. The third serial / parallel conversion means for supplying the parallel address data and the parallel data thus inputted to the EPROM, the parallel data outputted from the EPROM, and the parallel data inputted and converted are compared, and both are coincident with each other. A write / read data collation judging circuit for judging whether or not to carry out, and the EPRO
An on-board write mode determination circuit for determining whether the M microcomputer is in the on-board write mode,
The write / read data collation determination circuit performs collation determination between the parallel data output from the EPROM and the input and converted parallel data based on the determination of the on-board write mode determination circuit. Characterize.

Therefore, according to the EPROM microcomputer of the eighth aspect, even after the EPROM microcomputer is mounted on the application board, the rewriting of data to the EPROM circuit can be executed by using only extremely few external terminals.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION The EP of the embodiments of the present invention will be described below.
A ROM built-in microcomputer (or an EPROM microcomputer) will be described with reference to the drawings.

First Embodiment FIG. 1 is a block diagram showing the configuration of an EPROM microcomputer according to the first embodiment of the present invention. This EPROM
The microcomputer 100 includes a central processing unit (hereinafter, referred to as “CPU”) 101 that performs various arithmetic processes, and a CPU 101.
To a program start address setting circuit 103 for transferring a plurality of program start addresses to a program memory for storing a program to be processed by the CPU 101 (EPRO).
M) 105.

Here, the CPU 101 has a program counter 111 for holding the address of the program to be executed next by the CPU 101, and an instruction register 113 for temporarily holding the program read from the EPROM 105, and the program start address setting circuit 103. Is a program start address memory 107 having an area for storing a plurality of program start addresses and a desired program start address among the plurality of program start addresses stored in the program start address memory 107 And a selector 109 for selecting.

Further, as shown in FIG. 2, for example, 16K
When a byte MROM microcomputer is supported, the unused area of 16 Kbytes generated by the conventional 32 Kbyte OTP microcomputer is the EPROM 105 of the first embodiment.
Is set as the second program storage area.

Next, the EPROM according to the first embodiment
The operation of the microcomputer 100 will be described with reference to FIG.

First, the program is first stored in the first program storage area of the EPROM 105, and at the same time, the first address of the first program storage area is stored in the memory 1 of the program start address memory 107 in the program start address setting circuit 103. The first program start address is set.

Next, a selection signal generated by a predetermined circuit (not shown in the first embodiment) for selecting a program start address is input to the selector 109 and stored in the memory 1, for example. The first program start address that is present is selected.

Next, the selected first program start address is set to the program start address setting circuit 103.
Transfers to the program counter 111 in the CPU 101 and updates the address indicated by the program counter 111.

Next, the CPU 101 reads the program stored in the first program storage area at the first program start address indicated by the program counter 111 from the EPROM 105, temporarily stores it in the instruction register 113, and stores this program. Execute sequentially.

Next, the second program is stored in the second program storage area, and at the same time, the program start address memory 107 in the program start address setting circuit 103 is stored.
The second program start address, which is the start address of the second program storage area, is set in the memory 2 of FIG.

Next, the selection signal transmitted from the outside is input to the selector 109, whereby the second program start address stored in the memory 2 is selected.

Next, the program start address setting circuit 1
03 transfers the selected second program start address to the program counter 111 in the CPU 101, and updates the address indicated by the program counter 111.

Next, the CPU 101 reads the program stored in the second program storage area of the second program start address indicated by the program counter 111 from the EPROM 105, temporarily stores it in the instruction register 113, and stores this program. Execute sequentially.

The writing of the program to the first program storage area (conventional program storage area) and the second program storage area (conventional unused area) of the EPROM 105 is performed by the EP incorporated in the conventional OTP microcomputer.
The program can be written in the ROM by the same means.

Thus, the EP according to the first embodiment is
According to the ROM microcomputer 100, the unused area in the conventional OTP microcomputer can be used as the second program storage area.

At this point, the user can set an arbitrary program start address in the program start address memory 107, and the application range is widened and effective.
It is preferably composed of M. However, it can be easily realized by setting a fixed address by the MROM or the logic circuit. In this case, E
The start address of the program in the PROM 105 needs to match the fixed address.

Second Embodiment Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing the configuration of the EPROM microcomputer 300 according to the second embodiment of the present invention.

In FIG. 3, E according to the second embodiment
The PROM microcomputer 300 includes a selection signal generation circuit 301 that generates the selection signal shown in FIG. 1, and other configurations and operations are similar to those of the EPROM microcomputer 100 shown in FIG.

The selection signal generation circuit 301 is composed of an EPROM circuit, and has a memory circuit 303 in which a data storage area is divided into a plurality of blocks, and a write selector for selecting a write block among the plurality of blocks of the memory circuit 303. 305, a read selector 307 that selects a read block from a plurality of blocks of the memory circuit 303, a memory circuit 303, and a write selector 30.
5, and a control circuit 30 for controlling the read selector 307
9 and 9.

Now, the memory circuit 303 will be described in more detail.

The memory circuit 303 is a program start address of a desired program start address storage area of the EPROM 315 among a plurality of program start addresses (SA1, SA2, SA3, ...) Stored in the program start address memory 311. It is a stack-type memory that stores data for selecting, and as described above, the data storage area includes a plurality of blocks (D1, D2,
D3, D4). As shown in FIG. 4A, each block has a priority in write and read operations, and data operation is performed from a block with a higher priority. Here, priority is given to D1 to D4 in ascending order. The ranking is set to be low.

Next, the operation of the memory circuit 303 will be described with reference to FIG.

First, in the initial state, it is assumed that no data is written in all blocks. Hereinafter, a state in which no data is written in all the bits in the block is called "all" 0 "".

Next, in the first writing, data is written in D1 having the highest priority.

Next, in the second and subsequent writing, data is written in the block having the highest priority among the "all" 0 "" blocks in which no data has been written, and the block in which the data has already been written. Data is written in all the bits in, and the block is invalidated. Hereinafter, a state in which data is written in all the bits in the block is referred to as "all" 1 "".

Here, in the second writing, data is written to D2 having the highest priority among the blocks of "all" 0 "", and all bits are written to D1 in which data has already been written. Data is written to be “all“ 1 ””.

On the other hand, in the reading, the data is preferentially read from D1, and if "all" 1 "" is not satisfied, the data stored in the block is used as valid data for selecting the program start address storage area. Conversely, "all" 1 ""
If so, the data stored in the block is invalidated, the data of the block having the next highest priority is read, and it is similarly determined whether or not the data is valid. The valid data thus read is supplied to the program start address memory 311 as a program start address selection signal.

Next, the operation of the selection signal generation circuit shown in FIG. 3 will be described.

First, at the time of writing data, first, the data stored in the memory circuit 303 is changed to D1.
The data is sequentially read from, and if the read block is "all" 0 "", new data is written to the block.

Next, when some data is written in the read block, the data is written in all the bits of the block and set to "all" 1 "", and the data of the block having the next highest priority is read.

By repeating the above operation in sequence, a block in which no data is written is searched for and data is written to that block.

On the other hand, in the generation of the selection signal at the start of the program, the data is read from the block (D1) having a high priority as in the writing, and the read data is determined. When the read block is not "all" 1 "", the data stored in the block is determined to be valid, this data is transferred to the program start address memory 311 as a selection signal, and the desired program start address is selected and selected. The programmed program start address is set in the program counter 313.

Next, when the read block is "all" 1 "", the control circuit 309 regards the block as invalid, reads the data of the block having the next highest priority, and judges the data. To do.

The operation described above is repeated and the data of the effective block is used as the selection signal for the program start address memory 31.
Transfer to 1.

In this way, the EPROM microcomputer according to the second embodiment can generate the selection signal by the selection signal generation circuit 301, so that it is stored in the second program storage area in the program memory 315. The selected program can be selected and executed, and the program memory can be effectively used.

Third Embodiment Next, a third embodiment of the present invention will be described.

FIG. 5 is a block diagram showing the configuration of the EPROM microcomputer 500 according to the third embodiment of the present invention.

In FIG. 5, E according to the third embodiment
The PROM microcomputer 500 includes a selection signal generation circuit 501 which is another configuration example of the selection signal generation circuit 301 shown in FIG. 3, and other configurations and operations are the EPR shown in FIG.
It is similar to the OM microcomputer 300.

The selection signal generation circuit 501 is composed of an EPROM circuit, and the data storage area is divided into a plurality of blocks. The memory circuit 503 and the data of all the blocks of the memory circuit 503 are temporarily read, and the high priority data is read. To the control circuit 509 described later, a read shift register 505, a write shift register 507 for writing data to be newly written in the memory circuit 503 in a correct block, a memory circuit 503,
It has a control circuit 509 for controlling the read shift register 505 and the write shift register 507.

Next, the selection signal generation circuit 501 shown in FIG.
The operation of will be described. The configuration and operation of the memory circuit 503 are similar to those of the memory circuit 303 in FIG.

First, at the time of writing, first, the write data is stored in the area WSR1 in the write shift register 507, and further, all the data stored in each block of the memory circuit 503 is stored in the read shift register 505. Forward.

Next, each data of RSR1 to RSR4 transferred to the read shift register 505 is shifted by the read shift clock generated by the control circuit 509, and sequentially transferred to the control circuit 509 from the data of RSR1.

Next, the RSR transferred to the control circuit 509
When 1 is “all“ 0 ””, the data stored in WSR1 of the write shift register 507 is written to D1 in the memory circuit 503.

When the data transferred to the control circuit 509 is other than "all" 0 "", the control circuit 509 generates a write shift clock and changes the data stored in WSR1 of the write shift register 507 to WSR2. At the same time, the data is written in all the bits of D1 of the memory circuit 503 to be "all" 1 "".

Next, the control circuit 509 generates a read shift clock to write the shift register 50.
The data of RSR2 of No. 5 (shifted to RSR1 at this time) is transferred to the control circuit 503, and the data is judged.

Based on the result of the judgment, the above-mentioned operation is repeated to write the data in the correct block of the memory circuit 503.

On the other hand, the generation of the selection signal at the start of the program also transfers all the data in the memory circuit 503 to the read shift register 505 similarly to the write, and controls the read shift clock generated by the control circuit 509 in order from RSR1. The data is transferred to the circuit 509 and data is judged. When the data is "all" 1 "", the data is invalidated, and a read shift clock is generated to transfer the next data to the control circuit 509. When the data is other than "all" 1 "", the data is determined to be valid data and is transferred to the program start address memory 511 as a selection signal.

Based on the above operation, the EPROM microcomputer 500 according to the third embodiment can generate the selection signal by the selection signal generation circuit 501, so that it is stored in the second program storage area of the program memory. The stored program can be executed, and the program memory 515 can be used efficiently.

Fourth Embodiment Next, a fourth embodiment of the present invention will be described.

FIG. 6 is a block diagram showing the configuration of the EPROM microcomputer 600 according to the fourth embodiment of the present invention.

The EPROM microcomputer 600 according to the fourth embodiment is different from the EPROM microcomputer 300 according to the second embodiment in that a selection signal is sent by the data for selecting the program start address storage area stored in the memory circuit. The selection of the program start address, which was performed by the generation, is made the memory circuit as the program start address memory, and the judgment bit field or the stored address data to be described later is used to judge whether the stored data is valid or not. The determination is made by

In FIG. 6, E according to the fourth embodiment
The PROM microcomputer 600 is the selection signal generation circuit 3 of FIG.
3 is provided with a program start address memory circuit 601 in which the memory circuit 303 of FIG. 3 is used as a program start address memory.
EPROM microcomputer 3 according to the second embodiment shown in FIG.
The same as 00.

Program start address memory circuit 601
Is a program start address memory 603 configured by an EPROM circuit, the program start address storage area of which is divided into a plurality of blocks, and a write selector for selecting a storage area to be written in the program start address storage area of the program start address memory 603. 605
And a read selector 607 for selecting a storage area to be read out of the program start address storage area of the program start address memory 603, and a control circuit 609 for controlling the program start address memory 603, the write selector 605 and the read selector 607. There is.

Here, the program start address memory 6
03 will be described in more detail.

The program start address memory 603 is
This is a stack type memory, and as described above, the program start address storage area is divided into a plurality of blocks.

As shown in FIG. 7A, the individual program start address storage areas (SA1, SA2, SA3, S) are stored.
A4) has a priority in writing and reading operations, and data is operated from a storage area having a high priority. Here, the priority order is set to decrease from SA1 in ascending order.

Further, as shown in FIG. 7B, each storage area is composed of an address field A and a judgment bit field B. The address field A contains the program start address and the judgment bit field B contains the program start address. Stores the determination data whether the storage area is valid or not.

The function for determining whether the storage area is valid is
Although it is basically the same as the memory circuit of the second embodiment, the only difference is that the above-mentioned memory circuit targets all the bits of the stored data for judgment, whereas the program start of this embodiment is started. In the address memory, the judgment is made by the data of the judgment bit field B.

Next, the program start address memory 60
The operation of No. 3 will be described with reference to FIG.

First, in the initial state, it is assumed that no data is written in all storage areas.

Next, in the first writing, data is written in SA1 having the highest priority. Specifically, the program start address is written in the address field A.

Next, in the second and subsequent writing, the program start address is written in the storage area with the highest priority among the storage areas in which the program start address has not been written, and the storage area in which the address has already been written. "1" is written in the judgment bit field B of
The area is invalid.

Here, in the second write, the address is written to SA2, which has the highest priority in the storage area in which the program start address is not written in the address field A, and the address is already written in SA1. For "1" in the judgment bit field B
Is written.

On the other hand, in the read operation, SA1 is read first, and if the determination bit field B is not "1", the address stored in the storage area is used as the effective address. On the contrary, if it is "1", the address stored in the storage area is invalidated, the address of the storage area having the next highest priority is read, and it is similarly determined whether or not the address is valid.

Here, the address field A and the judgment bit field B are not divided and all the fields are set as the address field A, and it is judged by the judgment function of the memory circuit whether the data is valid or not. It is possible.

When the address thus read is valid, the control circuit 609 directly transfers the program start address to the program counter 613.

Fifth Embodiment Next, a fifth embodiment of the present invention will be described.

FIG. 8 is a block diagram showing the configuration of the EPROM microcomputer 800 according to the fifth embodiment of the present invention.

In FIG. 8, E according to the fifth embodiment is shown.
The PROM microcomputer 800 includes a program start address memory circuit 801 which is another example of the configuration of the program start address memory circuit 601 shown in FIG. 6, and other configurations and operations are the same as those of the fourth embodiment shown in FIG. EPR
It is similar to the OM microcomputer 600.

Program start address memory circuit 801
Is a program start address memory 803 which is composed of an EPROM circuit and whose data storage area is divided into a plurality of blocks, and addresses of all storage areas of the program start address memory 803 are temporarily read out, and control is performed from an address having a high priority. A read shift register 805 for transferring data to the circuit 809, and a write shift register 8 for writing an address newly written in the program start address memory 803 in a correct storage area.
07, and a control circuit 809 for controlling the program start address memory 803, the read shift register 805, and the write shift register 807.

The operation of writing data to the program start address memory 803, the operation of reading the effective program start address at the start of the program, and the setting of the program counter are the same as those described in the fourth embodiment.

Sixth Embodiment Next, an EPROM microcomputer according to a sixth embodiment of the present invention will be described.

FIG. 9 shows an EPRO according to the sixth embodiment.
3 is a block diagram showing a configuration of an M microcomputer 900. FIG.

The EPROM microcomputer 900 according to the sixth embodiment is the EPR microcomputer according to the second to fifth embodiments.
The OM microcomputers 300, 500, 600, 800 further program the program start address 909 with respect to the program address 907 supplied from the program counter 901.
Is added as a correction address, and the corrected address 911 generated by the adder 921 is included.
Is supplied to the address decoder of the program memory 905.

EPROM microcomputer 9 of the sixth embodiment
According to 00, the programs can be executed in different program storage areas without changing the immediate address or the like existing in the programs.

Seventh Embodiment Next, a seventh embodiment of the present invention will be described.

FIG. 10 shows an EPR according to the seventh embodiment.
3 is a block diagram showing a configuration of an OM microcomputer 1000. FIG.

This EPROM microcomputer 1000 includes an address input terminal 1001 and an EPROM microcomputer 1000.
Address serial / parallel conversion circuit 1002 for converting the serial data transmitted from the external writing device 1010 and input through the address input terminal 1001 into parallel data, and the data input terminal 1003.
And a write data serial / parallel conversion circuit 1004 for converting serial data input via the data input terminal 1003 into parallel data and supplying the parallel data to the EPROM circuit 1009, and parallel data read from the EPROM circuit 1009. A parallel / serial conversion circuit 1006 for reading, which converts the serial data into serial data and transmits the converted serial data from the data output terminal 1005 to, for example, the writing device 1100 outside the EPROM microcomputer 1000, and the data output terminal 10.
05, one to a plurality of mode setting terminals 1007 (only one mode setting terminal 1007 is shown in FIG. 10 as a representative), and by the mode setting signal input from this mode setting terminal 1007. On-board write determination circuit 1008 for determining the on-board write mode
Consists of

On-board write mode determination circuit 100
8 receives a mode setting signal via one to a plurality of mode setting terminals 1007, and determines whether the received mode setting signal is the onboard write mode. If the received mode setting signal is the onboard write mode, a mode / control signal is generated, and the address serial / parallel conversion circuit 1002, the write data serial / parallel conversion circuit 1004, and the read data parallel / serial conversion are performed. Circuit 1006, and EP
The generated mode / control signal is transmitted to the ROM circuit 1009, and these are set to the onboard write mode. After each of these circuits is set to the on-board write mode, the data input from the data input terminal 1003 is written to the corresponding location in the EPROM circuit 1009 based on the address input from the address input terminal 1001. .

After writing the data, the data is read in parallel from the EPROM circuit 1009, the obtained parallel data is converted into serial data by the parallel / serial conversion circuit 1006, and the EPROM microcomputer 1000 is read.
To a circuit external to the writing device 1010, for example. The writing device 1010 evaluates the serial data transmitted from the EPROM microcomputer 1000 that has written the data, and based on the evaluation result, the EP data is written.
A continuation or a stop of the writing operation to the ROM circuit 1009 is selected.

Thus, the EPRO of the seventh embodiment is
Since the M microcomputer 1000 has a configuration capable of serially inputting and outputting addresses and data, E
Data can be rewritten to the PROM circuit.

Eighth Embodiment Next, an eighth embodiment of the present invention will be described.

FIG. 11 shows an EPR according to the eighth embodiment.
3 is a block diagram showing a configuration of an OM microcomputer 1100. FIG.

In the EPROM microcomputer 1100 of the eighth embodiment, the address input terminal 1001 and the data input terminal 1003 in the EPROM microcomputer 1000 of the seventh embodiment are formed by one address / data input terminal 1101. The serial / parallel conversion circuit for address 1002 and the serial / parallel conversion circuit for write data 1004 are formed as one serial / parallel conversion circuit 1102. The other components are the same as the components of the EPROM microcomputer 1000 of the seventh embodiment, and therefore, the same reference numerals are used here and their description is omitted.

As in the above-mentioned configuration, this EPROM microcomputer 1100 has a configuration in which the input address bus and the input data bus are commonly used.

On-board write mode determination circuit 100
8 is the operation of the EPROM microcomputer 10 of the seventh embodiment.
It is similar to the case of 00. That is, E of the eighth embodiment
In the PROM microcomputer 1100, the EPROM circuit 100
The data and address written in 9 are serially time-divided EPR via the address / data input terminal 1101.
It is input to the OM microcomputer 1100. The address and data serially input by time division are converted into parallel data by the serial / parallel conversion circuit 1102, and E is passed through the address bus and data bus constructed in parallel.
The data is supplied to the PROM circuit 1009 and written in the location designated by the address data.

After the writing operation to the EPROM circuit 1009 is completed, as in the case of the EPROM microcomputer 1000 of the seventh embodiment, the EPROM circuit 1009 is
Data is read out in parallel, the obtained parallel data is converted into serial data by the parallel / serial conversion circuit 1006, and the serial data is output to a circuit external to the EPROM microcomputer 1100, for example, the writing device 1010. This writing device 1010 is an EPRO that has written data.
The serial data transmitted from the M microcomputer 1100 is evaluated, and the EPROM circuit 10 is evaluated based on the evaluation result.
Select whether to continue or cancel the write operation for 09.

Thus, the EPRO of the eighth embodiment is
In the M microcomputer 1100, the EPRO of the seventh embodiment is used.
The number of input terminals can be reduced as compared with the case of the M-microcomputer 1000. In addition, since the configuration is such that addresses and data can be input / output serially, E
Data can be rewritten to the PROM circuit.

Ninth Embodiment Next, a ninth embodiment of the present invention will be described.

FIG. 12 shows an EPR according to the ninth embodiment.
3 is a block diagram showing the configuration of an OM microcomputer 1200. FIG.

The EPROM microcomputer 1200 of the ninth embodiment is the EPROM microcomputer of the seventh embodiment described above.
The data input terminal 1003 and the data output terminal 1005 in the microcomputer 1000 are formed by one data input / output terminal 1203, and the data input serial / parallel conversion circuit 1004 and the data output parallel / serial conversion circuit 1006 are formed into one serial. -It has a configuration formed as a parallel conversion circuit 1204. Other components are the EPROM microcomputer 1 of the seventh embodiment.
Since they are the same as those of 000, the same numbers are used here and their explanations are omitted.

As in the above-mentioned configuration, the EPROM microcomputer 1200 has the input data bus and the output data bus configured as one common bidirectional data bus.

On-board write mode determination circuit 100
8 is the operation of the EPROM microcomputer 10 of the seventh embodiment.
It is similar to the case of 00. That is, E of the ninth embodiment
In the PROM microcomputer 1200, the EPROM circuit 100
Data to be written in or read from the writing device 1010 is serially input to the EPROM microcomputer 1200 side via the bidirectional data bus and the data input / output terminal 1203, and is serially transmitted from the EPROM microcomputer 1200 side to the writing device 1010.

After the data write operation to the EPROM circuit 1009 is completed, the EPR of the seventh embodiment is performed.
Similar to the case of the OM microcomputer 1000, data is read in parallel from the EPROM circuit 1009, the obtained parallel data is converted into serial data by the serial / parallel conversion circuit 1204, and the EPROM microcomputer 1200 is read.
To a circuit external to the writing device 1010, for example. The writing device 1010 evaluates the serial data transmitted from the EPROM microcomputer 1200 in which the data is written, and based on the evaluation result, the EPROM
A continuation or a stop of the write operation for the circuit 1009 is selected.

Thus, the EPRO of the ninth embodiment is
In the M microcomputer 1200, the EPRO of the seventh embodiment is used.
The number of input terminals can be reduced as compared with the case of the M-microcomputer 1000. In addition, since the configuration is such that addresses and data can be input / output serially, E
Data can be rewritten to the PROM circuit.

Tenth Embodiment Next, a tenth embodiment of the present invention will be described.

FIG. 13 shows an EP according to the tenth embodiment.
3 is a block diagram showing the configuration of a ROM microcomputer 1300. FIG.

In the EPROM microcomputer 1300 of the tenth embodiment, the EPR of the seventh embodiment described above is used.
Address input terminal 100 in OM microcomputer 1000
1 and the data input terminal 1003 to one address /
The data input terminal 1101 is formed, the address serial / parallel conversion circuit 1002 and the write data serial / parallel conversion circuit 1004 are formed as one serial / parallel conversion circuit 1102, and the input address / data bus (serial), EPR via serial / parallel conversion circuit 1102 and input address bus (parallel) and input data bus (parallel)
The data supplied to the OM circuit 1009 and the EPRO already
This data is evaluated by comparing it with the data written in the M circuit 1009, and if it matches the expected value, the EPROM
A write data / read data collation determination circuit 1304 that determines that data has been normally written to the circuit 1009 and generates a specific code, and a specific code generated by the write data / read data collation determination circuit 1304 is the EPROM microcomputer 1300. EPROM microcomputer 130 for outputting to the outside of the device, especially to the writing device 1010
The comparison result output terminal 1303, which is a 0 terminal, is provided. The other components are the same as the components of the EPROM microcomputer 1000 of the seventh embodiment, and therefore, the same reference numerals are used here and their description is omitted.

In the EPROM microcomputer 1300 having the above-described structure, the onboard write mode determination circuit 1008 includes one to a plurality of mode setting terminals 10.
07 (in the tenth embodiment, the mode setting terminal 1007
Will be described for one case. ), And determines whether the received mode setting signal is the on-board write mode. If the received mode setting signal is the onboard write mode, a mode / control signal is generated in the onboard write mode determination circuit 1008, the serial / parallel conversion circuit 1102, the write data / read data comparison determination circuit 1304, The generated mode / control signal is transmitted to the EPROM circuit 1009, and these are set to the onboard write mode. After each of these circuits is set to the on-board write mode, data is written in a corresponding place in the EPROM circuit 1009 based on the address and data input from the address / data input terminal 1101, and at the same time, write data / data is written. It is also held in the read data collation determination circuit 1304. After the data writing operation is completed, the data read from the EPROM circuit 1009 is compared with the data held in the write data / read data collation determination circuit 1304 and collated. If both data match as a result of collation, E
It is determined that the data is normally written in the PROM circuit 1009, and the write data / read data collation determination circuit 1304 generates a specific code. The generated specific code is transmitted to the EP through the collation result output terminal 1303.
It is transmitted to a circuit external to the ROM microcomputer 1300, for example, the writing device 1010. The writing device 1010 receives this specific code, and based on this specific code, an EP
A continuation or a stop of the writing operation to the ROM circuit 1009 is selected.

As described above, in the EPROM microcomputer 1300 of the tenth embodiment of the present invention, the conventional EPROM
Microcomputer and EPRO according to the seventh embodiment of the present invention
The number of input terminals can be reduced as compared with the case of the M-microcomputer 1000. In addition, since the configuration is such that addresses and data can be input / output serially, E
Data can be rewritten to the PROM circuit.

[0138]

As described above, the EPRO of the present invention
According to the M microcomputer, an executable program E which can be executed only once by the conventional EPROM microcomputer.
When there is an unused area in the program storage area for writing to the PROM, the executable program can be written in that area, so that the utility value of the EPROM microcomputer can be improved.

Further, according to the EPROM microcomputer of the present invention, even when there is an error in the written program, if there is an unused area in the program storage area,
Furthermore, since the program can be written and executed in the unused area, the development efficiency of the MROM microcomputer can be improved.

Further, according to the EPROM microcomputer of the present invention, since the address and data can be input / output serially, the EPROM microcomputer is not removed from the application board even after being mounted on the application board, and the unused area in the EPROM is not removed. On the other hand, there is an effect that data can be rewritten.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an EPROM microcomputer according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a program storage area of the EPROM shown in FIG.

FIG. 3 is a block diagram showing a configuration of an EPROM microcomputer according to a second embodiment of the present invention.

FIG. 4 is a diagram for explaining the memory circuit shown in FIG.

FIG. 5 is a block diagram showing a configuration of an EPROM microcomputer according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an EPROM microcomputer according to a fourth embodiment of the present invention.

FIG. 7 is a diagram for explaining the program start address memory shown in FIG.

FIG. 8 is a block diagram showing a configuration of an EPROM microcomputer according to a fifth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of an EPROM microcomputer according to a sixth embodiment of the present invention.

FIG. 10 is an EPROM according to a seventh embodiment of the present invention.
It is a block diagram which shows the structure of a microcomputer.

FIG. 11 is an EPROM according to an eighth embodiment of the present invention.
It is a block diagram which shows the structure of a microcomputer.

FIG. 12 is an EPROM according to a ninth embodiment of the present invention.
It is a block diagram which shows the structure of a microcomputer.

FIG. 13 is an EPRO according to a tenth embodiment of the present invention.
It is a block diagram which shows the structure of M microcomputer.

FIG. 14: MROM microcomputer and EP supporting it
It is a figure which shows an example of the program storage area of a ROM microcomputer.

FIG. 15: MROM microcomputer and EP supporting it
It is a figure which shows another example of the program storage area of a ROM microcomputer.

FIG. 16 is a diagram illustrating writing of data to a conventional microcomputer with built-in EPROM.

[Explanation of symbols]

101 CPU 103 Program Start Address Setting Circuit 105, 315, 515, 613, 813, 905 Program Memory (EPROM) 107, 311, 511, 603, 803 Program Start Address Memory 109 Selector 111, 313, 513, 611, 811, 901 Program counter 113 Instruction register 301, 501 Selection signal generation circuit 303, 503 Memory circuit 305, 605 Write selector 307, 607 Read selector 309, 509, 609, 809 Control circuit 505, 805 Read shift register 507, 807 Write shift register 601, 801 Program start address memory circuit 615 Program start address 617 Address bus 903 Adder 907 Program address 909 Program start address 911 Corrected address 1001 Address input terminal 1002 Serial / parallel conversion circuit 1003 Data input terminal 1004 Serial / parallel conversion circuit 1005 Data output terminal 1006 Parallel / serial conversion circuit 1007 Mode setting terminal 1008 Onboard write mode determination circuit 1009 EPROM circuit 1010 Writing device 1101 Address / data input terminals 1002, 1004, 1102, 1204 Serial /
Parallel conversion circuit (serial / parallel conversion means) 1203 Data input / output terminal 1006 Parallel / serial conversion circuit (parallel / serial conversion means) 1008 Onboard write mode determination circuit 1303 Collation result output terminal 1304 Write data / read data collation determination circuit

Claims (8)

[Claims] 1. An EPRO in which a program memory is stored
In an EPROM built-in microcomputer (EPROM microcomputer) that is used as an OTP microcomputer that has a built-in M and can write a program only once, if an unused area occurs in the program storage area in the program memory, A writing means for writing at least one program in an unused area; a selecting means for selecting a program stored in the program memory; and an executing means for executing the program selected by the selecting means. EPROM microcomputer. 2. An EPRO in which a program memory is stored
A program start address memory having an area for storing a plurality of program start addresses in an EPROM built-in microcomputer (EPROM microcomputer) used as an OTP microcomputer capable of writing a program only once, A selection signal generation circuit for generating a selection signal for selecting a desired program start address from a plurality of program start addresses stored in the start address memory; and an unused area in the program storage area in the program memory When at least one program is written in the unused area, the program start address of the written program is stored in the program start address memory, and the selection signal generated by the selection signal generation circuit is used. The above And selecting means for selecting the program start address, and executes a program represented by the selected the program start address in said selecting means EP
ROM microcomputer. 3. An EPROM microcomputer having a built-in EPROM as a program memory and used as an OTP microcomputer capable of writing a program only once, has a plurality of data storage areas for storing a program start address. Each time a program start address is written in a block of the plurality of blocks, the other blocks in which the program start address has already been written are invalidated, and the program start address written in the block is A program start address memory circuit to be valid, and when an unused area occurs in a program storage area in the program memory and at least one program is written in the unused area, the written program EPROM microcomputer and executes the written program by setting the program start address. 4. The program memory has an area for storing a program start address of a program stored in the program memory, and the EPROM microcomputer has the program start address with respect to an address supplied to the program memory. 4. The addition / subtraction means for adding or subtracting as a correction address is further provided, and the address obtained by the addition / subtraction means is supplied to the program memory as the program start address. EPROM microcomputer. 5. Serial address data input from an address input terminal is converted into parallel address data,
The converted parallel address data is converted into the EPRO.
First serial / parallel conversion means for supplying to M and second serial / parallel conversion means for converting the serial data input from the data input terminal into parallel data and supplying the converted parallel data to the EPROM. And parallel / serial conversion means for converting parallel data output from the EPROM into serial data and outputting the converted serial data from an external terminal, and determining whether the EPROM microcomputer is in an on-board write mode. An on-board write mode determination circuit is further provided, and when the determination result of the on-board write mode determination circuit is an on-board write mode, the first serial / parallel conversion means and the second serial / parallel conversion means, the parallel / Via serial conversion means The EPROM microcomputer according to any one of claims 1 to 4, wherein a data write operation to the EPROM is performed. 6. A third address for converting serial address data and serial data input from an address / data input terminal into parallel address data and parallel data, and supplying the converted parallel address data and parallel data to the EPROM. Serial / parallel conversion means, parallel / serial conversion means for converting parallel data output from the EPROM into serial data and outputting the converted serial data from an external terminal, and whether the EPROM microcomputer is in an on-board write mode. An on-board write mode determination circuit for determining whether or not the third serial / parallel conversion means and the parallel / serial circuit are provided when the determination result of the on-board write mode determination circuit is an on-board write mode. 5. The EP according to any one of claims 1 to 4, wherein a data writing operation into the EPROM is carried out through a converting means.
ROM microcomputer. 7. The serial address data input from the address input terminal is converted into parallel address data,
The converted parallel address data is converted into the EPRO.
First serial / parallel conversion means for supplying to M, serial data and parallel data input / output from the data input / output terminal are converted into parallel data and serial data, respectively, and the converted parallel data and serial data are respectively converted. EPROM, EPROM
Fourth serial / parallel conversion means to be supplied to the outside of the microcomputer, and an onboard write mode judgment circuit for judging whether or not the EPROM microcomputer is in the onboard write mode, the judgment of the onboard write mode judgment circuit When the result is an on-board write mode, a data write operation in the EPROM is performed via the first serial / parallel conversion means and the fourth serial / parallel conversion means. An EPROM microcomputer described in 1 to 4. 8. A third address for converting serial address data and serial data input from an address / data input terminal into parallel address data and parallel data, and supplying the converted parallel address data and parallel data to the EPROM. A serial / parallel conversion means, a parallel data output from the EPROM, and a write / read data collation determination circuit that compares the parallel data input and converted and determines whether the two match. An EPROM microcomputer further comprises an onboard write mode determination circuit for determining whether or not the write / read data collation determination circuit determines whether the EPROM microcomputer is in the onboard write mode determination circuit based on the determination of the onboard write mode determination circuit. The above-mentioned output The EPROM microcomputer according to any one of claims 1 to 4, wherein collation determination is performed between the parallel data and the parallel data input and converted.