JPH09319591A - Parallelizing system for loop having conditional jump out of loop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compiling method for enabling parallel execution by dividing a loop having a conditional jump out of the loop. SOLUTION: When a condition branch sentence detects the loop containing an out-of-loop jumping instruction sentence inside a source program, this loop is divided into a loop containing this condition branch sentence and a loop containing no condition branch sentence. Then, the loop containing the condition branch sentence is rearranged so as to be first executed, the value of control variable of the loop at the time of finishing the execution of the loop containing the condition branch sentence is substituted into a primary variable, the final value of the loop containing no condition branch sentence is set to the value of the primary variable and concerning the loop containing no condition branch sentence, parallel execution is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiling technique for converting a source program into object code, and more particularly to a compiling method for parallelizing a loop having a conditional jump.

[0002]

2. Description of the Related Art A conventional compiler technique will be described below with reference to a program example in C language shown in FIG.
FIG. 12 shows a program example including a loop whose parallelizability can be determined by a conventional compiler technique.

As a conventional program conversion technique, for example, Japanese Unexamined Patent Publication No. 5-250341 discloses a parallel computer as shown in FIG.
In order to execute a source program including a loop as shown in (1) in parallel, the source program is converted to generate an object program that can be executed in parallel.

FIG. 13 is a block diagram of the parallelizing compiler device described in the above-mentioned Japanese Patent Laid-Open No. 5-250341. Referring to FIG. 13, input means 102 inputs a source program from the outside and stores it in memory 103. The memory 103 stores and holds a program that realizes compilation, a source program input from the input unit 102, an object program that is a compilation result, and the like.
The processor 101 executes the compiling process according to the program stored in the memory 103. The output means 104 is a memory 10 generated by the processor 101.
The object program held in 3 is output to the output device.

FIG. 14 and FIG. 15 are functional block diagrams of the conventional parallelizing compiler apparatus, and show the compile processing executed by the processor 101 according to the program in the memory 103 by function. In addition,
14 and 15 are divided for convenience of drawing.

Referring to FIGS. 14 and 15, the input means 1
0 reads the source program input from the outside. The intermediate code generation unit 11 converts a source program written in a high-level language (for example, C language) to generate a program written in intermediate code. The program of this intermediate code is stored in the storage means 15. The loop detection means 12 detects the loop processing included in the source program.

The array detecting means 13 detects an array included in the source program. The variable extraction means 14 detects a variable (scalar variable) included in the source program.
The storage unit 15 stores the loops and sequences detected by the loop detection unit 12 and the sequence detection unit 13.

The simulating means 16 simulates the program of the intermediate code by referring to the information about the loop and the array stored in the storage means 15. Determination means 17
Determines whether the loop can be parallelized based on the simulation result and the stored contents of the storage unit 15. The object generation means 18 generates an object program for parallel execution when the determination means 17 determines that parallelization is possible, and generates a normal object program when it is determined that parallelization is impossible.

The output means 19 outputs an object program, and is, for example, a file device for storing the program as a file.

The processing operation of the conventional parallelizing compiler apparatus configured as described above will be described with reference to the flowcharts shown in FIGS. 16 and 17. FIGS. 16 and 17 are separated for convenience of drawing.

First, the source program before being compiled is input to the input means 10 (step 21).
Note that the source program is an example of the program as shown in FIG. 12, for example.

The source program input by the input means 10 is converted into an intermediate code by the intermediate code generation means 11 and stored in the storage means 15 (step 2).
2). When the intermediate code is generated, the loop detection means 12
Detects loop processing included in the intermediate code. Specifically, in the C language program shown in FIG. 12, the loop detection means 12 uses the “for” in the source program.
"Sentence" is detected as a loop process (step 23). The detection result of the loop processing is stored in the storage unit 15. Then, according to the presence / absence of the loop processing, if the loop processing exists, the process proceeds to step 25, while if the loop processing does not exist, the process branches to step 31 (see FIG. 17) (step 24).

Next, when the loop processing is present, the array detecting means 13 determines the array expression in the extracted loop processing and detects it. In the example shown in FIG. 12, the array detection unit 13 detects the array a [i] on the left side and the array b [i] on the right side (step 25). The detection results of these arrays are stored in the storage means 15.

Further, the variable extraction means 14 detects the variables included in the loop. In the example shown in FIG. 1, “fo
In the "r sentence" loop, the array b [i] used in the conditional branch is detected and stored in the storage means 15 (step 26).

After that, the simulation means 16 refers to the storage means 15 to determine whether or not the array is stored. If the array is stored, the process proceeds to step 28, and the array must be stored. If so, the process proceeds to step 29 (step 27).

If there is an array, the simulation means 16
Refers to the storage means 15 to simulate the intermediate code program, and registers the array on the right side in the array variable definition table in the storage means 15. In this simulation, the data reference relationship is also determined. That is, the simulating means 16 and the determining means 17 simultaneously take in each sentence of the intermediate code, and the simulation and the determination of the data reference relationship are alternately performed for each sentence.

For example, in the example shown in FIG. 12, the for statement is simulated from i = 0 to 100, and the array data reference relationship is registered in the array variable definition table.

When i = 0, the conditional expression (i == 0) holds, so k = 1 is stored, and the array a [1] on the left side and the array b [0] on the right side are stored in the array variable definition table. To be done.

Since the conditional expression (i == 0) is not satisfied when i = 1, k = 2 is stored, and the array a [2] on the left side and the array b [1] on the right side are array variable definition tables. Memorized in. In this way, the for statement is repeated from i = 0 to 100, and the simulation and the data reference relationship determination are performed.

On the basis of this result, the judging means 17 judges whether or not parallelization is possible. When determining the above data reference relationship,
When it is determined that there is a data reference relationship, the determination means 17
Will not be parallelizable.

In the program example shown in FIG. 12, since there is no data reference relationship, it is determined that parallelization is possible.

According to this determination result, the object generating means 18 generates an object program based on the intermediate code. In this program example, an object program that executes in parallel a loop of for statements related to the variable i is generated. The generated program is output means 1
9 is output.

[0023]

However, in the above-mentioned prior art, it is possible to determine that the condition can be parallelized at the time of parallelization because the condition of the conditional statement is determined to be true or false at the time of compilation by the value of the control variable. It has a problem that it is limited to cases where it is possible.

That is, when the conditional expression (b [i] == 0) of the conditional statement is an expression including an array whose elements change according to the value of the control variable, as in the program example shown in FIG.
Since the value of the array request cannot be known at compile time, the truth of the conditional statement cannot be determined by simulation at compile time. Therefore, the above technique cannot determine whether or not there is a data reference relationship, and as a result, it is determined that parallelization is impossible. In the program example shown in FIG. 18, when the value of the array b [i] is 0, division by zero (ze in the operation a [i] = 1 / b [i]
In order to avoid (ro divide), the jump control from the loop to the outside is performed by executing the break statement.

The present invention has been made in view of the above circumstances, and an object thereof is to enable parallelization of a loop which could not be parallelized by the conventional technique and to improve the execution performance of a program. It is to provide a method of compiling.

Here, a loop means a loop in which there is a conditional branch, and when the conditional branch is taken, the loop is jumped out, and whether or not the condition is met can be judged for the first time at the time of execution. .

[0027]

In order to achieve the above object, the parallelizing and compiling method of the present invention is a conditional branch statement programmed so that an instruction to jump out of a loop is executed depending on whether a condition is satisfied. When detecting a loop including in the loop, the loop is divided into a loop including the conditional branch statement and a loop not including the conditional branch statement,
The loop including the conditional branch statement is arranged to be executed first, and the final value of the loop not including the conditional branch statement is obtained from the value of the loop control variable at the end of the loop including the conditional branch statement. It is characterized in that a loop not including a conditional branch can be executed in parallel.

The principle of the present invention will be described below. In the present invention, after detecting and analyzing a loop in the source program in the same manner as in the conventional method, the loop converting means divides the loop into a conditional jump portion and a portion not including the jump portion, and The loop is transformed into a loop that checks the closing value of the control variable of the original loop by actually executing a jump at run time, and the latter loop uses the result of executing the former loop as the closing value of the control variable. Converted to a loop.

According to the present invention having the above-mentioned structure, the loop having a conditional jump to the outside of the loop is divided into a part having a jump and a part other than the jump, and converted into two loops. By checking the value of the control variable at the time of jumping at the time of execution and using this as the final value of the control variable of the latter loop, the latter loop can be determined for parallel execution.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram for explaining a compiler apparatus according to an embodiment of the present invention. Referring to FIG.
The input means 2 inputs a source program from the outside and stores it in the memory 3. The memory 3 stores and holds a program that realizes compilation, a source program input from the input unit 2, an object program that is a compilation result, and the like. The processor 1 executes compilation according to the program held in the memory 3. The output unit 4 outputs the object program generated by the processor 1 and stored in the memory 3 to the output device.

2 and 3 are block diagrams showing the functions of the compiler device according to the embodiment of the present invention. The compile process executed by the processor 1 according to the program stored in the memory 3 is classified by function. It is composed. It should be noted that FIGS. 2 and 3 are separated for convenience of drawing.

Referring to FIGS. 2 and 3, the input means 50
Reads a source program input from the outside.
The intermediate code generation means 51 converts a source program written in a high-level language (for example, C language) to generate a program written in intermediate code. The program of this intermediate code is stored in the storage means 55. The loop detection means 52 detects the loop processing included in the source program.

The array detecting means 53 detects an array included in the source program. The variable extraction means 54 detects a variable (scalar variable) included in the source program.
The storage unit 55 stores the loops and sequences detected by the loop detection unit 52 and the sequence detection unit 53.

The loop conversion unit 56 refers to the information about the loop and the array stored in the storage unit 55, determines whether or not the loop conversion can be performed from the intermediate code program, and performs the loop conversion. The judging means 57
Based on the result of the loop conversion and the content stored in the storage unit 55, it is determined whether the loop can be parallelized. The object generating means 58 generates an object program for parallel execution when it is determined by the determining means 57 that parallelization is possible, and generates a normal object program when it is determined that parallelization is not possible.

The output means 59 outputs an object program, and comprises, for example, a file device for storing the program as a file.

FIG. 4 is a block diagram showing the configuration of the loop converting means 56 in the embodiment of the present invention.

Referring to FIG. 4, the loop converting means 56 is
Conditional statement detection means 56a, out-of-loop branch detection means 56b,
It comprises variable definition detecting means 56c, temporary variable introducing means 56d, conditional sentence extracting means 56e, loop dividing means 56f, and loop correcting means 56g.

The conditional statement detecting means 56a inputs the intermediate code from the intermediate code generating means 51 one by one, and detects the conditional statement from the intermediate code.

The out-of-loop branch detecting means 56b determines whether or not there is an out-of-loop branch for the conditional statement detected by the conditional statement detecting means 56a.

The variable definition detecting means 56c determines whether or not there is a definition for a variable with respect to the conditional statement judged by the outside-loop branch detecting means 56b to have an outside-loop branch, and the array detecting means 53 and the variable extracting means 54. Judgment is made using the array / variable information generated in.

If there is no definition for the variable in the conditional statement from the detection result of the variable definition detecting means 56c, the temporary variable introducing means 56d introduces a temporary variable for loop division and reflects it in the intermediate code. . Conditional sentence extraction means 56
The e stores the range for the conditional statement in the loop.

The loop dividing means 56f puts out the conditional statement specified by the conditional statement extracting means 56e out of the loop, and inserts a loop having only the conditional statement in the same loop as the current loop immediately before the current loop.

The loop correction means 56g inserts an intermediate code for substituting the value of the control variable into the temporary variable between the loops divided by the loop division means 56f, and changes the end value of the loop immediately after that to the temporary variable. .

The processing operation of the compiler according to the embodiment of the present invention configured as described above will be described below with reference to the flowcharts of FIGS. 5 and 6. Note that FIG.
6 and 6 are divided for convenience of drawing.

First, the source program before being compiled is input to the input means 50 (step 61).
The source program input from the input means 50 is converted into intermediate code by the intermediate code generation means 51 and stored in the storage means 55 (step 62). When the intermediate code is generated, the loop detection means 52 detects the loop processing included in the intermediate code (step 63), and the detection result of the loop processing is stored in the storage means 55. Then, according to the presence / absence of the loop processing, if the loop processing exists, the process proceeds to step 65, while if not, the process proceeds to step 71 (step 64).

If loop processing exists, step 65
At, the array detecting means 53 determines the array expression in the extracted loop processing and detects it. The detection results of these arrays are stored in the storage means 55. Further, the variable extraction means 54 detects the variables included in the loop (step 66).

After that, the loop converting means 56 refers to the intermediate code to judge whether or not there is a conditional statement. If there is a conditional statement, the step 68 is carried out. If there is no conditional statement, the step 69 is carried out.
(Step 67).

That is, if there is a conditional statement, step 6
At 8, the loop conversion unit 56 refers to the storage unit 55 to perform the loop conversion.

The judging means 57 judges whether or not parallelization is possible (step 69). According to the determination result, the object generating means 58 generates an object program based on the intermediate code (steps 70, 71). The generated program is output from the output means 59 (step 72).

FIG. 7 is a flowchart showing the processing flow of the loop converting means 56 in the embodiment of the present invention.

Referring to FIG. 7, the intermediate code is first input to the conditional statement detecting means 56a (step 81). The conditional statement detecting means 56a examines the intermediate code to determine whether it is a conditional statement. If it is a conditional statement, proceed to step 83,
If it is not a conditional statement, the process proceeds to step 81 (step 8)
2).

The out-of-loop branch detection means 56b checks whether or not there is an out-of-loop branch in the intermediate code of the conditional statement. If there is an out-of-loop branch, the process proceeds to step 84, and if it is not a conditional statement. Proceed to the end (step 83).

The array definition means 53 and the variable extraction means determine whether or not there is a definition for a variable with respect to the conditional statement which is judged by the variable branch detection means 56c to have a branch outside the loop by the variable definition detection means 56c. Array generated at 54 /
The determination is made using the variable information. If there is a definition for the variable, the process ends, and if not, the process proceeds to step 85 (step 8
4).

The temporary variable introducing means 56d introduces a temporary variable for loop division and reflects it in the intermediate code (step 85).

The conditional statement extracting means 56e stores the range for the conditional statement in the loop, and the loop dividing means 56f outputs the conditional statement to the outside of the loop, and only the conditional statement in the same loop as the current loop. Is inserted immediately before the current loop (step 86).

The loop compensating means 56g inserts an intermediate code for substituting the value of the control variable into the temporary variable between the loops divided by the loop dividing means 56f, and changes the end value of the loop immediately after that to the temporary variable. (Step 87).

[0058]

EXAMPLES Examples of the present invention will be described below in order to explain the above-described embodiments of the present invention in more detail.

As an embodiment of the present invention, a C language loop is included and a conditional branch is executed to jump out of the loop (b [i] =
8 shows an example of the source program).

FIG. 9 shows a program resulting from introducing temporary variables into the loop of the program shown in FIG. 8 according to the embodiment of the present invention.

FIG. 10 shows a program resulting from dividing a loop according to the embodiment of the present invention.

FIG. 11 shows an embodiment of the present invention shown in FIG.
The program obtained as a result of correcting the closing price of the loop of the program is shown.

First, the source program before being compiled is input to the input means 50 (step 61 in FIGS. 5 and 6).

The source program input from the input means 50 is converted into intermediate code by the intermediate code generation means 51 and stored in the storage means 55 (step 6).
2). When the intermediate code is generated, the loop detection means 52
Detects loop processing included in the intermediate code.

Specifically, in the C language as shown in FIG. 8, the loop detecting means 52 detects the "for statement" in the source program as a loop process (step 6).
3). The detection result of the loop processing is stored in the storage unit 55. Then, according to the presence / absence of the loop processing, if it exists, the process proceeds to step 65, and if not, the process proceeds to step 71 (step 64).

Next, when the loop processing is present, the array detecting means 53 determines the array expression in the extracted loop processing and detects it. In FIG. 8, the array detection means 53 has an array a [i] on the left side and an array b [i] on the right side.
And are detected (step 65). The detection results of these arrays are stored in the storage means 55. Furthermore, the variable extracting means 54 detects the variables included in the loop. In the loop of “for sentence” in the program shown in FIG.
The array b [i] used in the conditional branch is detected and stored in the storage means (step 66).

After that, the loop converting means 56 refers to the intermediate code to judge whether or not there is a conditional statement. If there is a conditional statement, the process proceeds to step 68, and if not, the process proceeds to step 69 (step 67). In the program shown in FIG. 8, "if statement"
Exists, the process proceeds to step 68. If there is a conditional statement, the loop conversion means 56 refers to the storage means 55 to convert the loop (step 68). In the first embodiment, the loop converting means 56 converts the program into a program as shown in FIG.

The judging means 57 judges whether or not parallelization is possible (step 69). Since it is converted by the loop conversion means 56 as shown in FIG. 16, the loop of B does not depend on the reference relationship of the arrays of a [i] and b [i], and thus it is determined that parallelization is possible.

According to the determination result, the object generating means 58 generates an object program based on the intermediate code (steps 70, 71). The generated program is output from the output means 59 (step 7).
2).

The detailed processing operation of the loop transformation will be described below with reference to the flowchart of FIG. First, the intermediate code is input to the conditional statement detecting means 56a.

In the program example shown in FIG. 8, "for"
The intermediate code of the whole "sentence" is input (step 81).
The conditional statement detecting means 56a examines the intermediate code to determine whether it is a conditional statement. If it is a conditional statement, the process proceeds to step 83, and if it is not a conditional statement, the process proceeds to step 81.

In the program example shown in FIG. 8, "for"
Since the conditional statement (“if statement”) exists in the loop of “statement”, it is determined that there is a conditional statement (step 82).

The out-of-loop branch detecting means 56b checks whether or not there is an out-of-loop branch with respect to the intermediate code of the above-mentioned conditional statement. If there is an out-of-loop branch, the process proceeds to step 84 and the conditional statement If you proceed to the end.

In the program example shown in FIG. 8, since a branch statement outside the loop (break statement) exists, it is judged that there is a branch outside the loop (step 83).

In the variable definition detecting means 56c, the array detecting means 53 and the variable extracting means determine whether or not there is a definition for a variable with respect to the conditional statement judged by the outer loop branch detecting means 56b to have an outer loop branch. The determination is made using the array / variable information generated in 54, and if there is a definition for the variable, the process ends, and if not, the process proceeds to step 85.

In the example shown in FIG. 8, since all the sentences included in the conditional sentence are right-hand side values, it is determined that there is no definition for the variable (step 84).

The temporary variable introduction means 56d introduces a temporary variable for loop division and reflects it in the intermediate code. Temporary variables are given arbitrary identifiers so that their names do not conflict with other variables in the source program.

In the program example shown in FIG. 8, a temporary variable n is introduced as shown in FIG. 9 (step 85).

The conditional statement extracting means 56e stores the range for the conditional statement in the loop, and the loop dividing means 56f outputs the conditional statement to the outside of the loop so that only the conditional statement is present in the same loop as the current loop. Insert a loop just before the current loop.

In the example shown in FIG. 9, as shown in FIG. 10, the “if sentence” is extracted from the original “for sentence”, and the “for sentence” of only the “if sentence” and the other “for sentence” are extracted. f
or sentence ”(step 86).

The loop compensating means 56g inserts an intermediate code for substituting the value of the control variable into the temporary variable between the loops divided by the loop dividing means 56f, and changes the end value of the loop immediately after that to the temporary variable. To do.

This ensures that the result is the same as the original loop.

Then, in the example shown in FIG. 10, as shown in FIG. 11, the temporary variable n is set to "if
Statement is inserted so that the closing value of the control variable after executing the “for statement” is entered, and the “fo statement” of the “if statement” only is inserted.
Replace the closing price of "r sentence" with temporary variable n (step 8)
7).

Although the above embodiment has been described based on a program example in C language, the present invention is not limited to C language and can be applied to other various high-level languages. Is.

[0085]

As described above, according to the present invention,
For conditional loops that could not be parallelized and executed in parallel in the conventional technology, the conditional branch was included because the loop was divided into a conditional branch part and other parts. This has the effect of enabling parallel execution of loops correctly for non-existing loops.

This is because, in the present invention, by executing the conditional branch part first, the final value of the loop not including the conditional branch can be obtained, and the parallel execution is performed correctly.

[Brief description of drawings]

FIG. 1 is a block diagram of a parallelization compiling apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing functional means of the parallelizing / compiling device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing functional means of a parallelization compiling device according to an embodiment of the present invention.

FIG. 4 is a block diagram showing functional means of the parallelizing / compiling device according to the embodiment of the present invention.

FIG. 5 is a flowchart for explaining the processing operation of the parallelization compiling device according to the embodiment of the present invention.

FIG. 6 is a flowchart for explaining the processing operation of the parallelization compiling device according to the embodiment of the present invention.

FIG. 7 is a flowchart for explaining the processing operation of the loop conversion means in the embodiment of the present invention.

FIG. 8 is a diagram for explaining the embodiment of the present invention and is a diagram showing a program example.

FIG. 9 is a diagram for explaining the embodiment of the present invention and is a diagram showing an example of a program into which a temporary variable is introduced.

FIG. 10 is a diagram for explaining an example of the present invention,
It is a figure which shows the example of the program which divided the loop.

FIG. 11 is a diagram for explaining an embodiment of the present invention;
It is a figure which shows the example of a program which corrected the progress of the loop which does not include a conditional branch.

FIG. 12 is a diagram for explaining a conventional technique, and is a diagram showing an example of a program including a parallelizable loop in the conventional technique.

FIG. 13 is a block diagram showing a configuration of a conventional parallelizing compiling device.

FIG. 14 is a block diagram showing functional means of a conventional parallelizing compiling device.

FIG. 15 is a block diagram showing functional means of a conventional parallelizing compiling device.

FIG. 16 is a diagram for explaining a processing operation of a conventional parallelizing compiling device.

FIG. 17 is a diagram for explaining a processing operation of a conventional parallelizing compiling device.

FIG. 18 is a diagram for explaining a conventional technique and is a diagram showing a program example including a loop that cannot be parallelized by the conventional technique.

[Explanation of symbols]

 1 Processor 2 Input Means 3 Memory 4 Output Means 50 Input Means 51 Intermediate Code Generating Means 52 Loop Detecting Means 53 Array Detecting Means 54 Variable Extracting Means 55 Storage Means 56 Loop Converting Means 57 Judging Means 58 Object Generating Means 59 Output Means

Claims (3)

[Claims] 1. When a loop including a conditional branch statement programmed so that an instruction for jumping out of the loop is executed depending on whether a condition is satisfied is detected, the loop is set to the conditional branch statement. And a loop not including the conditional branch statement, arranged so that the loop including the conditional branch statement is executed first, and a loop at the end of the loop including the conditional branch statement. A parallel compiling method, wherein a final value of a loop that does not include the conditional branch statement is obtained from the value of a control variable, and the loop that does not include the conditional branch can be executed in parallel. 2. A loop in which a source program is scanned to detect a loop in which a conditional jump out of the loop exists, and a condition of the detected loop is determined and jumped out of the loop. , Other loops other than this, and the loop of the portion that jumps out of the loop, the value of the control variable after executing the loop, the final value of the control variable of the other loop And the other loop is converted so as to be executed in parallel. 3. It is determined whether or not a variable definition is included in the conditional statement that is determined to have a branch out of the loop. If the variable definition is not included, a loop split Introduce a temporary variable, assign the value of the control variable of the loop of the portion jumping out of the loop between the divided loops to the temporary variable, the closing value of the loop immediately after the loop of the portion jumping out of the loop 2. The parallelizing compiling method according to claim 1, wherein the setting is automatically made so as to be changed to a temporary variable.