JPH09319343A - Display device, and driving method for display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of connecting terminals and the number of analog switches of the driving circuit of a display device which performs a multi-gradation display. SOLUTION: First and second reference voltages, in which the voltage range required for the gradation display is divided into two parts and the voltages are stepwise increased as time passes in each voltage section, are respectively given to analog switches ASWia and ASWib. Then, a reference voltage is selected based on a most significant bit D2 of gradation display data D0 to D2. When the selected reference voltage reaches to the voltage corresponding to the data D0 and D1, the switches ASWia and ASWib are selectively conducted/shut off. The voltage corresponding to the data D0 to D2 among the voltages, in which the first and the second reference voltages are varied, are given to a picture element electrode through a source line Oi and the display based on the gradation display data is conducted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as an active matrix type liquid crystal display panel which performs multi-gradation display and a display panel driving method.

[0002]

2. Description of the Related Art FIG. 27 shows a schematic structure of a typical prior art. The active matrix type liquid crystal display panel 11 constituting the display device 10 of the first prior art includes
Source lines O1 to ON and gate lines L1 to L1 are arranged in a matrix.
LM is formed, and the thin film transistor T and the pixel electrode P are arranged at the intersections thereof. Pixel electrode P
, The voltage of the source lines O1 to ON is selectively applied via the thin film transistor T.

The source lines O1 to ON are connected to a source driver 12 composed of a semiconductor integrated circuit. The source driver 12 controls each source line Ok (k =
1 to N), one of the total eight types of reference voltages V0 to V7 supplied from the reference voltage source 13 is selected according to the 3-bit display data D0 to D2, and the terminals S1 to SN are selected. Give through. The gate driver 14 formed of a semiconductor integrated circuit selects, for the gate lines L1 to LM, gate signals G1 to GM for selecting one gate line.
Is output. The source driver 12 is based on the display data D0 to D2 associated with each pixel electrode P on the gate line Lj selected by receiving the gate signal Gj (j = 1 to M) every horizontal scanning period. A reference voltage is applied to each source line Ok.

FIG. 28 shows the structure of a part of the first prior art source driver 12 shown in FIG. 27 more specifically. The source driver 12 has source lines O1 to O
Decoder circuits FRk individually corresponding to N (k = 1 to 1
N) and responds to the data d0 to d2 corresponding to the display data D0 to D2, respectively, and outputs eight types of reference voltages V0 to V7 from the reference voltage source 13 to the analog switch A.
It is selected by SW0 to ASW7 and is selectively applied to the source line Ok to display 8 gradations.

In the first prior art shown in FIGS. 27 and 28, the source driver 12 receives a reference voltage source 13 and individual reference voltages V0 to V corresponding to the number of gradations.
7 are given in parallel. The source driver 12 requires the same number of connection terminals as the reference voltages V0 to V7 to be applied. Further, in order to output the reference voltage in the source driver 12, the analog switches ASW0 to ASW7 individually corresponding to the respective gradations are required by the number of gradations.

The analog switches ASW0 to ASW7 in the source driver 12 are source lines O1 to ON of the display panel 11 connected to the outside of the source driver 12.
In addition, in order to accurately write the levels of the selected reference voltages V0 to V7, it is necessary to make the ON resistance thereof sufficiently low. Therefore, the analog switches ASW0 to ASW7
The area occupied by the semiconductor chip is generally required to be about ten to several tens of times as large as that of the logic circuit element which is on / off controlled for the logical operation in the source driver 12.

For the above-mentioned reason, in the semiconductor chip, the analog switches ASW0 to ASW7 occupy a large proportion of the entire area where the source driver 12 is formed. Therefore, an increase in the number of analog switches ASW0 to ASW7 due to the increase in the number of gradations leads to an increase in the size of the semiconductor chip in which the source driver 12 is formed.

In recent years, in semiconductor chips such as the source driver 12, measures have been taken to reduce the chip size, but there is a limit to downsizing the terminals themselves, and the number of connection terminals is reduced. It is desired to let them do. Further, it is desired to reduce the number of analog switches ASW0 to ASW7 included in the source driver 12 to reduce the chip size of the source driver 12 including a semiconductor integrated circuit to reduce the cost.

In the first prior art, for example, when 16 gradation display is performed using 4-bit display data, 16
A connection terminal for a reference voltage for generating a voltage of a kind is required, and a total of 16 analog switches corresponding to each reference voltage are required. In fact, it has been impossible to mass-produce the source driver 12 for displaying more gradations such as 64 gradations and 256 gradations.

As a second prior art, Japanese Unexamined Patent Publication No. 4-214594 discloses a concept of reducing the number of connection terminals for the reference voltage and the number of analog switches to reduce the size of the semiconductor chip. It is disclosed. FIG. 29 shows a simplified configuration of the display device disclosed in this publication.

The liquid crystal is interposed between a pair of substrates, that is, one pixel substrate and the other counter substrate. On the pixel substrate, the pixel electrode 16, the drain line 17, the gate line 18, and the drain line 17 and the drain line 17 are provided at intersections of the drain line 17 and the gate line 18.
And the switching element 19 for applying the voltage of 2 to the pixel electrode 16. A portion of the liquid crystal that is interposed between each pixel electrode 16 and the counter substrate forms a liquid crystal element. On the counter substrate of the first prior art, the data electrodes 20 for each column extending in the vertical direction of FIG. 29 are formed.

A control pulse is applied from the scanning circuit 21 to the gate line 18 for sequential scanning, and a reference gradation signal whose voltage changes at a constant rate is drained to the pixel electrode 16 within each horizontal scanning period. Apply via line 17. In other words, the drain line 17 is commonly provided with a voltage of a ramp waveform in which the voltage rises or falls with time within one horizontal scanning period from the single reference gradation signal circuit 23. The data electrode 20 is supplied with a data signal whose voltage level is fixed only during a period corresponding to the gradation level.
Supply from 2. During the remaining period, the output of the signal supply circuit 22 is in the high impedance state. That is, a voltage whose voltage level is fixed is applied to the data electrode 20 for a time corresponding to the gradation level, and the gradation level is adjusted according to the length of the period in which the voltage level of the data electrode is fixed.

In the above-mentioned second prior art, a large number of data electrodes 20 divided into columns are provided on the other counter substrate.
There is a big problem that it is necessary to provide. At present, a pixel electrode 1 of a liquid crystal display panel that is widely used in general.
The counter substrate facing 6 has a large number of these pixel electrodes 16
Has a single common electrode formed over the entire area. Therefore, when implementing the prior art, it is difficult to implement the prior art because it is necessary to newly redesign the display panel itself.

Further, in the second prior art, since the gray level is held on the data electrode 20 side, an auxiliary for holding data formed on the picture element substrate of the display panel which has been generally used in the past. There is a problem that the capacity cannot be used as it is.

FIG. 30 shows a simplified configuration of the third prior art disclosed in Japanese Patent Laid-Open No. 5-297833. The shift register 27 uses the clock signal CLK as a timing for writing the input data composed of 4 bits for each color R, G, B into the data register 28.
Control based on When the input data for one line is written in the data register 28, the written data for one line is transferred to the data latch circuit 29 in parallel and held.

The data held by the data latch circuit 29 is supplied to the comparison section 30 at a predetermined timing. In the comparison unit 30, the data latch circuit 29 is provided for each color R, G, B.
From the 4-bit counter 31 is compared with the count value of 4 bits from the 4-bit counter 31, and the comparison result is supplied to the sample-and-hold circuit 32 with a built-in selector. In the sample-and-hold circuit 32 with a built-in selector, in addition to the comparison result of the comparison section 30, a predetermined 8 bits from the stepwise waveform voltage circuits 33 and 34 are provided.
Stepped waveform voltages VR and VB whose levels change respectively in steps and two steps are supplied.

Sample hold circuit 32 with built-in selector
At a timing corresponding to the comparison result of the comparison unit 30, the sample and hold capacitors built in the selector built-in sample and hold circuit 32 sample and hold the signals from the stepped waveform voltage generation circuits 33 and. The voltage VDD is supplied to the output buffer 35, and a signal voltage corresponding to the charging voltage level charged in the capacitor in the selector built-in sample hold circuit 32 is output for each color R, G, B to output each column. Give each line.

In the third prior art, a sample-hold capacitor 32 having a built-in selector has a sample-hold capacitor, and the voltage due to the charge accumulated in the capacitor is applied to each line provided in the output buffer 35. It outputs via the voltage follower by each operational amplifier. Therefore, the staircase waveform voltage generation circuits 33, 3
The output of No. 4 is only given to the capacitor of the sample-hold circuit 32 with a built-in selector, and is not directly given to the line of the display panel. The voltage applied to each line of the display panel is the output buffer 35.
Since it is a voltage amplified by the operational amplifier provided in, the voltage applied to each line changes undesirably due to variations in the characteristics of the operational amplifier, resulting in deterioration of display quality. The variation in the characteristic of the operational amplifier is caused, for example, by the presence of the deviation of the output voltage due to the variation of the input offset voltage and the narrowing of the output voltage range due to the limitation of the dynamic range of the operational amplifier.

Further, as a fourth prior art, there is one disclosed in Japanese Patent Publication No. 7-50389. 31 shows the configuration of the X driver 120 for driving the source electrode disclosed in the above publication, and FIG. 32 shows the X driver 1
20 shows the timing of each signal in 20.

The shift register 121 has M sets of signals Q1.
To QM are output and 4-bit data input signals PD1 to P
The timing of writing D4 into the half latch 129 of the latch A circuit 122 is controlled based on the start pulse VSP and the clock signal XCL. The latch A circuit 122 is provided with M sets of half latches 129 formed by four D flip-flops, and the M sets of half latches 129 sequentially take in and hold the signal data. The half latch 130 of the latch B circuit 123 is shown in FIG.
When the latch clock signal LCL shown in (3) is input, the data held in the M sets of half latches 129 of the latch A circuit 122 are simultaneously fetched and held in the half latches 130 of the latch B circuit 123. .

The 4-bit binary counter 124 is reset by the latch clock signal LCL and counts the gradation basic signal F16 shown in FIG. 32 (2). Comparator 12
The outputs QA to QD of the binary counter 124 and the output of the half latch 130 are input to the M comparators 138 of 5 and the comparison result is the D flip-flop 126 as the output signal Y shown in FIG. Given to the input D of. The D flip-flop 126 takes in the output of the comparator 138 in synchronization with the rising of the gradation basic signal F16, is set by the latch clock signal LCL, and is reset by the stop signal STOP. The output Q of the D flip-flop 126 is raised by the level shifter 127 to a voltage capable of driving the analog switch 128.

The analog switch 128 is shown in FIG.
The video voltage VID shown in (1) is supplied, and the opening / closing is controlled by the output of the level shifter 127. The video voltage VID is 1 from the off-level voltage VOFF of the liquid crystal to the on-level voltage VON in one horizontal scanning period TH.
Next, it changes linearly, and once it reaches the on-level voltage VON, it rapidly changes to the off-level voltage VOFF, and becomes a repetitive sawtooth waveform with the off-level voltage until the next rise.

Video voltage VID varying as described above
Is controlled by opening and closing the analog switch 128,
The voltage Vpix shown in FIG. 32 (6) is applied to the picture element electrode of the liquid crystal display panel through the source line. Voltage V
The level of pix at the time ta when the basic signal F16 for gradation first rises after the output signal Y falls is held until time tb when the horizontal scanning period TH ends.

In the fourth prior art, the video voltage V supplied to the source electrode through the analog switch 128 is used.
Since the ID has a first-order linear sawtooth waveform, when the timing of the output signal of the comparator 138 is slightly deviated, the voltage at that timing is held, resulting in deterioration of display quality.

Further, in each of the above-mentioned prior arts, since the charge charged in the liquid crystal element is not discharged, the charge charged at the previous display timing remains in the liquid crystal element and the liquid crystal element is driven according to new display data. However, there is a problem that the voltage due to the charged electric charge does not become the voltage corresponding to the gradation display data. For example, if a liquid crystal element is displayed at a previous display timing by being charged with a high voltage and then a display is performed at a voltage lower than the voltage charged at the next display timing, the liquid crystal element is first displayed. Unless the electric charge charged to is discharged, the previous electric charge remains,
The display quality of the liquid crystal display panel may be degraded.

[0026]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the number of connection terminals and the number of analog switches while increasing the number of gradations, thereby reducing the size of semiconductor chips such as source drivers and reducing current consumption. It is an object of the present invention to provide a driving method of a display device and a display panel, which enables cost reduction and high-density mounting.

Another object of the present invention is to use the display panel in which a single common electrode is formed on the counter substrate which is widely used at the present time as it is, and as described above, the number of connection terminals and the number of analog switches. It is an object of the present invention to provide a method for driving a display device and a display panel that can reduce

Still another object of the present invention is shown in FIG.
It is possible to prevent display quality from deteriorating due to variations in characteristics of semiconductor elements without using a complicated circuit configuration such as an operational amplifier as in the prior art described in relation to It is an object of the present invention to provide a display device and a display panel driving method capable of reducing the size of a semiconductor chip and reducing power consumption.

[0029]

According to the present invention, picture element electrodes are arranged in a matrix at intersections of a plurality of first and second lines, respectively, and a dielectric material is provided between the picture element electrodes and a common electrode facing each other. In the active matrix type display panel in which the layers are interposed, the driving voltage corresponding to the gradation display data is applied to the first line, and the second line is selected for each scanning period predetermined by the pixel control signal, In a display device driven to perform display, a grayscale clock signal generating unit that sequentially generates a grayscale clock signal of a number equal to or greater than the number of grayscales in each scanning period, and a voltage required for grayscale display. Within each voltage range obtained by dividing the range into a plurality of ranges, a plurality of reference voltages provided corresponding to the number of divisions are generated for each scanning period so as to change in a fixed direction in synchronization with the grayscale clock signal. Voltage source and A switching element for voltage application, which is provided for each of the first lines in correspondence with the number of divisions with the voltage source and is provided with each of the reference voltages, and each of which is provided for each of the first lines. Selection means for selecting a reference voltage in which a voltage for driving the pixel electrodes is included in a change range corresponding to display data, and a gradation clock provided for each of the first lines and for each of the scanning periods. A voltage application switching element that counts the grayscale clock signal from the signal generating means and is supplied with the reference voltage selected by the selecting means with reference to the time when the count value reaches the value corresponding to the grayscale display data. And a switching control unit that controls from one of ON and OFF predetermined to correspond to the selected changing direction of the reference voltage to the other. According to the present invention,
The drive voltage required for gradation display is divided into a plurality of voltage sections. It is necessary while increasing the number of gradations because the reference voltage that changes in each section is selected according to the gradation display data and the pixel electrodes are driven when the selected reference voltage becomes the voltage corresponding to the gradation display data. It is possible to reduce the number of necessary signal lines.

Further, in the display panel of the present invention, the driving voltage applied via the first line is applied to the pixel electrodes arranged at the intersections of the first and second lines arranged in a matrix. Two pixel lines are applied via a pixel switching element that is made conductive by a pixel control signal applied via two lines, and a constant voltage serving as a reference is applied to a common electrode provided opposite to the pixel electrode, and Grayscale display is performed by providing a potential difference with the common electrode, and a pixel control signal is sequentially applied to each second line in a plurality of predetermined horizontal scanning periods as the predetermined scanning period to generate a pixel control signal. And a driver circuit for conducting a pixel switching element connected to a second line, and a gradation display for sequentially deriving the gradation display data for each first line by serial bits during the horizontal scanning period. And a data latch circuit for deriving the grayscale display data from the grayscale display data generating means by parallel bits by one horizontal scanning period, and deriving the data. For each scanning period, a number of grayscale clock signals equal to or greater than the number of grayscales to be grayscale-displayed during that period are sequentially generated, and the voltage source supplies a predetermined first voltage to a first voltage rather than a first voltage. High second
Voltage, or a first reference voltage that gradually decreases from a second voltage to a first voltage, and a third reference voltage that is higher than the second voltage from the second voltage. Alternatively, the second reference voltage that gradually decreases from the third voltage to the second voltage, and the constant voltage serving as the reference that becomes the first and third voltages are generated at predetermined intervals, and the voltage application switching is performed. The element includes first and second voltage application switching elements that are interposed between the voltage source and the first line and are supplied with first and second reference voltages, respectively.
The switching control means includes a subtraction counter for setting a value corresponding to gradation display data for each horizontal scanning period and subtracting each time a gradation clock signal is received,
When the count value of the subtraction counter reaches a predetermined value, the first
And controlling the second voltage applying switching element to be turned on or off. According to the present invention, the first and second voltages that gradually increase or decrease with the lapse of time supplied from the voltage source are supplied to the electrodes of the display panel via the first and second voltage application switching elements. Is applied to the first and second switching elements for voltage application so that the voltage corresponding to the gradation display data is applied by the switching control means to which the output of the data latch circuit is applied. Display on the panel.
Therefore, the voltage corresponding to the grayscale display data may be a voltage included in one of the first and second voltages, and the changing voltage of the first and second voltages in one horizontal scanning period. The difference can be reduced, and a desired voltage can be easily applied to the first line of the display panel to perform gray scale display.

In the present invention, the voltage application switching element is a P-channel transistor element when the supplied reference voltage is a voltage that changes so as to increase, and the voltage is a voltage that changes so as to decrease. In some cases, N-channel transistor elements are used. According to the present invention, when the first and second reference voltages are voltages that change so as to increase, the P-channel transistor element is used as the voltage application switching element to which the reference voltage is applied, and changes so as to decrease. When the voltage is set to N, a N-channel transistor element is used. Therefore, the voltage application switching element can be composed of either one of the conductivity type transistors, and the area on the semiconductor chip where the device for driving the display panel is formed can be reduced. In addition, a desired drive voltage within a voltage range that changes as the first and second reference voltages supplied from the voltage source is supplied to the pixel electrode via the first line of the display panel, and the pixel electrode is easily The key display can be performed.

Further, in the display panel of the present invention, the driving voltage applied via the first line is applied to the pixel electrodes respectively arranged at the intersections of the first and second lines arranged in a matrix. Two pixel lines are applied via a pixel switching element that is made conductive by a pixel control signal applied via two lines, and a constant voltage serving as a reference is applied to a common electrode provided opposite to the pixel electrode, and Grayscale display is performed by providing a potential difference with the common electrode, and a pixel control signal is sequentially applied to each second line in a plurality of predetermined horizontal scanning periods as the predetermined scanning period to generate a pixel control signal. And a driver circuit for conducting a pixel switching element connected to a second line, and a gradation display for sequentially deriving the gradation display data for each first line by serial bits during the horizontal scanning period. And a data latch circuit for deriving the grayscale display data from the grayscale display data generating means by parallel bits by one horizontal scanning period, and deriving the data. For each scanning period, a number of grayscale clock signals equal to or greater than the number of grayscales to be grayscale-displayed during that period are sequentially generated, and the voltage source supplies a predetermined first voltage to a first voltage rather than a first voltage. High second
Voltage, or the first reference voltage that gradually decreases from the second voltage to the first voltage, and the third reference voltage that is higher than the second voltage from the second voltage to the third reference voltage. ,
A second reference voltage that gradually decreases from the third voltage to the second voltage, and gradually increases from the third voltage to a fourth voltage higher than the third voltage, or from the fourth voltage to the third voltage. The third reference voltage that gradually decreases, and gradually increases from the fourth voltage to the fifth voltage higher than the fourth voltage, or the fifth reference voltage.
A fourth reference voltage that gradually decreases from the voltage to the fourth voltage is created as a gradation display drive voltage, and a time point corresponding to the gradation display data elapses.
And a constant voltage serving as the reference that is the third voltage,
The voltage application switching element is interposed between the voltage source and the first line, and is provided with first, second, third and fourth reference voltages, respectively, first, second, third and fourth.
The switching control means includes the first reference voltage at a point in time when the time corresponding to the gradation display data elapses with respect to the first line for each horizontal scanning period. To a fourth reference voltage, the common electrode is switched every horizontal scanning period to apply a voltage so that the common electrode holds the voltage in a dielectric layer between the pixel electrode and the common electrode. It is characterized by controlling to. According to the present invention, the drive voltage corresponding to the gradation display data is a voltage included in the change range of any one of the first to fourth reference voltages divided into four voltage sections. . Since the reference voltage is selected in accordance with the gradation display data and the driving voltage is temporally selected, the change range of the first to fourth reference voltages in one horizontal scanning period can be reduced, and the desired driving voltage can be temporally changed. It is possible to select multi-gradation with high accuracy and easily apply it to the first line of the display panel.

In the present invention, as the first to fourth voltage application switching elements, when the supplied reference voltage is a voltage that increases stepwise, a P-channel transistor element is used and the voltage gradually decreases. When it is voltage,
An N channel transistor element is used. According to the present invention, when the first to fourth reference voltages are increasing voltages, the first to fourth reference voltages are applied.
Since the fourth voltage application switching element is a P-channel transistor and is an N-channel transistor when the voltage is decreasing, any one of the first to fourth voltage application switching elements may be a conductivity type transistor. Therefore, the area of the semiconductor chip forming the circuit for driving the display panel can be reduced.

In the present invention, the voltage application switching element is an analog switch.
According to the present invention, since the voltage application switching element is an analog switch, even if the reference voltage supplied from the voltage source changes in either the rising direction or the falling direction, the voltage within the changing voltage range is not changed. It is possible to easily perform gradation display by extracting a voltage corresponding to the gradation display data and applying it to the pixel electrode through the first line of the display panel.

Further, according to the present invention, an analog switch which is electrically connected between the voltage application switching element and the picture element electrode at the end of each scanning period and supplies a predetermined voltage to the picture element electrode is provided. It is characterized by being provided. According to the present invention, at the end of each scanning period, the analog switch is turned on and a predetermined voltage is applied to the pixel electrode. Therefore, the voltage applied to the picture element electrode in the previous horizontal scanning period is changed to a constant voltage, and even if the voltage to be applied to the picture element electrode varies greatly in each scanning period, the display It is possible to prevent deterioration of the quality of the display on the panel. In particular, when the voltage application switching element is an N-channel transistor element when the reference voltage is a decreasing voltage and the voltage application switching element is a P-channel transistor element when the reference voltage is an increasing voltage, Therefore, the configuration of the voltage application switching element can be reduced. If a predetermined voltage is used as the first reference voltage in the scanning period, it is possible to perform display on the display panel without the drive voltage being affected by the charges held in the pixel electrodes.

Further, according to the present invention, a dielectric layer is interposed between a pixel electrode of an active matrix type and a common electrode, and a voltage corresponding to gray scale display data is applied between the electrodes to perform gray scale display. In a method of driving a panel, a first voltage gradually increases from a first voltage to a second voltage higher than the first voltage or decreases from a second voltage to a first voltage with a lapse of time at a predetermined cycle. A reference voltage of 1 and a second reference voltage that gradually increases from the second voltage to a third voltage higher than the second voltage or decreases from the third voltage to the second voltage. The electrodes are provided with the first electrodes at the time when the time corresponding to the gradation display data elapses in each of the cycles.
Alternatively, a second reference voltage is applied, the first and third voltages are applied to the common electrode by switching them every cycle, and the applied voltage is held by a dielectric layer between the electrodes. This is a method of driving the display panel. According to the present invention, one electrode is applied with a voltage corresponding to gradation display data among the voltages that can change the first and second voltages that gradually increase or decrease with time and display. Since the panel is driven, the voltage corresponding to the gradation display data only needs to be a voltage included in one of the first and second voltages, and the change in the first and second voltages in each cycle. The difference in applied voltage can be reduced, and a desired voltage can be easily applied to the display panel for grayscale display.

Further, according to the present invention, a dielectric layer is interposed between the pixel electrodes of the active matrix type and the common electrode, and a voltage corresponding to gradation display data is applied between the electrodes to m (m is 2). In the method of driving a display panel for displaying an (integer) gradation, a predetermined first voltage to a second voltage are divided into n (n is a divisor of m excluding 1 and m) voltage sections. Divide and create first to nth reference voltages that change from the lowest voltage to the highest voltage or change from the highest voltage to the lowest voltage in each voltage section in a predetermined cycle. Each time, a reference voltage including a drive voltage corresponding to grayscale display data is selected and applied in the voltage section of the first to nth reference voltages, and the common electrode is switched every cycle. Either one of the first voltage and the second voltage is applied and applied The pressure is a driving method of a display panel, characterized in that to hold a dielectric layer between the electrodes.
According to the present invention, it is possible to perform m-gradation display on an active matrix type display panel by AC drive by dividing a necessary voltage range into n. If the number of divisions n is increased, the number of signal lines and the number of switching elements can be relatively reduced even when the number of gradations m is increased, and a large margin can be taken when determining the selection timing.

The present invention is also characterized in that the first to nth reference voltages change in a linear function within the voltage section. According to the present invention, the reference voltage changes in a linear function within the voltage section divided into n, so that a desired voltage can be selected by adjusting the timing.

Further, the present invention is characterized in that the first to nth reference voltages are respectively increased or decreased in m / n steps within the voltage section. According to the present invention, since the reference voltage changes in m / n steps in each voltage section divided into n, even if the number of gradations m increases, the number of changing steps of each reference voltage is reduced to select. Can be done easily.

[0040]

1 is a block diagram showing a configuration of a liquid crystal display device 100 for explaining a first embodiment of the present invention. The liquid crystal display device 100 includes a liquid crystal display panel 36, a source driver 37, and a gate driver 38.
A display control circuit 39 and a reference voltage source circuit 41.

Active matrix type liquid crystal display panel 3
6 is the source line O1 which is the first line in M rows and N columns.
~ ON and the gate lines L1 to LM, which are the second lines, are arranged on the pixel substrate, which is one substrate. At the intersections of the source lines O1 to ON and the gate lines L1 to LM, thin film transistors (abbreviated as TFTs) T (j, i) (j = 1 to M, i = 1 to 1) that are pixel switching elements.
N) is arranged.

A gate signal G is applied to the gate lines L1 to LM.
1 to GM are sequentially applied, the thin film transistor T (j, i = 1 to 1) whose gate electrode is connected to the gate line Lj to which the gate signal Gj is applied.
N) becomes conductive. This allows the source lines O1 to ON
The gray scale display driving voltage from the pixel electrode P (j, i) through the conducting thin film transistor T (j, i = 1 to N).
= 1 to N).

A single common electrode Q facing all of these picture element electrodes P is formed on the other picture element electrode P, which is opposed to the one picture element substrate via the liquid crystal which is a dielectric layer. The gradation display is performed by the electric field between the common electrode Q and the picture element electrode P to which the drive voltage is selectively applied. A voltage having a polarity different from that of the drive voltage is applied to the common electrode Q with reference to a predetermined voltage value. In FIG. 1, the common electrode Q is shown in a divided manner in order to show that one pixel is displayed by the pixel electrode P and the common electrode Q.

The source lines O1 to ON are connection terminals S of a source driver 37 realized by a semiconductor integrated circuit.
1 to SN, respectively. Gate lines L1 to L
M is connected to the connection terminals G1 to GM of the gate driver 38 realized by the semiconductor integrated circuit, respectively. In this specification, the connection terminal and the signal applied to the connection terminal may be denoted by the same reference numerals.

In each horizontal scanning period WH in which the gate lines L1 to LM sequentially become high level, a thin film transistor T (pixel switching element whose gate electrode is connected to the high level gate line Lj is connected. j, i = 1 to N) are conducted. Therefore, the driving voltage corresponding to the gradation display data given through the source lines O1 to ON charges the liquid crystal layer existing between the pixel electrodes P (j, i = 1 to N) and the common electrode Q. To do. The charged voltage level between the liquid crystal layers is held by the capacitance between the liquid crystal layers during one vertical scanning period in which a total of M gate lines L1 to LM are scanned.

The source driver 37 includes a display control circuit 3
The serial 3-bit gradation display data D0 to D2 is sequentially provided from 9 in correspondence with the source lines O1 to ON.
The display control circuit 39 also generates a clock signal CK, a hold signal LS, a grayscale clock signal CLK, a start pulse signal SP, and an alternating signal FR and supplies them to the source driver 37. These reference symbols D0 to D2, C
K, LS, CLK, SP, FR may be used to indicate a signal, a connection terminal or a line, as well as other reference signs in the following description.

Clock signal CK and hold signal LS
The signal synchronized with the
Also provided from 9 to the gate driver 38. The gate driver 38 synchronously applies the sequential gate signals G1 to GM to the gate lines L1 to LM as described above.

A reference voltage source circuit 41 is provided to apply a drive voltage to the source lines O1 to ON. The reference voltage source circuit 41 supplies first and second reference voltages having waveforms that increase stepwise with the passage of time shown in FIGS. 10 (4) and 10 (5), which will be described later, via lines 42a and 42b. Output. The cycle of the voltage output from the reference voltage source circuit 41 is selected to be equal to one horizontal scanning period WH.

FIG. 2 is a block diagram showing a specific structure of the source driver 37, and FIG. 3 shows one horizontal scanning period WH.
5 is a waveform diagram for explaining the operation of the source driver 37 in FIG. The source driver 37 is a shift register S
R, the data memory DM, the selector SE, the subtraction counter CNT, the detection decoder DE, and the switch circuit AS.
And W. In FIG. 2, reference numeral n indicates the number of lines, and the gradation display data is 3 bits D0 to D2.
When it consists of n may be, for example, n = 3.

A start pulse signal SP and a clock signal CK sequentially generated are input to the shift register SR. Based on this, the shift register SR has
(3) to memory control signals SR1, SR2, ..., S for each source line O1 to ON shown in FIG.
R (N-1) and SRN are sequentially derived. Serial 3-bit gradation display data D given from the display control circuit 39
Reference numerals DA1, DA2, DA3, ..., D shown in FIG. 3B correspond to the source lines O1 to ON.
As indicated by AN, the signals are sequentially input to the source driver 37. The gradation display data D0 to D3 input to the source driver 37 are sequentially stored in the data memory DM in response to the memory control signals SR1 to SRN.

The alternating signal FR is given to the selector SE, and the signal levels of the gradation display data D0 to D2 are converted according to the signal level of the alternating signal FR and given to the subtraction counter CNT. The subtraction counter CNT is shown in FIG.
In response to the hold signal LS given through the line 45 for each horizontal scanning period WH shown in (7), the parallel 3-bit gradation display data D0 to D2 output from the selector SE are supplied to all sources. Store and latch corresponding to lines O1 to ON. The subtraction counter CNT is further supplied to the gradation clock signal CLK via the line 46.
The subtraction counter CNT outputs a high level signal until the number of gradation clock signals CLK equal to the number of gradations indicated by the gradation display data are input.

The detection decoder DE has a subtraction counter CNT.
Is detected to be low level, and when the output of the subtraction counter CNT becomes low level, a predetermined signal is output to the switch circuit ASW. In the switch circuit ASW, the first and second reference voltages are supplied to the line 42.
a and 42b, and the gradation display data D
Voltages corresponding to 0 to D2 are applied to the source lines O1 to ON via the connection terminals S1 to SN. Display control circuit 3
The horizontal synchronization signal Hsyn shown in FIG.
The above-described operation is performed within one horizontal scanning period WH defined by

FIG. 4 is a waveform diagram for explaining the operation of the display control circuit 39. The horizontal synchronizing signal Hsyn shown in FIG. 4 (2) is generated for each period of the vertical synchronizing signal Vsyn shown in FIG. 4 (1) in correspondence with each of the gate lines L1 to LM. Reference numeral 1 in FIG. 4 (2)
H, 2H, ..., MH individually indicate the horizontal scanning period WH. The gradation display data DA1 to DAN corresponding to the source lines O1 to ON are displayed in each horizontal scanning period WH.
The signal is generated from the display control circuit 39 and given to the source driver 37 as indicated by DA11, DA12, ..., DA1M in (3). In the signal shown in FIG. 4 (3), diagonal lines are drawn to collectively represent the grayscale display data DA given to the N source lines O1 to ON. FIG. 4 (4) shows the waveform of the hold signal LS generated every one horizontal scanning period WH.

The signal WHD shown in FIG. 4 (5) is the gradation display data D0 to D given in one horizontal scanning period WH.
2 generally shows the voltage levels applied to the source lines O1 to ON. In the signal shown in FIG. 4 (5), diagonal lines are drawn to collectively represent the voltage levels of the N source lines O1 to ON. In the non-interlace system, one screen of the liquid crystal display panel 36 is displayed in one vertical scanning period. The present invention can be similarly implemented in the case of the interlace system.

4 (6) to 4 (8) show gate signals G1, G2, G which are picture element control signals applied from the gate driver 38 to the gate lines L1, L2, LM, respectively.
The waveforms of M are shown respectively. For example, when the j-th gate signal Gj is at a high level, all N thin film transistors T (j, i) (j, i = 1 to N) whose gate electrodes are connected to the gate line Lj thereof are all It is turned on, and at this time, the pixel electrodes P (j, i = 1 to 1
N) is charged according to the drive voltage applied to the source line Oi. By repeating the above operation for each gate line L1 to LM a total of M times, one screen is displayed in one non-interlaced vertical scanning period. The polarity of the voltage applied to each of the picture element electrodes is inverted by a so-called AC driving method, for example, every one vertical scanning period, so that deterioration of the liquid crystal is suppressed.

FIG. 5 is a circuit diagram showing the configuration of the reference voltage source circuit 41. The reference voltage source circuit 41 is, for example, in the present embodiment, a voltage VAA set to be equal to or higher than the ground voltage.
To voltage VCC are divided into a plurality of voltages, for example, two voltages, which are output every horizontal scanning period WH. More specifically, the reference voltage source circuit 41 creates a voltage VB that is an intermediate voltage between the voltage VAA and the voltage VCC, and uses, for example, the first voltage VB to the second voltage VCC as the first reference voltage.
The voltage that gradually changes is output, and as the second reference voltage, for example, the voltage that gradually changes from the third voltage VAA to the second voltage VB is output.

The reference voltage source circuit 41 comprises a timing control circuit 61, a voltage generation circuit 62, and a voltage selection circuit 63. The timing control circuit 61 includes flip-flops FF1 to FF4; FF5 to FF8. Flip-flops FF1 to FF4; FF
The clock signal CK is commonly input to 5 to FF8, and the hold signal LS input to the flip-flops FF1 and FF5 is sequentially input to the flip-flop F of the next stage, for example, at each rising edge of the clock signal CK.
It is input to the input D of F.

The outputs Q of the flip-flops FF1 to FF8 are applied to the eight analog switches AS1 to AS8 of the voltage selection circuit 63, respectively, and control the opening and closing of the analog switches AS1 to AS8. The first reference voltage is
For example, assuming that the voltage VB changes stepwise from the voltage VCC, the output Q of the flip-flop FF1 controls conduction / interruption of the analog switch AS4, and the output Q of the flip-flop FF2 controls conduction / interruption of the analog switch AS3. The output Q of the flip-flop FF3 controls conduction / interruption of the analog switch AS2, and the output of the flip-flop FF4Q controls conduction / interruption of the analog switch AS1.

The second reference voltage is, for example, the voltage VA.
If the voltage changes from A to the voltage VB stepwise, the output Q of the flip-flop FF5 controls conduction / interruption of the analog switch AS8, and the output Q of the flip-flop FF6.
Controls the conduction / cutoff of the analog switch AS7, and the output Q of the flip-flop FF7 is the analog switch AS6.
Of the analog switch AS5 is controlled by the output Q of the flip-flop FF8.
Analog switches AS1 to A in the voltage selection circuit 63
S4: The outputs of AS5 to AS8 are commonly connected and are output as the first and second reference voltages, respectively. The output of the timing control circuit 61 is selectively switched to the analog switch A.
By giving S1 to AS8, it is possible to determine the direction in which the potentials of the first and second reference voltages change, that is, whether the potential of each reference voltage rises or falls with time. Further, the first and second reference voltages may be output by switching the changing direction for each of the plurality of horizontal scanning periods WH.

The voltage generating circuit 62 includes resistors R1 to R6,
The resistors R11 and R12 are included. Resistance R1
R6, R11, and R12 have predetermined resistance values. The resistors R11 and R12 change the voltage from the voltage VCC to the voltage VAA.
The voltage at the connection point between the resistors R11 and R12 is the voltage VB.

The resistors R1 to R3 are connected to the voltage Vcc from the voltage Vcc.
The voltage of one end of the resistor R1 is connected in series between B and
That is, the voltage VCC is input to the analog switch AS1 of the voltage selection circuit 63. The other end of the resistor R1 and the resistor R2
The voltage at the connection point with one end of the resistor R2 is input to the analog switch AS2, and the voltage at the connection point between the other end of the resistor R2 and one end of the resistor R3 is given to the analog switch AS3. Resistance R3
Of the other end, that is, the voltage VB is applied to the analog switch AS4.

The resistors R4 to R6 apply the voltage VB to the voltage VA.
It is connected in series between A and the voltage of one end of the resistor R4,
That is, the voltage VB is input to the analog switch AS5. The voltage at the connection point between the other end of the resistor R4 and one end of the resistor R5 is input to the analog switch AS6, and the voltage at the connection point between the other end of the resistor R5 and one end of the resistor R6 is given to the analog switch AS7. The voltage at the other end of the resistor R6, that is, the voltage VAA is given to the analog switch AS8.

FIG. 6 is a waveform diagram for explaining the voltage output from the reference voltage source circuit 41. FIG.
(1) is based on the concept of the third prior art described above,
It is a wave form diagram of the reference voltage which changes in steps in the horizontal scanning period WH. The reference voltage is divided into 16 stages in the horizontal scanning period WH, and the constant period T1 at a certain voltage level is 1/16 of the horizontal scanning period WH. FIG.
(2) and (3) are waveform diagrams of the first and second reference voltages output from the reference voltage source circuit 41. The first and second reference voltages are divided into eight stages in the horizontal scanning period WH, and one of the first and second reference voltages is the pixel according to the gradation display data D0 to D2. It is supplied to the electrode P. For the first and second reference voltages, the period T2 that is constant at a certain voltage level is ⅛ of the horizontal scanning period WH, which is twice as long as the period T1 in the reference voltage of the third prior art shown in FIG. 6 (1). Therefore, when applying a voltage to the pixel electrode P, a stable voltage can be applied. Further, even when the timing for controlling conduction / interruption of the analog switches AS1 to AS8 deviates from a predetermined timing, a desired voltage can be applied to the pixel electrode P.

FIG. 7 is a block diagram showing a specific configuration of each source line Oi of the source driver 37, FIG. 8 is a circuit diagram of the selector SEi, and FIG. 9 is a subtraction counter CNTi and a detection decoder DEi. 3 is a circuit diagram showing a specific configuration of FIG.

First, the configurations of the selector SEi and the subtraction counter CNTi will be described. Referring to FIG. 8, selector SEi includes selector circuits 111, 112,
It is configured to include 113. The gradation display data D0 is given to the selector circuit 111, the gradation display data D1 is given to the selector circuit 112, and the gradation display data D2 is given to the selector circuit 113. In FIG. 8, the selector S to which the 3-bit gradation display data D0 to D2 is input
Although the configuration of Ei is shown, the configuration may be such that n-bit gradation display data D0 to Dn-1 is input. In that case, the gradation display data Dn-1 of the most significant bit is given to the selector circuit 113, and the remaining gradation display data D0 to Dn-2 is inputted to the circuit having the same configuration as the selector circuit 111. .

Since the selector circuits 111 and 112 have the same structure, the selector circuits 111 and 112 are designated by the same reference numerals.
Will be described as a representative. The selector circuit 111 is AND
Circuits 115 and 116, NOR circuit 117, inverter circuits 118 and 119, and clocked inverter circuit 1
40 and 141 are included.

The gradation display data D0 is input to one input of the AND circuit 115, and the signal FR * (* means inversion) which is the inverted AC signal FR is input to the other input. The gradation display data D is input to one input of the AND circuit 116.
A signal obtained by inverting 0 by the inverter circuit 119 is input, and the AC signal FR is input to the other input. AND
The outputs of the circuits 115 and 116 are applied to one and the other inputs of the NOR circuit 117.

The output of NOR circuit 117 is applied to inverter circuit 118 and clocked inverter circuit 140. The output of the clocked inverter circuit 141 to which the output of the inverter circuit 118 is given and the output of the clocked inverter circuit 140 are commonly connected to form the grayscale display data DS0. To the clocked inverter circuit 141, gradation display data DS2, which will be described later, is given as a clock signal, and conduction / operation is performed between a conduction state in which the gray scale display data DS2 operates as an inverter and a cutoff state in which the output has high impedance.
The interruption is controlled. In addition, the clocked inverter circuit 1
40 is a signal D obtained by inverting the gradation display data DS2.
S2 * is given as a clock signal to control conduction / interruption. Therefore, depending on the signal level of the gradation display data DS2, the clocked inverter circuits 140, 14
One of the outputs of 1 is output as the gradation display data DS0.

The selector circuit 113 is an AND circuit 11
5, 116, NOR circuit 117, and inverter circuit 1
And 19 are included. In the selector circuit 113,
The output of the NOR circuit 117 becomes the gradation display data DS2.

With reference to FIG. 9, the subtraction counter CNTi
Is an inverter circuit N0, N1, INV1 and NAND
Circuits NA0, NA1, NB0, NB1 and NAND1,
It is configured to include flip-flops F0 and F1. Of the parallel 3-bit grayscale display data DS0 to DS2 from the selector circuit SEi, DS0 and DS1 are given to one input terminal of the NAND circuits NA0 and NA1, and the D-type flip-flop F0 with RS (reset, set), F1
To the set input terminal S *. Further, gradation display data DS0, D input to the inverter circuits N0, N1
S1 is given to one input terminal of the NAND circuits NB0 and NB1 and inputted to the reset input terminals R * of the flip-flops F0 and F1 respectively.

NAND circuits NA0, NA1; NB0, N
The hold signal LS via the line 45 is input to the other input of B1. Flip-flop F
The outputs Q * of 0 and F1 are applied to their own data input terminals D, respectively.

The output of the NAND circuit NAND1 is applied to the clock input terminal CK of the first-stage flip-flop F0. The grayscale clock signal CLK via the line 46 is input to one input of the NAND circuit NAND1.
The output of the NOR circuit NOR1 described later is inverted by the inverter circuit INV1 and is given to the other input.
The output Q of the flip-flop F0 is given to the clock input terminal CK of the flip-flop F1.

The detection decoder DEi is a NOR circuit NOR.
1, NOR3, NAND circuit NAND2, and inverter circuit INV2. The outputs Q * of the flip-flops F0 and F1 are given to the NOR circuit NOR1. N
The output of the OR circuit NOR1 is the above-mentioned subtraction counter CNT.
It is supplied to the inverter circuit INV1 provided in i and is also supplied to the inverter circuit INV2.

The output of the inverter circuit INV2 is NAN.
It is given to one input of the D circuit NAND2. The other input of the NAND circuit NAND2 is supplied to the gray scale display data DS2.
Is given. The output of the NOR circuit NOR1 is given to one input of the NOR circuit NOR3, and the gradation display data DS2 is given to the other input.

The output of the NAND circuit NAND2 controls conduction / interruption of the analog switch ASWia to which the first reference voltage is supplied, and the output of the NOR circuit NOR3 outputs the analog switch ASWi to which the second reference voltage is supplied.
Control conduction / interruption of b. The switch circuit ASWi includes analog switches ASWia and ASWib. Each of the analog switches ASWia and ASWib conducts when the input signal is at a high level and shuts off when the input signal is at a low level. Becomes a high impedance state.

Any of the analog switches ASWia,
Conduction of ASWib causes the lines 42a, 4a
The first or second reference voltage supplied to 2b is shown in FIG.
Is applied to the corresponding source line Oi via the connection terminal Si shown in FIG.

Referring again to FIG. 7, the source driver 37
The operation of will be described. A data memory DMi individually corresponding to the i-th (i = 1 to N) source line Oi
Is gradation display data D0 to D2 consisting of serial 3 bits.
Are sampled and stored when the memory control signal SRi from the shift register SR is applied. The data stored in the data memory DMi is given to the selector SEi.

First and second from the reference voltage source circuit 41
Between the lines 42a and 42b to which the reference voltage is applied and the source lines O1 to ON, in the switch circuit ASW, analog switches ASW1a and ASW1b, which are switching elements for voltage application, ASW2a and ASW2.
b; ...; ASWNa and ASWNb are individually interposed.

Further, the source driver 37 shown in FIG. 7 has a structure in which the gradation clock signal CLK is supplied from the outside, but a circuit for generating the gradation clock signal CLK is provided in the source driver 37. Thus, the number of signal input terminals provided in the source driver 37 can be reduced by one.

Next, the operation of the subtraction counter CNTi shown in FIG. 9 will be described. When the hold signal LS is input to the subtraction counter CNTi, the flip-flops F0, F
The gradation display data DS0, DS from the selector SEi
Each bit of 1 is loaded. Flip-flop F0,
The gradation display data loaded in F1 is sequentially subtracted in response to the gradation clock signal CLK. When all the outputs Q of the flip-flops F0 and F1 forming the subtraction counter CNTi are at a low level of logic "0", this is detected by the detection decoder DEi.

The analog switch ASWi remains conductive until the detection signal from the detection decoder DEi is input, and one of the first and second reference voltages is supplied from the output terminal Si to the source line. It is output to Oi. When the detection signal from the detection decoder DEi is given, the analog switch ASWi is cut off, and the impedance of the source driver 37 seen from the output terminal Si becomes a high impedance state.

At the same time, the output of the NOR circuit NOR1 passes through the inverter circuit INV1 and the NAND gate NA.
The grayscale clock signal CLK is given to the ND1 so that it is not given to the first stage flip-flop F0. In this way, the subtraction counting operation of the subtraction counter CNTi is stopped, and this state is maintained until the hold signal LS is input again.

FIG. 10 is a timing chart for explaining the operation of the source driver 37. When a gate signal Gj (j = 1 to M) having the waveform shown in FIG. 10A is applied to a certain gate line Lj, horizontal scanning from time t0 to time t2 when the gate signal Gj is at a high level. In the period WHj, the transistor T (j, i = 1 to 1 whose gate electrode is connected to the gate line Lj
N) is conducting, and the conducting transistor T (j,
The voltage applied to the source lines O1 to ON via i = 1 to N) is applied to the pixel electrodes P (j, i = 1 to N). Further, the horizontal scanning period W from time t2 to time t4
At Hj + 1, the gate signal Gj + 1 shown in FIG.
Is at a high level. The period WHj is a data non-inversion period, and the period WHj + 1 is a data inversion period. Table 1 below shows the number of gradations of the gradation display data D0 to D2 in the data inversion period and the non-inversion period. In the present embodiment, the gradation display data D0 to D
2 is output as it is in the data non-inversion period, and all bits are inverted and output in the data inversion period.

[0084]

[Table 1]

Hold signal LS shown in FIG. 10 (3)
Is generated in synchronization with the horizontal synchronizing signal Hsyn shown in FIG. The display control circuit 39 sends the synchronization signal to the line 49.
(See FIG. 1), whereby the reference voltage source circuit 41 derives the first reference voltage shown in FIG. 10 (4) to the line 42a after time t0, and is shown in FIG. 10 (5). The second reference voltage is derived on line 42b.

During one horizontal scanning period WH, the number of gray scale clock signals CLK that is ½ or more of the number of gray scales represented by the gray scale display data is time-sequentially derived. In this embodiment, as shown in FIG. 10 (6), it is assumed that 8-gradation display is performed because the gradation display data is composed of 3-bit data, and four gradation clock signals are generated in each horizontal scanning period WH. CLK is generated. The number of gradation clock signals CLK generated in the horizontal scanning period WH may be a value exceeding 4. Source line Oi
Which of the first and second reference voltages is applied is determined by the logical value of the gradation display data D2.
In the data non-inversion period, the second reference voltage is applied when the logic of the gradation display data D2 is "0", and the first reference voltage is applied when the logic is "1". In the data inversion period, the logic of the gradation display data D2 is "0".
When, the first reference voltage is applied, and when the logic is "1", the second reference voltage is applied.

Here, if the gradation display to be displayed in the period WHj is the number of gradations 4, it is shown in FIG. 10 (7) until time t1 when the fourth gradation clock signal CLK rises in the period WHj. The output signal from the detection decoder DEi becomes high level, the analog switch ASWib becomes conductive, and the second reference voltage is applied from the connection terminal Si to the source line Oi.
Given to. The output signal in the period WHj is NOR
The output of the circuit NOR3 is shown. At times t0 to t1, FIG.
The second reference voltage is applied to the source line Oi as it is, as indicated by the driving voltage 0 (9).

After time t1, since the analog switch ASWi is cut off as described above, the driving voltage corresponding to the gradation number 4 remains applied to the picture element electrode P, and the picture element electrode of the display panel is kept. Electric charges are accumulated and a voltage is held in the display portion of the liquid crystal layer in the vicinity. Further, in FIG. 10 (8),
The alternate long and short dash line indicates the opposite voltage VC applied to the opposite electrode. The counter voltage VC is equal to or lower than the voltage VAA in the period WHj, which is the data non-inversion period from time t0 to t2.
For example, it becomes the ground voltage GND.

In the source driver 37, if the AC drive is performed every horizontal scanning period WH, the counter voltage VC is equal to or higher than the voltage VCC in the period WHj + 1 which is the data inversion period from time t2 to t4. It becomes a voltage, for example, voltage VDD. If the number of gradations indicated by the gradation display data is 3 in the horizontal scanning period WHj + 1 from time t2 to time t4, the output signal becomes high level from time t2 to time t3, and the analog switch ASWia becomes conductive. . The output signal in the period WHj + 1 indicates the output of the NAND circuit NAND2. Time t3
Then, the analog switch ASWia remains conductive until the output signal becomes low level.

At time t2 to t3, the analog switch ASW
Since ia is conducting, the first reference voltage is derived as a drive voltage from the line 42a to the source line Oi via the analog switch ASWia and the connection terminal Si. The driving voltage corresponding to the number of gradations 3 is held in the pixel electrode P (j, i = 1 to N) via the transistors T to N which are in conduction.

Such an operation is repeated for each gate line L1 to LM for each horizontal scanning period WH, and the pixel electrode P
The drive voltage corresponding to the grayscale display data of is held for one vertical scanning period.

FIG. 11 is an equivalent circuit diagram showing the liquid crystal display panel 36 in a simplified manner to explain the principle of the present invention. In the present invention, consider a circuit having a so-called low-pass filter function in which the resistance Rs of one source line Oi to be driven by the source driver 37 and the electrostatic capacitance Cs of the source line Oi are connected in series.

The equivalent capacitance of the picture element electrode P is indicated by reference numeral CL. The capacitance CL of this picture element electrode P
Is sufficiently smaller than the capacitance Cs of the source line Oi (Cs >> CL). Therefore, the voltage applied to the pixel electrode P has the same value as the voltage at the connection point 51 between the resistor Rs and the electrostatic capacitance Cs. Therefore, in the equivalent circuit shown in FIG. 11 having the function as the low-pass filter, the reference voltage is applied to the source line Oi through the analog switch ASWi to charge the pixel electrode P. For example, when the time constant Cs · Rs = 10 ⁻⁷ , the conduction time of this analog switch ASWi is at least 20 to 30.
It may be μsec or more.

As described above, according to the present invention, the resistance Rs and the electrostatic capacitance Cs of the source line Oi which the liquid crystal display panel 36 inevitably has are positively utilized to hold the voltage at the pixel electrode P. Let Further, in another embodiment of the present invention, the gate line L (j-1) and the source line which are scanned one time earlier in the scanning direction than the gate line Lj to which the gate electrode of the transistor T is connected. An auxiliary capacitance may be formed between the Oi and Oi on one of the substrates on which the pixel electrodes P are formed to substantially increase the capacitance for holding a voltage on the pixel electrodes P. .

FIG. 12 is a timing chart for explaining the operation of the source driver 37a in the display device 100a which is another structural example of the present embodiment. The configuration of the source driver 37a is the same as that of the source driver 37 described above, and thus the description thereof is omitted. Source driver 37
In the above, the AC conversion is performed every one horizontal scanning period WH, but the source driver 37a performs the AC conversion every plurality of horizontal scanning periods WH. Therefore, in the horizontal scanning periods WHj and WHj + 1 shown in FIG. 12, the counter voltage VC shown in FIG. 12 (9) is, for example, the ground voltage GND.

The signals shown in FIGS. 12 (1) to 12 (6) in the timing chart shown in FIG.
Since it is the same as the signals shown in (1) to (6), description thereof will be omitted. In the horizontal scanning period WHj from time t10 to time t12 in FIG.
In the horizontal scanning period WHj + 1 from 12 to t14, the display with the gradation number 6 is performed.

The output signal shown in FIG. 12 (7) becomes high level until time t11 when the gradation clock signal CLK rises for the second time, and the analog switch ASWib is turned on. The output signal in the period WHj is the NOR circuit NOR
3 shows the output. By turning on the analog switch ASWib, the drive voltage shown in FIG. 12 (8) has the same waveform as the second reference voltage from time t10 to time t11. Time t1 when the analog switch ASWib is cut off
After 1, the voltage at time t11 is held.

In the horizontal scanning period WHj + 1, the number of gradations is 6
Therefore, the analog switch ASWia conducts,
The first reference voltage is output until time t13, and the voltage at time t13 is held until time t14. Period WHj +
The output signal at 1 indicates the output of the NAND circuit NAND2.

FIG. 13 shows a reference voltage source circuit 41 in a display device 100b which is still another configuration example of this embodiment.
It is a figure for demonstrating the voltage output from b. FIG.
3 (1) is a waveform diagram of the reference voltage of the fourth prior art which linearly changes from the voltage VAA to the voltage VCC in one horizontal scanning period WH. 13B and 13C are waveform diagrams of the first and second reference voltages output from the reference voltage source circuit 41b. In the horizontal scanning period WH, the first reference voltage changes linearly from the voltage VB to the voltage VCC,
The second reference voltage changes linearly from the voltage VAA to the voltage VB. First according to the gradation display data D0 to D2
One of the second reference voltage and the second reference voltage is supplied to the pixel electrode P.

The rate of change of the voltage of the first and second reference voltages in one horizontal scanning period is smaller than the rate of change of the reference voltage shown in FIG. 13A, and the timing for controlling the analog switches ASWia and ASWib is controlled. Even if there is a deviation, the deviation amount of the voltage actually applied to the line Oi from the desired voltage can be reduced.

FIG. 14 is a timing chart for explaining the operation of the source driver 37b in the display device 100b. In FIG. 14, FIG. 14 (1)-
The signals shown in (3) and (6) are the same as those shown in FIG.
Since the signals are the same as those shown in (3) and (6), their explanations are omitted. In the horizontal scanning period WHj from time t20 to t22 in FIG.
In the horizontal scanning period WHj + 1 from 2 to t24, display with 6 gradations is performed.

The first reference voltage shown in FIG. 14 (4) changes linearly from the voltage VB to the voltage VCC.
The second reference voltage shown in (5) changes linearly from the voltage VAA to the voltage VB.

The output signal from the detection decoder DEi shown in FIG. 14 (7) becomes high level until time t21 when the gradation clock signal CLK rises for the second time, and the analog switch ASWib becomes conductive. The output signal in the period WHj indicates the output of the NOR circuit NOR3. By turning on the analog switch ASWib, the state shown in FIG.
The drive voltage shown in (8) has the same waveform as the second reference voltage from time t20 to time t21. Analog switch A
After time t21 when SWib is cut off, the voltage at time t21 is held.

In the period WHj + 1, since the number of gradations is 6, the analog switch ASWia is rendered conductive, so that the driving voltage becomes the voltage VB at the time t22. Period WHj +
The output signal at 1 indicates the output of the NAND circuit NAND2. The drive voltage is the same as the first reference voltage at time t2.
It increases linearly from 2 to time t23 at time t23
After that, the voltage at time t23 is held until time t24.

FIG. 15 is a block diagram for explaining the configuration of the source driver 137 in the display device 100c according to the second embodiment of the present invention, and FIG. 16 shows a part of the source driver 137 extracted. It is a circuit diagram.
In the source driver 137, the same components as those of the source driver 37 described above are designated by the same reference numerals and the description thereof will be omitted.

The feature of the source driver 137 is that a switch circuit SW is provided in place of the analog switch circuit ASW in the source driver 37, and further a discharge circuit DC is provided. The switch circuit SW is the first
P-channel MOS field-effect transistors (hereinafter abbreviated as “P-channel transistors”) SW1a, SW2a, ..., SWNa to which a reference voltage is applied, and N-channel MOS field-effect transistors (hereinafter, referred to as a second reference voltage) "N-channel transistor" is abbreviated) S
W1b, SW2b, ..., SWNb. The P-channel transistor SWia and the N-channel transistor SWib are paired, and the output of the detection decoder DEi is given to each gate. The outputs of the P-channel transistor SWia and the N-channel transistor SWib are commonly connected and connected to the terminal Si via the discharge circuit DC.

The discharge circuit DC includes analog switches DC1, DC2, ..., DCN. The analog switch DCi has an input terminal connected between the switch circuit SWi and the terminal Si, an output terminal connected to a predetermined voltage Vh, and conduction / cutoff is controlled by a discharge signal dis described later.

The source driver 137 comprises a P-channel transistor SWia and an N-channel transistor SWib as a switch for controlling the output of the first and second reference voltages, which is two analog switches in the above-mentioned source driver 37. Therefore, it is possible to reduce the area on the semiconductor chip necessary for forming the source driver 37. However, the P-channel transistor SW
The potential of ia can be raised but cannot be lowered, and the potential of the N-channel transistor SWib cannot be raised but can be lowered. Therefore, it is necessary to discharge by the discharge circuit DCi. . In addition, in the present embodiment, as will be described later, the voltage Vh
Is set to the voltage VB, the P-channel transistor SW
The first reference voltage applied to ia is from voltage VB to voltage V
N-channel transistor S with voltage rising to CC
The second reference voltage applied to Wib needs to be a voltage that drops from the voltage VB to the voltage VAA.

Operations of the switch circuit SWi and the discharge circuit DCi will be described with reference to FIG.
In FIG. 16, 6-bit gradation display data D0 to D5 is given to the selector SEi. In the selector SEi and the subtraction counter CNTi shown in FIGS. 8 and 9, the most significant bit is the gradation display data D2.
However, in the selector SEi and the subtraction counter CNTi shown in FIG. 16, the most significant bit is the gradation display data D.
It is 5.

NAND circuit NAN of detection decoder DEi
D2 is the P-channel transistor SWi when the gradation display data DS5, which is the most significant bit, is at the high level.
It is a circuit for driving a. NAND circuit NAND
Reference numeral 2 makes the transistor SWia conductive while the output of the NOR circuit NOR1 is at a low level, and outputs the first reference voltage via the transistor SWia. When the output of the NOR circuit NOR1 becomes high level, the NAND circuit N
AND2 outputs a high level, and the transistor SWia
Is cut off. Since the transistor SWia is cut off, the output of the output terminal becomes a high impedance state.

The NOR circuit NOR3 is a circuit for driving the N-channel transistor SWib when the gradation display data DS5 is at low level. N
The OR circuit NOR3 makes the transistor SWib conductive while the output of the NOR circuit NOR1 is at the low level, and outputs the second reference voltage via the transistor SWib. When the output of the NOR circuit NOR1 becomes high level,
The NOR circuit NOR3 outputs a low level and the transistor SWib is cut off. When the transistor SWib is cut off, the output of the output terminal becomes a high impedance state.

The discharge circuit DCi includes a P-channel transistor TrP and an N-channel transistor TrN.
And an inverter circuit NT1. The source of the transistor TrP and the drain of the transistor TrN are commonly connected, and the output of the switch circuit SWi is given to the connection point. Also, the transistor T
The drain of rP and the source of the transistor TrN are commonly connected, and a predetermined voltage Vh is applied to the connection point. The gate of the transistor TrN receives the discharge signal dis, and the gate of the transistor TrP receives the discharge signal dis.
The signal inverted at T1 is given. Therefore, when the discharge signal dis becomes high level, the transistors TrN and TrP become conductive, and the voltage applied to the terminal Si becomes the voltage Vh. In the following description of the present embodiment, the voltage Vh is the voltage VB.

FIG. 17 is a timing chart for explaining the operation of the source driver 137. FIG.
Each of the signals shown in (2) to (4), (8), and (10) is the same as the above-mentioned signals shown in (1) to (3), (6), and (9) of FIG. Is omitted. FIG.
The signal shown in (1) represents the alternating signal FR that defines the cycle in which the above-described AC driving is performed. Period WHj from time t31 to time t34 when the AC signal FR is at high level
Is a period in which the gradation display data is not inverted by the selector SEi, and a period WHj + 1 from time t34 to time t37 is a period in which the gradation display data is inverted by the selector SEi. In Table 2 below, the gradation display data D0 to D2 and the gradation display data DS0a to D0 output from the selector SEi in the inversion period and the non-inversion period are shown.
S2a and DS0b to DS2b are shown.

[0114]

[Table 2]

When 8-gradation display is performed in the liquid crystal display device 100c, in the non-inversion period, the first reference voltage selected when the gradation display data D2, which is the most significant bit, is at the high level, The voltages corresponding to the gradation numbers 5, 6, 7, and 8 are output, and the second reference voltage selected when the gradation display data D2 is at the low level is
The voltages corresponding to the gradation numbers 4, 3, 2, 1 are output.

In the inversion period, the voltage corresponding to the number of gradations 4, 3, 2, 1 is output as the first reference voltage selected when the gradation display data D2 is at the high level.
As the second reference voltage selected when the gradation display data D2 is at the low level, the voltages corresponding to the gradation numbers 5, 6, 7, and 8 are output.

Before the hold signal LS rises at time t31, the discharge signal dis rises at time t30, and the drive voltage shown in FIG. 17 (11) becomes the voltage VB defined as the voltage Vh.

Here, assuming that the gradation display to be displayed in the period WHj is the number of gradations 2, it is shown in FIG. 17 (9) until time t32 when the third gradation clock signal CLK rises in the period WHj. The output signal from the detection decoder DEi becomes high level, the transistor SWib becomes conductive,
The second reference voltage is applied to the source line Oi from the connection terminal Si. More specifically, since the logic of the grayscale display data DS2b when displaying with the grayscale of 2 in the non-inversion period is “0”, the output of the NOR circuit NOR1 causes N
The output of the OR circuit NOR3 becomes high level and the transistor SWib becomes conductive. Further, while the output of the NOR circuit NOR3 is at the high level, the output of the NAND circuit NAND2 is also at the high level and the transistor SWia is cut off. The output signal in the period WHj indicates the output of the NOR circuit NOR3.

From time t31 to t32, FIG.
, The second reference voltage is directly applied to the source line Oi as a drive voltage. After time t32, since the transistor SWib is cut off as described above, the drive voltage corresponding to the gray scale number 2 remains applied to the picture element electrode P, and the electric charge is generated in the picture element display portion of the display panel. The voltage is accumulated and held. At the time t33 between the fourth rise of the clock signal CLK and the end of the period WHj in the period WHj, the discharge signal dis rises, so that the transistors TrP and TrN become conductive and the voltage level of the drive voltage. Becomes the voltage VB.

If the gradation display to be displayed in the horizontal scanning period WHj + 1 from time t34 to time t37 is the number of gradations 6, the output signal becomes high level from time t34 to time t35, and the transistor SWib becomes conductive. To do. The logic of the gray scale display data DS2b at the time of displaying 6 gray scales in the inversion period is the same as the logic of the gray scale display data DS2b in the non-inversion period described above, and the outputs of the NOR circuit NOR3 and the NAND circuit NAND2 are also output. Will be the same. The output signal in the period WHj + 1 indicates the output of the NOR circuit NOR3.

At time t35, the transistor SWib remains conductive until the output signal becomes low level. Since the transistor SWib is conducting from time t34 to time t35, the second reference voltage is derived as the drive voltage on the source line Oi. Even after the transistor SWib is cut off at the time t35, the driving voltage corresponding to the number of gradations 6 is held in the pixel electrode P through the transistor T which is conducting. The held voltage is discharged when the discharge signal dis rises at time t36, and the voltage level of the driving voltage becomes the voltage VB. Since the initial voltage of the horizontal scanning period is VB which is the starting voltage for any reference voltage, that is, the second voltage, the display panel is not affected by the voltage held by the charges of the pixel electrodes. Can be displayed.

Such an operation is repeated for each gate line L1 to LM for each horizontal scanning period WH.
The drive voltage corresponding to the grayscale display data of is held for one vertical scanning period.

FIG. 18 is a timing chart for explaining the operation of the source driver 137a in the display device 100d which is another structural example of the present embodiment. FIG.
Each signal shown in 8 (2) to (8) corresponds to the above-mentioned FIG. 17 (2).
Since the signals are the same as those shown in (8) to (8), the description thereof will be omitted. In the source driver 137, one horizontal scanning period W
Although the signal level of the alternating signal FR is switched for each H to perform the AC driving, the source driver 137a performs the AC driving for each of a plurality of predetermined horizontal scanning periods WH. The alternating signal FR shown in FIG. 18 (1) is the time t40.
From time t47 to time t47, the level is always high. FIG.
In the timing chart shown in FIG. 8, the gray scale number 2 is displayed in the period WHj, and the gray scale number 6 is displayed in the period WHj + 1.
Will be displayed.

Since the alternating signal FR is always at the high level, the output of the above-mentioned selector SEi is as shown in Table 3 below.

[0125]

[Table 3]

Since the alternating signal FR is always at the high level, the first reference voltage shown in FIG.
The voltages corresponding to 7 and 8 are obtained, and the second voltage shown in FIG.
The reference voltage is a voltage corresponding to the gradation numbers 4, 3, 2, 1. The output signal shown in FIG. 18 (9) is at the high level until time t42 when the grayscale clock signal CLK rises for the third time, and the transistor SW to which the second reference voltage is applied.
Conduct ib. The output signal in the period WHj is N
The output of the OR circuit NOR3 is shown.

By turning on the transistor SWib, the drive voltage shown in FIG. 18 (10) has the same waveform as the second reference voltage from time t41 to time t42.
After the time t42 when the transistor SWib is cut off,
The voltage at time t42 is held. At time t43,
When the discharge signal dis rises, the transistors TrP and TrN become conductive and the drive voltage becomes the voltage VB.

In the period WHj + 1, since the number of gradations is 6, from time t44 to time t45, the output signal becomes the low level, the transistor SWia becomes conductive, the first reference voltage is output, and the voltage at time t45 becomes , And is held until time t46 when the discharge signal dis rises. More specifically, since the logic of the grayscale display data DS2b when displaying the grayscale number 6 in the non-inversion period is "1", the output of the inverter circuit INV2 which is the inverted output of the NOR circuit NOR1 is used. , NAND circuit NA
The output of ND2 becomes low level and the transistor SWi
a conducts. Further, while the output of the NAND circuit NAND2 is at the low level, the output of the NOR circuit NOR3 is also at the low level, and the transistor SWib is cut off. The output signal in the period WHj + 1 is the NAND circuit N
The output of AND2 is shown. When the discharge signal dis rises, the drive voltage becomes the voltage VB.

FIG. 19 shows a source driver 13 in a display device 100e which is still another configuration example of the present embodiment.
7 is a timing chart for explaining the operation of 7b. In FIG. 19, the signals shown in (2) to (5) and (8) of FIG. 19 are the same as the signals shown in (2) to (5) and (8) of FIG. The horizontal scanning period WHj from time t51 to time t54 in FIG.
Then, the gradation number 2 is displayed, and from time t54 to time t5.
In the horizontal scanning period WHj + 1 up to 7, it is assumed that the display with the gradation number 6 is performed.

The first reference voltage shown in FIG. 19 (6) is the same as the first reference voltage shown in FIG. 14 (4), and changes linearly from voltage VB to voltage VCC. Also,
The second reference voltage shown in (7) of FIG.
It is the same as the second reference voltage shown in (5) and changes linearly from the voltage VAA to the voltage VB.

The output signal shown in FIG. 19 (9) becomes high level until time t52 when the gradation clock signal CLK rises for the third time, and the N-channel transistor SWib is made conductive. The output signal in the period WHj is the NOR circuit N
The output of OR3 is shown. By turning on the transistor SWib, the drive voltage shown in FIG. 19 (11) has the same waveform as the second reference voltage from time t51 to time t52. Time t52 when the transistor SWib is cut off
After that, the voltage at time t52 is held. Time t
At 53, when the discharge signal dis rises, the transistors TrP and TrN become conductive and the drive voltage becomes the voltage VB.

In the period WHj + 1, since the number of gradations is 6, the output signal becomes the low level until time t55 when the gradation clock signal CLK rises for the second time, the P-channel transistor SWia becomes conductive, and the time t55 is reached. One reference voltage is output and the voltage at time t55 is held until time t56 when the discharge signal dis rises. The output signal in the period WHj + 1 indicates the output of the NAND circuit NAND2. After time t56, the voltage becomes VB until time t57 when the next horizontal scanning period WH starts.

Before the writing of the next gradation display data signal is started, the charge held in the liquid crystal element is discharged and then the writing based on the next gradation display data is performed. A liquid crystal display device having stable and high display quality can be realized without being affected by electric charges based on existing gradation display data.

In each of the above-described embodiments, the case where 8-bit display is performed by using 3-bit data as the gradation display data has been mainly described. However, data having a larger number of bits is used. , And by providing a number of reference voltages corresponding to the data, it is possible to perform display with a larger number of gradations.

FIG. 20 shows the configuration of the source driver 237 as the third embodiment of the present invention. In the present embodiment, parts corresponding to the source driver 37 shown in FIG. 7 are designated by the same reference numerals, and duplicated description will be omitted. The source driver 237 includes a shift register SR and a data memory D.
M, selector SE, subtraction counter CNT, detection decoder DE, a plurality of P-channel transistor elements PchTr,
And a plurality of N-channel transistor elements NchTr.

For the voltage source used in this embodiment, the concept of the reference voltage source circuit 41 of FIG. 5 is applied, and the voltage gradually increases from a predetermined first voltage to a second voltage higher than the first voltage. Or a first reference voltage that gradually decreases from a second voltage to a first voltage and a third reference voltage that gradually increases from a second voltage to a third voltage higher than the second voltage, or a third reference voltage from a second voltage to a second voltage. A second reference voltage that gradually drops to a voltage and a third reference voltage
Higher than the fourth reference voltage and the third reference voltage that gradually increases from the voltage to the fourth voltage higher than the third voltage or gradually decreases from the fourth voltage to the third voltage A fourth reference voltage that gradually increases to the fifth voltage or that gradually decreases from the fifth voltage to the fourth voltage is created as the gradation display drive voltage and corresponds to the gradation display data. When the time elapses, it is configured to generate a reference constant voltage that becomes the first voltage and the third voltage at each predetermined cycle.

FIG. 21 shows the source driver 2 of this embodiment.
37 shows a more specific electrical circuit configuration of 37. Portions corresponding to the configuration of FIG. 9 are designated by the same reference numerals, and redundant description will be omitted. That is, one of the plurality of P-channel transistor elements PchTr has a fourth reference voltage and a third reference voltage.
The reference voltage of is connected. The second reference voltage and the first reference voltage are applied to one of the plurality of N-channel transistor elements NchTr.
The reference voltage of is connected.

The shift register SR shown in FIG. 20 has one of the data memories DM according to the clock signal CK for sampling based on the start pulse signal SP.
Generate memory control signals such that one takes in the data.
The data memory DM sequentially takes in 4-bit gradation display data D0 to D3 input from the outside in accordance with the memory control signal. The selector SE determines the subtraction counter C according to the level corresponding to the gradation display data D0 to D3.
Switch the count mode of NT. The switching is performed according to the input data D3. When the logic of the input data D3 is high level “1”, that is, when D3 = H, the forward count mode, the logic of the input data D3 is low level “0”,
That is, when D3 = L, each operates in the reverse count mode.

FIG. 22 shows gradation display data D0 to D3,
Grayscale display data DS0a, DS1a; DS0b, which is the output of the selector SE in the inversion period and the non-inversion period.
The relationship with DS0b is shown. The input data D0 to D3 are the same in the inversion period and the non-inversion period. When the input data D3 indicated by d3L is logic "0", the grayscale display data DS1a, DS0a in the inversion period and the grayscale display data DS1b, DS0b in the non-inversion period are the input data D1, D0 indicated by hatching. It needs to be logically inverted.
When the input data D3 represented by d3H is logic "1",
The input data D1 and D0 indicated by hatching are logically displayed as they are as gradation display data DS1a and DS0; DS1b and DS.
It must be output as 0b.

FIG. 23 shows, as the selector SE of this embodiment, a specific electrical configuration that satisfies the logical relationship shown in FIG. Since the selector circuits 211 and 212 are partially the same in configuration as the selector circuits 111 and 112 in FIG. 8, corresponding parts are designated by the same reference numerals and redundant description will be omitted. Clocked inverter circuit 140, 14
The inverted input data D3 * and the input data D3 are provided as the 1 clock signal.

As shown in FIG. 21, the selector circuit 21
The outputs DS0 and DS1 of 1 and 212 are input to one input terminals of the NAND circuits NA0 and NA1 of the subtraction counter CNT similar to FIG. In addition, the inverter circuits N0, N
The gradation display data DS0 and DS1 input to 1 are NA
It is input to one of the input terminals of the ND circuits NB0 and NB1. NAND circuits NA0 and NB0; NA1 and NB1 are
Hold signal LS to the other input terminal via line 45
Is inputted and the outputs are inputted to the set input terminal S * and the reset input terminal R * of the D-type flip-flops F0 and F1 with RS (reset, set), respectively. With such a configuration, when the hold signal LS becomes logic "1", the flip-flops F0 and F of the subtraction counter CNT are
1, the gradation display data from the data memory DM is loaded via the selector SE.

The gradation display data loaded in the subtraction counter CNT is subtracted according to the gradation clock signal CLK. The NOR circuit NOR1 in the detection decoder DE is
While the outputs of the flip-flops F0 and F1 of the subtraction counter CNT hold the High level of the logic "1" even if it is 1 bit, the Low level of the logic "0" is output. When the outputs of the flip-flops F0 and F1 of the subtraction counter CNT are all at the Low level, N in the detection decoder DE
The output of the OR circuit NOR1 is inverted and becomes the High level.

In the output transistor section, the fourth side is provided on the source side of the P-channel transistors PchTrA and PchTrB.
And the third reference voltage are respectively supplied, the second and first reference voltages are respectively supplied to the source sides of the N-channel transistors NchTrC, NchTrD, and the transistors PchTrA, PchTrB, NchTrC,
The drains of the NchTrDs are commonly connected to the source line Oi.

FIG. 24 shows gradation display data D0 to D3 as input data and transistors PchTrA and Pch of the output transistor section in the inversion period and the non-inversion period.
The relationship with the outputs of chTrB, NchTrC, and NchTrD is shown. In FIG. 24 (1), the alternating signal FR has a logic "1".
24 (2) when the high level of
It shows when R is a logic "0" low level.
According to the most significant bit D3 of the input data, one of the P-channel transistors PchTrA and PchTrB or the N-channel transistors NchTrC and NchTrD is selected as indicated by hatching. Further, according to the grayscale display data D2 which is 1 bit lower than the most significant bit D3, the hatched lines are removed in each selected group of the P-channel transistors PchTrA and PchTrB or the N-channel transistors NchTrC and NchTrD as shown. , Either one of the transistor elements is selected.

FIG. 24 shows an example of 16 gradation display.
From FIG. 24A, in the non-inversion period, the gradation display data D3, which is the most significant bit, is at the Low level and the most significant bit D is
When the grayscale display data D2 that is 1 bit lower than 3 is at the Low level, the first reference voltage is selected by the detection decoder DE at n00, and the N-channel transistor Nc is selected.
It can be seen that the drive voltage corresponding to the display gradation numbers 4, 3, 2, 1 is output from hTrD. Gradation display data D3, D
When 2 is at the Low level and the High level, respectively, the second reference voltage is selected for n01, and the number of display gray levels is 8, 7, from the N-channel transistor NchTrC.
Driving voltages corresponding to 6 and 5 are output. When the grayscale display data D3 and D2 are High level and Low level, respectively, the third reference voltage is selected for n10, and the driving corresponding to the display grayscale numbers 12, 11, 10, 9 from the P-channel transistor PchTrB is performed. The voltage is output. When the grayscale display data D3 and D2 are both at the high level, the fourth reference voltage is selected for n11 and the number of display grayscales from the P-channel transistor PchTrA is 16,
The drive voltage corresponding to 15, 14, 13 is output.

From FIG. 24 (2), the grayscale display data D3, which is the most significant bit, and the grayscale display data D2, which is one bit lower than the most significant bit D3, are both L during the inversion period.
When it is at the ow level, it can be seen that at r00, the fourth reference voltage is selected by the detection decoder DE, and the drive voltage corresponding to the display gradation numbers 4, 3, 2, 1 is output from the P-channel transistor PchTrA. Gradation display data D
When D3 and D2 are Low level and High level, respectively, the third reference voltage is selected for r01 and P
From the channel transistor PchTrB to the display gradation number 8,
Drive voltages corresponding to 7, 6, and 5 are output. The gradation display data D3 and D2 are High level and Lo, respectively.
In the case of w level, the second reference voltage is selected for r10, and the drive voltage corresponding to the number of display gray scales 12, 11, 10, 9 is output from the N-channel transistor NchTrC. When the grayscale display data D3 and D2 are both at the high level, the first reference voltage is selected for r11 and N
Number of display gradations 1 from the channel transistor NchTrD
Driving voltages corresponding to 6, 15, 14, and 13 are output.

Therefore, the drive voltage output from the drain side of the P-channel transistor element or the N-channel transistor element changes in accordance with the selected reference voltage, and the liquid crystal element of the active matrix type liquid crystal display device using the TFT has it. Charge or discharge the pixel capacity.
Flip-flop F which is the content of the subtraction counter CNT
When the outputs of 0 and F1 are all logic "0", the P-channel transistor element or the N-channel transistor element is turned off, and the high impedance is cut off.
The drive voltage immediately before interruption is stored in the pixel capacitance of the liquid crystal element.

In the 1H inversion driving method, an alternating display operation is performed by alternately repeating inversion / non-inversion every 1H which is one horizontal scanning period. FIG. 25 shows an example of the timing when displaying with the number of gradations 2 by the 1H inversion drive method in which the polarity of the drive voltage that changes stepwise for each cycle of the hold signal LS is inverted. FIG. 26 shows 1H
An example of the timing when displaying with 6 gradations by the inversion driving method is shown. The drive voltage is held after the rise of the gradation clock signal CLK after counting the gradation clock signal CLK corresponding to the number of display gradations.

According to the present embodiment, it is possible to obtain a more stable sampling rate per unit time without being affected by the previous display data. By this, the expected value of the drive voltage corresponding to the gradation display level,
It is possible to improve the display quality by reducing the level difference from the driving voltage actually written in the liquid crystal element. Further, since the discharge circuit is not used, it is possible to minimize the occurrence of switching noise that occurs excessively according to the discharge pulse signal dis, and it is possible to achieve low power consumption and high display quality.

In each of the embodiments described above, the reference voltage is changed stepwise by a constant step in synchronization with the grayscale clock signal CLK, but the drive voltage of the pixel electrode and the actual display grayscale are different from each other. If there is a non-linear relationship between the two, it is possible to achieve a more suitable change by changing the voltage division ratio of the resistance of the voltage generation circuit 62 shown in FIG. Further, the reference voltage can be changed not only in a stepwise manner, but also in a waveform such as a continuous sawtooth wave.

[0151]

As described above, according to the present invention, the drive voltage required for gradation display is divided into a plurality of voltage sections. It is necessary while increasing the number of gradations because the reference voltage that changes in each section is selected according to the gradation display data and the pixel electrodes are driven when the selected reference voltage becomes the voltage corresponding to the gradation display data. The number of such signal lines can be reduced, and the number of connection terminals and the number of analog switches can be reduced. This makes it possible to reduce the size of semiconductor chips such as source drivers, reduce current consumption, reduce costs, and achieve high-density mounting. Further, since the common electrode facing the pixel electrodes arranged in a matrix can be single, a display panel which is widely used at present can be used as it is. Furthermore, it is possible to prevent display quality from deteriorating due to variations in the characteristics of semiconductor elements with a simple circuit configuration that does not use a complicated circuit configuration such as an operational amplifier.

Further, according to the present invention, the voltage corresponding to the gradation display data may be a voltage included in one of the first and second voltages, and the first voltage in one horizontal scanning period. The difference between the changing voltages of the second voltage and the second voltage can be reduced, and a desired voltage can be easily applied to the first line of the display panel to perform gray scale display.

Further, according to the present invention, when the first or second reference voltage is a rising voltage, the first or second voltage application switching element to which the reference voltage is applied is a P-channel transistor and drops. Since it is an N-channel transistor when the voltage is applied, either the first or second switching element for voltage application can be formed of a conductive type transistor, and the area of a semiconductor chip forming a circuit for driving the display panel can be reduced. Can be reduced.

Further, according to the present invention, the driving voltage corresponding to the gradation display data is divided into four voltage sections from the first to the first.
The voltage may be any voltage included in the change range of any one of the fourth reference voltages, and the change range of the first to fourth reference voltages in one horizontal scanning period can be reduced, and the desired drive can be achieved. It is possible to select a voltage with high time accuracy and easily apply it to the first line of the display panel to perform multi-gradation display.

Further, according to the present invention, when the first to fourth reference voltages are increasing voltages, the first to fourth voltage applying switching elements to which the reference voltages are applied are P-channel transistors and decrease. When the voltage is applied, since it is an N-channel transistor, any one of the first to fourth voltage applying switching elements can be composed of a conductive type transistor, and the area of a semiconductor chip forming a circuit for driving the display panel can be reduced. Can be reduced.

Further, according to the present invention, since the voltage application switching element is an analog switch, even if the reference voltage changes in either the rising or falling direction, the reference voltage supplied from the voltage source A desired driving voltage can be easily applied to the first line of the display panel within the change range,
Gradation display can be performed.

Further, according to the present invention, an analog switch is provided between the voltage application switching element and the picture element electrode, which is conducted at the end of each scanning period and supplies a predetermined voltage to the picture element electrode. Since it is provided, the voltage applied to the pixel electrode in the previous scanning period is changed to a predetermined voltage. As a result, even if the voltage to be applied to the pixel electrode differs greatly for each scanning period,
It is possible to prevent the display quality from being degraded on the display panel.

Further, according to the present invention, in the multi-gradation display on the active matrix type display panel, the drive voltage is temporally selected from the first and second reference voltages generated by dividing the required voltage range into two. Therefore, the number of signal lines and the number of switching elements can be reduced, and a large margin can be taken when determining the timing of selection.

Further, according to the present invention, it is possible to perform m gradation display of an active matrix type display panel by AC drive by dividing a necessary voltage range into n. Number of divisions n
By increasing, the number of signal lines and the number of switching elements can be relatively reduced even when the number of gradations m is increased, and a large margin can be taken when determining the timing of selection.

Further, according to the present invention, the reference voltage changes in a linear function within the voltage section divided into n, so that the desired voltage can be selected by adjusting the timing.

Further, according to the present invention, the reference voltage changes in m / n steps without each voltage section divided into n. Therefore, even when the number of gradations m increases, the number of change steps of each reference voltage is changed. It can be made smaller and the selection easier.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a liquid crystal display device 100 for explaining a first embodiment of the present invention.

FIG. 2 is a block diagram showing a specific configuration of a source driver 37.

FIG. 3 is a source driver 3 in one horizontal scanning period WH.
7 is a waveform diagram for explaining the operation of FIG.

FIG. 4 is a waveform diagram for explaining the operation of the display control circuit 39.

5 is a circuit diagram showing a configuration of a reference voltage source circuit 41. FIG.

FIG. 6 is a waveform diagram for explaining a voltage output from the reference voltage source circuit 41.

7 is a block diagram showing a specific configuration of each source line Oi of a source driver 37. FIG.

FIG. 8 is a circuit diagram of a selector SEi.

FIG. 9 is a circuit diagram showing a specific configuration of a subtraction counter CNTi and a detection decoder DEi.

FIG. 10 is a timing chart for explaining the operation of the source driver 37.

FIG. 11 is an equivalent circuit diagram showing a simplified liquid crystal display panel 36 for explaining the principle of the present invention.

FIG. 12 is a timing chart for explaining the operation of the source driver 37a in the display device 100a that is another configuration example of the first embodiment.

FIG. 13 is a diagram for explaining a voltage output from a reference voltage source circuit 41b in a display device 100b which is still another configuration example of the first embodiment.

FIG. 14 is a source driver 3 of the display device 100b.
7 is a timing chart for explaining the operation of 7b.

FIG. 15 is a display device 1 according to a second embodiment of the present invention.
12 is a block diagram for explaining a configuration of a source driver 137 in 00c. FIG.

FIG. 16 is a circuit diagram showing a part of a source driver 137 extracted.

FIG. 17 is a timing chart for explaining the operation of the source driver 137.

FIG. 18 is a timing chart for explaining the operation of the source driver 137a in the display device 100d which is another configuration example of the second embodiment.

FIG. 19 is a timing chart for explaining the operation of the source driver 137b in the display device 100e that is still another configuration example of the second embodiment.

FIG. 20 is a block diagram illustrating a configuration of a source driver 237 according to a third embodiment of the present invention.

FIG. 21 is a block diagram specifically showing the configuration of part of a source driver 237.

FIG. 22 is a chart showing logical operation of a selector in the source driver 237.

FIG. 23 is a block diagram showing an example of a specific logical configuration of a selector in the source driver 237.

FIG. 24 is a chart showing logical operation of an output unit in the source driver 237.

FIG. 25 is a timing chart for explaining the operation of the source driver 237.

FIG. 26 is a timing chart for explaining the operation of the source driver 237.

FIG. 27 is a block diagram showing a configuration of a display device 10 that is first prior art.

28 is a block diagram specifically showing the configuration of part of the source driver 12 in the display device 10. FIG.

FIG. 29 is a diagram showing the configuration of the second prior art.

FIG. 30 is a diagram showing the configuration of the third prior art.

FIG. 31 is a block diagram showing the configuration of an X driver 120 in the fourth prior art.

FIG. 32 is a timing chart of each signal in the X driver 120.

[Explanation of symbols]

36 active matrix type liquid crystal display panel 37, 37a, 37b, 137, 137a, 137b,
237 source driver 38 gate driver 39 display control circuit 41, 41b reference voltage source 42a, 42b line 100, 100a to 100e display device 140, 141 clocked inverter circuit ASW1a to ASWNa, ASW1b to ASWNb analog switch CK clock signal CLK gradation clock Signal CM Comparison circuit CNT1 to CNTN Subtraction counter D0 to D2 Gray scale display data DE1 to DEN Detection decoder DM1 to DMN Data memory L1 to LM Gate line LS Hold signal NchTrC, NchTrD N channel transistor O1 to ON Source line P (j, i) ) Pixel electrodes PchTrA, PchTrB P channel transistors S1 to SN, G1 to GM connection terminals SE1 to SEN selector SR shift register T j, i) the thin film transistor WH 1 horizontal scanning period

Claims (11)

[Claims] 1. An active matrix type in which picture element electrodes are arranged in a matrix at intersections of a plurality of first and second lines, respectively, and a dielectric layer is interposed between the picture element electrodes and a common electrode facing each other. In the display panel, a drive voltage corresponding to gradation display data is applied to the first line, and the second line is selected for each scanning period predetermined by the pixel control signal,
In a display device driven to perform gray scale display, a gray scale clock signal generating unit that sequentially generates a gray scale clock signal of a number equal to or greater than the number of gray scales in each scanning period, and is required for gray scale display. A plurality of reference voltages provided corresponding to the number of divisions are respectively changed in a certain direction in each voltage section obtained by dividing the various voltage ranges in synchronization with the gradation clock signal in each scanning period. A voltage applying switching element that is provided between the voltage source for generating each of the first lines and the voltage source for each of the first lines and is provided with each of the reference voltages, and for each of the first lines. Selecting means for selecting a reference voltage in which a voltage for driving the pixel electrode corresponding to the gradation display data is included in a voltage section; and provided for each of the first lines and for each of the scanning periods. To
Voltage application in which the grayscale clock signal from the grayscale clock signal generating means is counted, and a reference voltage selected by the selecting means is applied with reference to the time when the count value reaches the value corresponding to the grayscale display data. And a switching control means for controlling the switching element for switching from one of ON and OFF that is predetermined corresponding to the selected change direction of the reference voltage to the other. 2. In the display panel, a driving voltage applied through the first line is applied to the pixel lines which are arranged at the intersections of the first and second lines arranged in a matrix, respectively. The pixel electrode and the common electrode are applied via a pixel switching element that is conducted by a pixel control signal and are applied to the common electrode provided opposite to the pixel electrode to apply a reference constant voltage. Gradation display is performed by providing a potential difference between and, and in the plurality of predetermined horizontal scanning periods as the predetermined scanning period, a pixel element control signal is sequentially supplied to each second line, and a pixel element control signal is supplied. And a driver circuit for conducting a pixel switching element connected to a second line, and gradation display data generation for sequentially deriving the gradation display data for each first line by serial bits during the horizontal scanning period. And a data latch circuit for deriving the gray scale display data from the gray scale display data generating means by parallel bits for every one horizontal scanning period, and the gray scale clock signal generating means is provided for each horizontal scanning period. To
During the period, a number of grayscale clock signals equal to or greater than the number of grayscales to be grayscale-displayed are sequentially generated in time, and the voltage source is configured such that the voltage source supplies a predetermined first voltage to a second voltage higher than the first voltage. A first reference voltage that gradually increases from the second voltage to the first voltage, or a third reference voltage that is higher than the second voltage from the second voltage. The second reference voltage that gradually decreases from the third voltage to the second voltage, and the constant voltage serving as the reference that becomes the first and third voltages in each predetermined cycle are generated. A first and a second voltage application switching element, which is interposed between the voltage source and the first line and is supplied with the first and second reference voltages, respectively, wherein the switching control means is configured to perform the horizontal scanning period. Corresponds to each gradation display data When the count value of the subtraction counter reaches a predetermined value, the first value is set, and the subtraction counter subtracts each time the grayscale clock signal is received.
The display device according to claim 1, wherein the switching element for applying the second voltage is controlled to be turned on or off. 3. The voltage application switching element is a P-channel transistor element when the supplied reference voltage is a voltage that changes so as to increase, and the P-channel transistor element is used when the reference voltage is a voltage that changes so as to decrease. The display device according to claim 1, wherein a channel transistor element is used. 4. In the display panel, a driving voltage applied via the first line is applied to the pixel electrodes arranged at the intersections of the first and second lines arranged in a matrix in the second line. The pixel electrode and the common electrode are applied via a pixel switching element that is conducted by a pixel control signal and are applied to the common electrode provided opposite to the pixel electrode to apply a reference constant voltage. Gradation display is performed by providing a potential difference between and, and in the plurality of predetermined horizontal scanning periods as the predetermined scanning period, a pixel element control signal is sequentially supplied to each second line, and a pixel element control signal is supplied. And a driver circuit for conducting a pixel switching element connected to a second line, and gradation display data generation for sequentially deriving the gradation display data for each first line by serial bits during the horizontal scanning period. And a data latch circuit for deriving the gray scale display data from the gray scale display data generating means by parallel bits for every one horizontal scanning period, and the gray scale clock signal generating means is provided for each horizontal scanning period. To
During the period, a number of grayscale clock signals equal to or greater than the number of grayscales to be grayscale-displayed are sequentially generated in time, and the voltage source is configured such that the voltage source supplies a predetermined first voltage to a second voltage higher than the first voltage. The first reference voltage that gradually increases from the second voltage to the first voltage, the second reference voltage that gradually increases from the second voltage to the third voltage that is higher than the second voltage, or A second reference voltage that gradually decreases from the third voltage to the second voltage, and gradually increases from the third voltage to the fourth voltage higher than the third voltage, or gradually from the fourth voltage to the third voltage. And a fourth reference voltage that gradually increases from a fourth voltage to a fifth voltage higher than the fourth voltage, or that gradually decreases from a fifth voltage to a fourth voltage. Is created as the drive voltage for gradation display, and the time corresponding to the gradation display data elapses. The reference constant voltage, which is the first and third voltages, is generated for each predetermined period of time, and the voltage application switching element is interposed between the voltage source and the first line to generate the first and second voltages. , First, second, third and fourth provided with third, fourth and fourth reference voltages, respectively.
Of the voltage application switching element, the switching control means, for each of the horizontal scanning period,
Any one of the first reference voltage to the fourth reference voltage at the time when the time corresponding to the gradation display data elapses is applied to the first line, and the common electrode is 2. The display device according to claim 1, wherein a voltage is applied by switching for each horizontal scanning period so that the voltage is controlled to be held by the dielectric layer between the pixel electrode and the common electrode. 5. A P-channel transistor element is used as the first to fourth voltage application switching elements when the supplied reference voltage is a voltage that increases stepwise, and the voltage gradually decreases. The display device according to claim 4, wherein an N-channel transistor element is sometimes used. 6. The display device according to claim 1, wherein the voltage application switching element is an analog switch. 7. An analog switch is provided between the voltage application switching element and the picture element electrode, the analog switch being conductive at the end of each scanning period and supplying a predetermined voltage to the picture element electrode. 7. The method according to claim 1, wherein
The display device according to any one of the above. 8. A display panel drive for performing gradation display by interposing a dielectric layer between an active matrix type pixel electrode and a common electrode, and applying a voltage corresponding to gradation display data between the electrodes. In the method, in a predetermined cycle, the voltage gradually increases from a first voltage to a second voltage higher than the first voltage over time, or
A first reference voltage that drops from the second voltage to the first voltage;
The second voltage gradually increases from the second voltage to the third voltage higher than the second voltage, or decreases from the third voltage to the second voltage.
And a reference voltage for each of the first and second time points at the time when the time corresponding to the gradation display data has elapsed in each of the cycles.
Of the display panel, characterized in that the reference voltage is applied to the common electrode, the first and third voltages are applied to the common electrode by switching for each cycle, and the applied voltage is held by the dielectric layer between the electrodes. Driving method. 9. A dielectric layer is interposed between an active matrix type pixel electrode and a common electrode, and a voltage corresponding to gradation display data is applied between the electrodes to m (m is an integer of 2 or more). In a method of driving a display panel for displaying gradation, a predetermined first voltage to a second voltage is n (n is 1).
(Divisor of m, excluding m and m), and changing from the lowest voltage to the highest voltage in each voltage section or changing from the highest voltage to the lowest voltage in each voltage section in a predetermined cycle.
The reference voltage is created for each pixel period, and the reference voltage including the drive voltage corresponding to the gradation display data is selected in the voltage section of the first to nth reference voltages for each cycle. The voltage is applied to the common electrode at each of the cycles by applying either one of the first voltage and the second voltage, and the applied voltage is held by the dielectric layer between the electrodes. Driving method of display panel. 10. The method of driving a display panel according to claim 9, wherein the first to nth reference voltages change in a linear function within the voltage section. 11. The method according to claim 9, wherein the first to nth reference voltages are respectively increased or decreased in m / n steps within the voltage section.