JPH09318706A - Testing apparatus for semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a testing apparatus by which a DRAM is operated on a first page or a high page when the DRAM is used in the memory part of a defect analysis memory. SOLUTION: A random address from a pattern generator is converted into a serial address by using an address conversion part 1. The serial address is divided into a row address and a column address. Fail data, the row address and the column address are stored temporarily in a FIFO memory 4. After that, by the control of a memory control part 5, the read modified write operation of the fail data is performed to a DRAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory testing device for testing a semiconductor memory of the present invention.

[0002]

2. Description of the Related Art FIG. 12 is a block diagram of a conventional semiconductor memory test apparatus. This semiconductor memory testing device includes a timing generator 61, a pattern generator 62, and a failure analysis memory 63.
And a waveform shaper 64 and a logical comparator 65 to test the memory under test 66.

A pattern generator 62 outputs an address signal, test data and a control signal to be given to a memory under test 66 according to a reference clock generated by a timing generator 61. These signals are applied to the waveform shaper 64, where they are shaped into the waveform required for the test and applied to the memory under test 66. In the memory under test 66, writing / reading of test data is controlled by a control signal. The test data read from the memory under test 66 is the logical comparator 65.
The expected value data output from the pattern generator 62 is compared with the expected value data, and whether the memory under test 66 is defective or non-defective is determined based on the match / mismatch. If there is a mismatch,
The fail data is stored in the failure analysis memory 63.

FIG. 13 is a block diagram of the failure analysis memory 63. The failure analysis memory 63 includes an address selection unit 71, a memory control unit 72, and a memory unit 73.
The address selecting unit 71 divides the address signal from the pattern generator 62 into an upper address and a lower address, outputs the upper address to the memory control unit 72, and outputs the lower address to the memory unit 73. Here, the memory unit 73 There are as many high-order addresses as there are. When the fail data is output from the logical comparator 65, the memory control unit 72 outputs a write signal to the memory unit 73 indicated by the higher address and stores the fail data of the memory under test 66 in the memory unit 73. After the test, the failure analysis memory 63
The defective address of the memory under test 66 is analyzed by examining the contents of the.

[0005]

In the conventional semiconductor memory test apparatus described above, since the high speed SRAM is used for the memory portion of the failure analysis memory, the address values are # 0, #.
Serial access to access by incrementing one by one such as 1 and # 2, address value is #FFFF, # 0, # 128
The operation speed did not change with any access such as random access with random access such as 1.

In recent years, the increase in capacity of SRAM has converged, and it has become necessary to use DRAM in the memory section in order to increase the capacity of the failure analysis memory in response to the increase in capacity of the memory under test. . However, DRAM operates at high speed for serial access to access each column address within the same row address (first page or hyperpage operation, hereinafter referred to as page operation), but random access to access other row addresses one after another. Then it becomes a low speed operation. 14 (1) and 14 (2) are timing charts of the read-modify-write operation (the operation of modifying the data read from the memory and writing the data to the read memory) when random access or serial access is performed. In the figure, R1 and R2 are row addresses, C1 and C2 are column addresses, and RD1 and RD2.
Indicates read data, and WD1 and WD2 indicate write data.

The failure analysis memory (AFM) is accessed by an address generated by the pattern generator (the same as the test address pattern applied to the memory under test). Since this address is randomly generated, the AFM is When the DRAM is used, the fail fetch operation of the AFM (which is performed by the read modify write operation because fail data is accumulated) does not operate at high speed. In order to operate this at a high speed, the conventional interleave method (a method in which several memories with the same capacity are operated sequentially to make them appear to be operating at high speed) is used, but DRAM is randomly If interleaving is performed in accordance with the operation cycle at the time of access, the number of interleaves (the number of memories used for interleaving) will increase. The larger the number of interleaves, the larger the number of memories. An example of a case where two memories (operating ratio of 1: 2) having the operation cycles shown in (1) and (2) of FIG. 15 are operated at high speed by using interleave will be described with reference to a timing chart. Here, each memory forming the interleave is called a bank, and the number of interleaves is 8
In this case, each memory is numbered like banks # 1- # 8.

From the above, when the capacity of the AFM is increased by using a DRAM, a failure analysis memory with a large number of interleaves is created, which increases the number of memories used for the failure analysis memory. It gets bigger.

It is an object of the present invention to operate a semiconductor memory test device for operating a DRAM in a first page or a high page when the DRAM is used in a memory portion of a failure analysis memory.

[0010]

A semiconductor memory test apparatus according to the present invention uses a DRAM as a memory section and has address conversion means for converting a random address from a pattern generator into a serial address.

According to an embodiment of the present invention, the address conversion means writes the serial address by a serial address generating pointer for generating a serial address, an address from the pattern generator, and a write signal, and the pattern is written. It includes a conversion memory from which the serial address is read by an address signal and a read signal from the generator.

Further, the semiconductor memory testing device of the present invention is
A DRAM as a memory unit, a FIFO memory provided in each bank for temporarily holding fail data and its address stored in the DRAM, and a row address provided in each bank and read from the FIFO memory And a multiplexer for switching and outputting the column address, an address conversion unit for converting a random address from the pattern generator into a serial address, and a serial address output from the address conversion unit is divided into a row address and a column address, An address match detection that outputs a page flag signal indicating a page operation when the row address output from the address selection section and the row address output from the address selection section are input and the row addresses in the previous cycle and this cycle match Section and fail cycle Buffer counter that returns to 0 when it counts up to the maximum value, a bank counter that counts up when the buffer counter counts up to the maximum value, and the FIFO of the corresponding bank by decoding the count value of the bank counter. In memory,
A fail storage signal generator that outputs a fail storage signal that is a write signal for fail data, and a bank flag that is provided in each bank and that receives the page flag signal and the fail storage signal.
It also has a memory control unit for outputting various timing signals to refresh the DRAM and store fail data by read-modify-write in the DRAM.

According to an embodiment of the present invention, the memory control unit includes a refresh timer for generating a refresh request signal, the fail storage signal, and the D
Input the 1-address storage signal that is output each time the storage of the fail data to the RAM is completed. If the refresh operation flag is off and the count value of the fail-storage signal and the count value of the 1-address storage signal do not match, store the fail data. When the operation flag is turned on and a fail store trigger signal for outputting a fail store trigger signal for activating the storage of the fail data stored in the FIFO memory in the DRAM and a refresh request signal are output, the fail storage operation is performed. When the flag is off, the refresh operation flag is turned on, a refresh trigger that outputs a refresh start signal, a read-modify-write circuit that performs a read-modify-write operation for storing fail data in the DRAM, and a DRAM Refresh operation, The timing generation memory in which the timing data for storing the fail data in the DRAM is stored in advance, the program counter generating the address pointer of the timing generation memory, and the increment, decrement, and hold of the program counter. When the sequence memory in which the sequence data to be stored is stored and the address pointer is generated by the program counter, and the fail storage trigger signal from the fail storage trigger or the refresh start signal from the refresh trigger is input, the sequence memory outputs the sequence data. And a sequence control unit for operating the program counter according to the sequence data.

According to an embodiment of the present invention, the fail store trigger counts the fail store signal F.
An IFO storage counter, a DRAM storage counter that counts the 1-address storage signal, a counter comparator that compares the value of the FIFO storage counter with the value of the DRAM storage counter, and the values of both counters do not match, and the DRAM When fail data storage operation is not performed, and the values of both counters do not match,
Further, it has a circuit for generating and outputting the fail storage trigger signal when the page operation or the read modify write operation, which is the operation of storing fail data in the DRAM, is completed.

The present invention relates to the DRA used in the memory section.
Even if a random test address pattern is used for M, the page operation is performed at high speed to reduce the number of interleaves.

The test address pattern of the memory under test is
As shown in FIG. 11, a serial access pattern for serial access, a pattern for alternately accessing an address that is incremented by +1 from the minimum value and an address that is decremented by -1 from the maximum value, and a diagonal access pattern of a memory matrix. Etc. The present invention converts the test address pattern other than the serial access pattern into a serial address pattern as shown in FIG. 11 to page the DRAM of the memory section.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a failure analysis memory of a semiconductor memory testing device according to an embodiment of the present invention.

The failure analysis memory comprises an address conversion unit 1, an address selection unit 2, a fail storage signal generation unit 3, a FIFO memory 4, a memory control unit 5, a multiplexer 6 and a DRAM (memory unit) 7. here,
The FIFO memory 4, the memory control unit 5, the multiplexer 6 and the DRAM 7 are provided for each bank.

The address conversion unit 1 converts a random address from the pattern generator into a serial address. As shown in FIG. 2, the pattern generator generates random addresses # 0, # 3, # 2, #. 1, # 5, # 7, #
When 4 and # 6 are sequentially output, this address is given to the conversion memory 11 and serial addresses # 0, # 1 and
# 2, # 3, # 4, # 5, # 6 and # 7 are sequentially output.

When the conversion memory 11 is used, as shown in FIG. 3, the position of the address for storing the fail data changes depending on whether the address conversion is performed in the conversion memory 11 or not. The pointer in the failure analysis memory is used when analyzing the fail data in the failure analysis memory (mainly in the read operation of the failure analysis memory), but if it is used as it is, it will be different when the address conversion is applied as shown in FIG. If not, the fail information to read will be different. Since the pointer value in the failure analysis memory and the address value (not converted) from the pattern generator correspond to each other 1: 1 (if it does not correspond, fail information at the same address as the memory under test can be read out). Fail information that is not converted is correct fail information. Therefore, when the address conversion is performed by the conversion memory 11, the position of the address of the failure analysis memory changes, and the fail information at the correct position of the address cannot be read. This drawback is solved as follows. As shown in FIG. 5, when the address is converted by the conversion memory, the output of the pointer that generates the address when reading the fail information in the failure analysis memory is also converted to the value of the pointer through the conversion memory 11. Read the fail information. As a result, the same fail information can be read with or without address conversion. As a result, normal fail information can be read even when fail data is stored in the conversion memory 11 after address conversion.

The address selection unit 2 outputs the row address and column address of the DRAM 7 using the address from the pattern generator, as described in [Prior Art].

The FIFO memory 4 is a memory for temporarily holding the address and fail data because the DRAM 7 cannot store data during the refresh operation (operation for holding data).

As shown in FIG. 6, the fail storage signal generator 3 includes an address coincidence detector 21 and a buffer counter 2.
2, a bank counter 23 and a decoder 24. The address match detection unit 21 performs match detection of the row address output from the address selection unit 2 in the previous cycle and this cycle, and outputs a page flag signal when the address of the previous cycle and the address of this cycle match. The buffer counter 22 has a count value having the same depth as the FIFO memory 4, counts up every fail cycle, and returns to "0" when the count reaches the maximum value. When the buffer counter 22 counts up to the maximum value, the bank counter 23 counts as one FIFO memory 4
Counts up as if it was full. The decoder 24 decodes the count value of the bank counter 23 and generates a fail storage signal in the bank designated by the count value of the counter 23.

The memory control unit 5 controls the DRAM 7. As shown in FIG. 7, a fail storage trigger 31, a refresh trigger 32, an oscillator 33, a refresh timer 34, a sequence control unit 35, a program counter 36, and a sequence memory 37. The timing generation memory 38, the OR gate 39, the flip-flop 40, the three-state buffer 41, and the buffer 42.

As shown in FIG. 8A, the fail storage trigger 31 includes a FIFO storage memory 51, a DRAM storage counter 52, a counter comparator 53, a synchronizing flip-flop 54, flip-flops 55 and 56, and an AND gate 57. , 58 and an OR gate 59. FI
The FO storage counter 51 counts the fail storage signal generated from the fail storage signal generator 3, and the DRAM storage counter 32 outputs 1 from the sequence memory 37.
Count the address storage signal. Counter comparator 33
Outputs a mismatch signal when the value of the FIFO storage counter 31 and the value of the DRAM storage counter 32 do not match. Then, as shown in FIG. 8B, the flip-flops 55 and 56 and the AND gate 57 generate the leading edge differential signal of the mismatch signal, and the fail storage operation to the DRAM 7 is started via the OR gate 59 as a fail storage trigger. The FIFO storage counter 51 operates with the reference clock (system operation clock) output from the timing generator, the DRAM storage counter 52 operates with the clock from the oscillator in the failure analysis memory, and the mismatch detection circuit 53 operates with the asynchronous circuit. Therefore, the synchronizing flip-flop 54 is inserted between the counter comparator 53 and the flip-flop 54 in order to match the clock from the oscillator. When the fail data storing operation for one address to the DRAM 7 is completed and the one address storing signal is inputted to the DRAM storing counter 52, the DRAM storing counter 52
Is counted up and the coincidence signal is output from the counter comparator 53, the operation of storing the fail data in the DRAM 7 ends. If the mismatch signal is output even when the DRAM storage counter 52 is counted up, the storage operation end signal (output when the page operation or the read modify write operation is completed) is output by the AND gate 58 to the next fail. It is output as a storage trigger signal, and the fail storage operation to the DRAM 7 is activated.

The refresh trigger 32 activates a refresh operation in response to a refresh request signal from the refresh timer 34. Each trigger 31, 32 sets the fail storage operation flag and the refresh operation flag to the other trigger 3 when the fail storage operation or the refresh operation is being performed.
1 or 32, one of the operations is placed in a waiting state so that the fail storing operation and the refreshing operation do not conflict with each other, one of the flags is dropped by the operation end signal from the sequence memory 37, and the operation in the waiting state is performed. Is started. The refresh timer 34 measures time with the clock from the oscillator 33, and refresh time for one row address (refresh time of DRAM 7 ÷ DRAM 7
Refresh cycle), a refresh request signal is output to the refresh trigger 32. Where DR
The AM7 refresh time is the time during which data can be retained without refreshing the DRAM 7, and data will be lost if the refreshing operation is not performed within this time. The refresh cycle is the number of times of refreshing that must be performed within the refresh time, and depends on the number of row addresses of the DRAM 7 to be used. I will end up.

The sequence controller 35, the program counter 36, the sequence memory 37, and the timing generation memory 38 perform timing generation for controlling the DRAM 7. When the activation signal from the fail storage trigger 31 or the refresh trigger 32 is input to the sequence control unit 35, the sequence control unit 35 starts the operation of the program counter 36 and generates the address pointers of the sequence memory 37 and the timing generation memory 38. . The output signal from the sequence memory 37 is input to the sequence control unit 35, and the program counter 36 is incremented by the data in the sequence memory 37.
Load and hold. The timing generation memory 38 stores timing data for performing the refresh operation and the fail storage operation in advance, and as shown in FIG. 9 according to a sequence (address pointer generated from the program counter 36) controlled by the data in the sequence memory 37. To generate timing. And DR
AM7 is refresh operation when refreshing, FI
At the time of fail storage from the FO memory 4 to the DRAM 7, a read-modify-write operation is performed. After the fail storage operation is completed, a storage operation end signal is output to the FIFO memory 4 to output the next fail data from the FIFO memory 4. FIG. 9 shows timing data and waveforms generated during the fail storage operation (read modify write operation). The program counter 36 shows an example when the increment operation is simply performed. In addition, the page flag signal is "H"
When the sequence data is input to the sequence controller 35, timing data for page operation is output from the timing generation memory 38, and the DRAM 7 performs page operation. During the page operation, every time one fail address (column address) worth of fail data is stored in the DRAM 7, a one address storage signal is output and the FIFO memory 4 outputs the fail data. Even if the page flag signal is “H” and is input to the sequence control unit 35, the fail storage trigger 31
Since the page operation cannot be performed at the beginning of the storage operation started from (see FIG. 14), the sequence control unit 35 ignores the page flag signal.

The OR gate 39, the flip-flop 40, the three-state buffer 41, and the buffer 42 shown in FIG. 7 are circuits for performing a read-modify-write operation.
First, the three-state buffer 41 is disabled by the input / output control signal IOCNT.
Read the fail data from the buffer 42, and the OR gate 39 through the buffer 42 and the OR with the fail data from the logical comparator and outputs the latch signal DLATC to the flip-flop 40.
Latch with H. Next, the three-state buffer 41 is enabled and the data latched by the flip-flop 40 is written to the DRAM 7. The row / column address selection signal RCASEL is a switching signal for the multiplexer 6, and the multiplexer 6 has RCASEL set to “0”.
, A row address is selected, and when RCASEL is “1”, a column address is selected and output to the DRAM 7.

When the address conversion unit 1 can generate a serial address in the failure analysis memory, the row address does not change randomly, so that the fail store signal generation unit 3 continues to output the page flag signal, and the memory control unit 5 causes the DRAM 7 to operate. Fail storage is performed by page operation. In this way, the page operation can be performed by converting the random address into the serial address.

FIG. 10 is a circuit diagram of the address conversion unit 1 which generates the conversion data by hardware. The address conversion unit 1 assigns a random address from the pattern generator to # 0,
The serial address is converted into serial addresses such as # 1, # 2, ..., As shown in FIG. 10, it is composed of a conversion memory 11, a serial address generation pointer 12, an address multiplexer 13, and a write data multiplexer 14. . The serial address generation pointer 12 is a MUT (Memory Under) from the pattern generator.
Write signal of the conversion memory 11, for example, # 0, # 1, # 2, ..., # 7 is sequentially generated by the Test signal. The write data multiplexer 14 selects the write data sent from the controller 15 that controls the operation of the semiconductor memory test apparatus or the write data output from the serial address generation pointer 12. The conversion memory 11 receives a MUT signal indicating a write from the pattern generator and address signals # 7, # 1, # 0, # 5,
When # 2, # 6, # 3, and # 4 are sequentially output, the data # sequentially output from the write data multiplexer 14
0, # 1, # 2, # 3, # 4, # 5, # 6, # 7 are assigned addresses # 7, # 1, # 0, # 5, # 2, # 6, # respectively.
3 and # 4. Therefore, the conversion memory 11 performs a read operation by the MUT signal from the pattern generator, and the address signals # 7, # 1, # 0, # 5, # 2, and #.
When 6, # 3, and # 4 are sequentially input to the conversion memory, the data # 0, # 1, # 2, # 3, # 4, and # from the conversion memory 11 are input.
5, # 6 and # 7 are sequentially output, which means that the random address from the pattern generator is converted into a serial address. The address multiplexer 13 is for selecting an unconverted address (random address) from the pattern generator or a converted address (serial address) output from the conversion memory 11, and selects an unconverted address during the serial access pattern test. .

These series of operations are written in the instruction memory for controlling the pattern generator to generate the test address pattern and the serial address generating pointer 1.
2 increment, serial address storage, address from the address generator in the pattern generator, MUT signal from the MUT signal generator (control signal of memory under test /
RAS, / CAS, / WE, / OE, etc.) and the like.

As described above, the serial address is generated by the address conversion using the conversion memory 11, and the FIF is generated.
The address and page flag of the same row address are stored in the O memory 4. This allows the FIFO memory 4
The operation of storing the fail data from the DRAM to the DRAM 7 is performed by the page operation. Therefore, the fail data can be stored in the DRAM 7 at high speed, so that the number of interleaves is reduced and the number of memories used for the failure analysis memory is also reduced. Further, the converted data can be easily generated.

[0034]

As described above, according to the present invention, since the conversion data is used to generate the serial address, the operation of storing fail data in the DRAM becomes faster, so that the number of interleaves is reduced and the failure analysis is performed. This has the effect of reducing the number of memories used for the memory.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a failure analysis memory in a semiconductor memory test device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of address conversion in an address conversion unit 1.

FIG. 3 is a diagram showing that the position of an address for storing fail data is changed when address conversion is performed in a conversion memory and when address conversion is not performed.

FIG. 4 is a diagram showing that read data from a failure analysis memory is different when address translation is applied and when it is not applied.

FIG. 5 is a diagram showing that the same fail information can be read with or without address conversion for the pointer of the failure analysis memory.

FIG. 6 is a configuration diagram of a fail storage signal generator 3.

FIG. 7 is a configuration diagram of a memory control unit 5.

FIG. 8 is a configuration diagram of a fail storage trigger 31 ((1) in the same figure)
FIG. 9 is a timing diagram for generating a fail store trigger signal ((2) in the same figure).

FIG. 9 is a diagram showing an example of data in the timing generation memory 38 and timing generated thereby.

10 is a circuit diagram of the address conversion unit 1. FIG.

FIG. 11 is an explanatory diagram of the present invention.

FIG. 12 is a configuration diagram of a conventional example of a semiconductor memory test device.

FIG. 13 is a configuration diagram of a failure analysis memory 63.

FIG. 14 is a diagram showing a timing example of a read modify write operation at the time of random access and serial access.

FIG. 15 is a diagram showing an interleaving method.

[Explanation of symbols]

 1 Address Converter 2 Address Selector 3 Fail Storage Signal Generator 4 FIFO Memory 5 Memory Controller 6 Multiplexer 7 DRAM 11 Conversion Memory 12 Serial Address Generation Pointer 13 Address Multiplexer 14 Write Data Multiplexer 15 Controller 21 Address Match Detector 22 Buffer Counter 23 Bank Counter 24 Decoder 31 Fail Storage Trigger 32 Refresh Trigger 33 Oscillator 34 Refresh Timer 35 Sequence Controller 36 Program Counter 37 Sequence Memory 38 Timing Generation Memory 39 OR Gate 40 Flip-Flop 41 Three-State Buffer 42 Buffer 51 FIFO Storage Counter 52 DRAM Storage Counter 53 counter comparator 54 synchronization Use flip-flops 55 and 56 flip-flops 57, 58 AND gate 59 OR gate 61 timing generator 62 pattern generator 63 failure analysis memory 64 the waveform shaper 65 logic comparator 66 MUT 71 address selection unit 72 memory control unit 73 memory unit

Claims (5)

[Claims] 1. A semiconductor memory test apparatus having a memory section having an address space equivalent to that of a memory under test and storing fail data of the memory under test, wherein a DRAM is used as the memory section, and a pattern generator is used. 6. A semiconductor memory test apparatus having an address conversion means for converting a random address of the above into a serial address. 2. The address conversion means writes a serial address according to a serial address generation pointer for generating a serial address, an address from the pattern generator, and a write signal, and an address signal from the pattern generator, The semiconductor memory testing device according to claim 1, further comprising a conversion memory in which the serial address is read by a read signal. 3. A semiconductor memory test apparatus having a memory section having an address space equivalent to that of a memory under test and storing fail data of the memory under test, wherein the DRAM as the memory section and each bank are provided. , A FIFO memory for temporarily holding fail data and its address stored in the DRAM, a multiplexer provided in each bank for switching and outputting a row address and a column address read from the FIFO memory, and a pattern An address conversion unit that converts a random address from the generator into a serial address; an address selection unit that divides the serial address output from the address conversion unit into row addresses and column addresses and outputs the row address and column address to the FIFO memory; Row address output from the address selector Is input and the row address in the previous cycle matches the row address in the present cycle, the address match detection unit that outputs a page flag signal indicating the page operation, and the fail cycle are counted. When the count reaches the maximum value, the buffer counter returns to 0. When the buffer counter counts up to the maximum value, the bank counter that counts up and the count value of the bank counter are decoded, and a fail storage signal that is a fail data write signal is written to the FIFO memory of the corresponding bank. A fail storage signal generator for outputting and a bank flag provided in each bank, which inputs the page flag signal and the fail storage signal, outputs a switching signal to the multiplexer, outputs various timing signals to the DRAM, and refreshes the DRAM. Reload to the DRAM A semiconductor memory test apparatus having a memory control unit for performing a fail data storage operation by a modified write. 4. The memory control unit inputs a refresh timer for generating a refresh request signal, the fail storage signal, and a 1-address storage signal output each time storage of fail data in the DRAM is completed. When the refresh operation flag is off and the count value of the fail storage signal and the count value of the one address storage signal do not match, the fail storage operation flag is turned on and the DRAM of the fail data stored in the FIFO memory concerned. And a fail store trigger that outputs a fail store trigger signal for activating storage, and when the refresh request signal is output, when the fail store operation flag is off, the refresh operation flag is turned on and a refresh start signal is output. Refresh trigger and the DR A read-modify-write circuit that performs a read-modify-write operation for storing fail data in M, and timing data for performing a refresh operation for the DRAM and an operation for storing the fail data in the DRAM are stored in advance. A timing generation memory, a program counter for generating an address pointer of the timing generation memory, a sequence memory for storing sequence data for incrementing, decrementing, and holding the program counter, and an address pointer generated by the program counter, When a fail store trigger signal is input from the fail store trigger or a refresh start signal is input from the refresh trigger, the sequence data output from the sequence memory is input. Having a sequence control unit for operating the program counter in accordance with data, a semiconductor memory testing device of claim 3, wherein. 5. The fail storage trigger includes a FIFO storage counter for counting the fail storage signal, a DRAM storage counter for counting the one-address storage signal, a value of the FIFO storage counter and a value of the DRAM storage counter. The counter comparator for comparison and the values of both counters do not match, and the DRAM
When the fail data storage operation to the DRAM is not performed, the values of the counters do not match, and the DRAM
5. The semiconductor memory testing device according to claim 4, further comprising a circuit that generates and outputs the fail storage trigger signal when a page operation or a read-modify-write operation, which is a fail data storage operation to the memory, is completed.