JPH09312380A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the surface step difference between gate electrodes and semiconductor substrate and inhibit impurity diffusion into the gate electrodes by depositing side walls to the side sections of the gate electrodes of FETs for memory cells and also side walls to the gate electrodes of FETs for peripheral circuits and the side sections of a TEOS film of an upper layer. SOLUTION: A resist pattern is formed on other regions that n-type FET- forming regions for forming peripheral circuits. Impurity ions are implanted into the FET-forming regions to form n-type low-concn. impurity regions in source/drain regions. TEOS film laminated on the whole surface of a semiconductor substrate 1 is anisotropically etched to form gate electrodes 9 of peripheral circuit-forming FETs 6 and side walls 11 deposited to side sections of a TEOS film 10 laminated on its upper layer with the side walls 11 formed also on the side sections of a TEOS film 10a laminated on n-type FETs forming regions for forming memory cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a complementary metal oxide semiconductor (CMOS) having memory cells.
r) A semiconductor device having a structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 31 shows a typical conventional DRAM (dy
FET (fiel) that composes a namic random access memory
3 is a diagram showing a cross-sectional structure of a d effect transistor), in which 101 is a P-type semiconductor substrate, and 102 is a P formed from the surface of the semiconductor substrate 101 to a predetermined depth.
Well 103 is an N well, and P well 10
An N-type FET 104 serving as an access transistor of a memory cell and an N-type FET 105 of a peripheral circuit are formed on the second well 2, and a P-type FET 106 of the peripheral circuit is formed on the N well 103.
Are formed. The FETs 104, 105, 106 formed on these same semiconductor substrates are electrically isolated by the element isolation regions 107.

Further, 108 is a gate insulating film formed on one main surface of the semiconductor substrate 101, and 109 is the gate insulating film 1.
Gate electrode 110 formed on 08, and gate electrode 1
TEOS (tetraethyl orthosilicat) laminated on 09
The film e) and 111 are sidewalls made of an insulating film formed by adhering to the side cross sections of the gate electrode 109 and the TEOS film 110.

Reference numeral 112 denotes an N-type source / drain region formed on the surface of the semiconductor substrate 101 except under the gate electrode 109 of the N-type FET 104 for memory cell formation and the N-type FET 105 for peripheral circuit formation. A low-concentration impurity region containing an impurity, 113 is a high-concentration impurity region containing an N-type impurity formed in a source / drain region not including a lower portion of the sidewall 111 of the N-type FET 105, 11
Reference numeral 4 denotes a source / drain region of the LDD structure composed of the low-concentration impurity region 112 and the high-concentration impurity region 113 of the peripheral circuit forming N-type FET 105.

Reference numeral 115 is a gate electrode 1 of the P-type FET 106.
09 shows a high-concentration impurity region formed on the surface of the semiconductor substrate 101, which will be the source / drain regions of the active region other than the lower part of 09. As shown in the figure, generally in an N-type FET for forming a memory cell, an N-type high concentration impurity region is not formed in the source / drain region for the purpose of suppressing deterioration of refresh characteristics of DRAM.

The gate electrode 109 of the semiconductor device of FIG.
The method of forming the source / drain regions is as follows. First, LOCOS oxidation is performed on the semiconductor substrate 101 to form an element isolation region 107 in a region to be an inactive region, and then a surface of the semiconductor substrate 101 in a region to be an active region is oxidized to form a gate insulating film 108. .

Thereafter, a polysilicon film containing impurity phosphorus, which will serve as the gate electrode 109, is laminated to a predetermined thickness on the entire surface of the semiconductor substrate 101, and then a TEOS film 110 is laminated. After that, a resist pattern having a desired shape is formed by photolithography, and TEOS is used as an etching mask.
After etching the film 110 and removing the resist pattern,
The polysilicon film is etched using the TEOS film 110 as an etching mask to pattern the gate electrode 109 and the TEOS film 110 above the gate electrode 109 into a predetermined shape.

Next, N-type ions are selectively implanted into the formation regions of the N-type FETs 104 and 105 for forming memory cells and peripheral circuits, and the N-type ions are lowered from the surface of the semiconductor substrate 101 to a relatively shallow position. The concentration impurity region 112 is formed. Next, after stacking a TEOS film by the CVD technique, anisotropic oxide film etching is performed to form the gate electrode 109.
A sidewall 111 is selectively formed on the side cross section of the TEOS film 110.

In the conventional manufacturing process of a semiconductor device, when the high-concentration impurity regions 113 and 115 to be the source / drain regions are formed after the gate electrode 109 is formed, the implantation energy is large, so that TEO is formed on the gate electrode 109.
If the S film 110 is not formed, impurities will be implanted into the gate electrode 109 and the channel region below it.
If the threshold of ET fluctuates, or if P-type ions are implanted during the ion implantation for forming the high-concentration impurity region 115 of the P-type FET 106, the gate electrode 10
Since 9 is made of phosphorus-doped polysilicon and is N-type, the gate electrode itself is depleted, which adversely affects the FET characteristics, especially the threshold value. However, as shown in FIG.
The formation of the OS film 110 has an advantage that impurities can be suppressed from being implanted into the gate electrode 109 during the ion implantation.

However, the semiconductor device having the TEOS film 110 has a problem in terms of fine processing. As can be seen from the cross-sectional view of FIG. 31, since the TEOS film 110 is formed in addition to the gate electrode 109,
The size increases in the height direction by the film thickness, and the surface step T also increases accordingly as shown in FIG.

If the surface step T becomes unnecessarily large, particularly in the memory cell portion where the minimum size is used, this leads to the problem that the dimensional controllability of photolithography such as bit lines and storage nodes is deteriorated in the subsequent process. Further, when the method of removing the TEOS film 110 is used in order to reduce the surface step T, the flattening of the interlayer insulating film is indispensable because the TEOS film 110 is etched without a residue, and the TEOS film 110 is averaged. However, there was a problem of increasing costs.

In the memory cell portion where the patterns are dense, the height above the surface of the semiconductor substrate 101 is TEO.
Although averaged on the upper surface of the S film 110,
There is a problem that the absolute step difference with the peripheral circuit portion, which has a sparse pattern, becomes larger than that of the memory cell portion, and the process margin is impaired especially in the process of aluminum wiring.

FIG. 32 is a sectional view of a semiconductor device according to another conventional technique, in which the reference numerals used in the description are the same as or the same as the corresponding reference numerals. And TEO having the structure shown in FIG.
It is the figure which showed the semiconductor device which abbreviate | omitted the S film | membrane 110.

In such a semiconductor device, the gate electrode 1
The surface step T2 of 09 is larger than that of the surface step T of FIG.
Since the thickness is reduced by the film thickness of the OS film 110, it is advantageous for fine processing of the memory cell portion. However, in the peripheral circuit forming FET, impurities may be injected into the gate electrode 109 and the channel region during the impurity injection for forming the high-concentration impurity regions 113 and 115, and the threshold value of the FET may vary. The structure is disadvantageous with respect to the FET characteristics of the peripheral circuit formation region.

Further, since the height of the side wall 111 formed by adhering to the side cross section of the gate electrode 109 is inevitably low, the side wall 111 is changed due to the process variation such as the dry etching time at the time of forming the side wall 111. There is also a problem that the width d fluctuates remarkably and the FET characteristics are made unstable.

Further, the structure is similar to that shown in FIG. 31 which is shown as a structure of a semiconductor device according to a general prior art, and the memory cell forming FET has no side wall on the side cross section of the gate electrode, and the FET on the gate electrode is active. An oxide film is formed on the entire surface of the area, and the FET for peripheral circuit formation has a TE film on the gate electrode.
A structure of a semiconductor device in which a sidewall is formed only on a side cross section of a gate electrode without an OS film is disclosed in Japanese Patent Application Laid-Open No. 5-291.
It is disclosed in Japanese Patent No. 530. Similar to the semiconductor device shown in FIG. 31, such a semiconductor device also has problems such as FET characteristics.

[0017]

As described above, in the structure of the conventional semiconductor device, T is formed on the gate electrode of the FET.
When the EOS film is formed, the surface step of the semiconductor device increases, which makes microfabrication difficult, and when the TEOS film is not formed, there is a problem that the characteristics of the FET are adversely affected.

The present invention has been made in order to solve the above-mentioned problems, and in the FET formed in the memory cell formation region, the surface step between the gate electrode and the semiconductor substrate is reduced to form a peripheral circuit. Regarding the FET having a high concentration impurity region in the source / drain region, FE having stable characteristics without the impurity being implanted and diffused in the gate electrode and the channel region by the source / drain implantation.
To get T.

[0019]

According to the present invention, there is provided a semiconductor device having a first FET for forming a memory cell and a second FET for forming a peripheral circuit formed on one main surface of a semiconductor substrate. A first FET is formed by adhering to at least a first gate electrode formed on at least one main surface of the semiconductor substrate via a first gate insulating film and a side cross section of the first gate electrode. The second FET has a low-concentration impurity region formed in the semiconductor substrate with one sidewall and a channel region below the first gate electrode interposed therebetween.
Is a second gate electrode formed on at least one main surface of the semiconductor substrate via a second gate insulating film, a TEOS film laminated on the second gate electrode, and the second gate electrode. It has a second sidewall formed by adhering to a side cross section of the gate electrode and the TEOS film, and a high-concentration impurity region formed in the semiconductor substrate with a channel region below the second gate electrode sandwiched therebetween. It is a thing.

A semiconductor device having a first FET for forming a memory cell and a second FET for forming a peripheral circuit formed on one main surface of a semiconductor substrate according to the present invention is the first FE described above.
T is formed in the semiconductor substrate at least with a first gate electrode formed on one main surface of the semiconductor substrate with a first gate insulating film interposed between the first gate electrode and a channel region below the first gate electrode. A low concentration impurity region, the first gate electrode, and a first TEOS film stacked on the low concentration impurity region, and the second FET is at least on one main surface of the semiconductor substrate. A second gate electrode formed via a second gate insulating film, a second TEOS film laminated on the second gate electrode, the second gate electrode and the second TEOS. It has a sidewall formed by adhering to a side cross section of the film, and a high-concentration impurity region formed in the semiconductor substrate with a channel region below the second gate electrode interposed therebetween.

In addition to the above structure, in the semiconductor device according to the present invention, in the second FET, which is an N-channel type transistor, in the semiconductor substrate with the channel region below the second gate electrode interposed therebetween. It has a low-concentration impurity region formed in.

Further, in addition to the above structure, in the semiconductor device according to the present invention, the low concentration impurity regions of the first FET and the second FET are different from each other.

A method of manufacturing a semiconductor device according to the present invention is
A first step of forming an element isolation region on a main surface of a semiconductor substrate to form a plurality of electrically isolated active regions, a first FET and a peripheral circuit constituting a memory cell on the active region. A second step of laminating a polysilicon film on each of the second FET forming regions via a gate insulating film, and the second step of forming the second FET forming region on the polysilicon film. The shape of the FET gate electrode TE
Third step of selectively forming OS film, first FE
The first FE is formed on the polysilicon film in the T formation region.
Fourth step of selectively forming a resist pattern in the shape of a gate electrode of T, anisotropic etching is performed on the polysilicon film using the TEOS film and the resist pattern as an etching mask to form the polysilicon film. A fifth step of patterning the gate electrodes of the first and second FETs to obtain a first gate electrode and a second gate electrode made of the polysilicon film, and removing the resist pattern, at least the above A sixth step of forming a sidewall made of an insulating material on a side cross section of the second gate electrode, and in the semiconductor substrate with a channel region below the first gate electrode in a formation region of the first FET sandwiched therebetween. A seventh step of forming a low-concentration impurity region, which is located above the second FET formation region with the channel region below the second gate electrode interposed therebetween. It is intended to include an eighth step of forming a high-concentration impurity regions in the semiconductor substrate.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. Embodiment 1 of the present invention will be described. 1 is a sectional view showing a first embodiment according to the present invention, in which 1 is a P-type semiconductor substrate, 2 is a P well formed from the surface of the semiconductor substrate 1 to a predetermined depth, and 3 is an N well. And an N-type FET 4 serving as a memory cell access transistor on the P-well 2,
An N-type FET 5 forming a peripheral circuit is formed, and a P-type FET 6 forming a peripheral circuit is formed on the N well 3. These FETs 4, 5, 6 are active regions 4a, 5a, electrically isolated by an element isolation region 7, respectively.
It is in a state of being formed on 6a.

Further, 8 is a gate insulating film formed on one main surface of the semiconductor substrate 1, 9 is a gate electrode formed on the gate insulating film 8, and 10 is a TE layered on the gate electrode 9.
The OS film 11 is formed by adhering to the side cross sections of the gate electrode 9 and the TEOS film 10, and shows a sidewall made of an insulating film.

Further, 12 is an N-type impurity which becomes a source / drain region, which is formed on the surface of the semiconductor substrate 1 except under the gate electrode 9 of the N-type FET 4 and the N-type FET 5 for forming the peripheral circuit which constitute the memory cell. Is a low concentration impurity region containing N, 13 is a high concentration impurity region containing N type impurities formed in the source / drain region not including the lower portion of the sidewall 11 of the N type FET 5, and 14 is an N type FE for peripheral circuit formation.
The source / drain region of the LDD structure composed of the low concentration impurity region 12 and the high concentration impurity region 13 of T5 is shown.

Further, the N-type FET 4 for forming the memory cell and the N-type FET 6 for forming the peripheral circuit respectively have sources / sources.
It is also possible to change the ion species of impurities to be implanted into the drain region, the implantation energy, and the implantation amount to form the FETs in the optimum state. Reference numeral 15 denotes a high-concentration impurity region formed on the surface of the semiconductor substrate 1 which becomes the source / drain region of the active region other than the portion below the gate electrode 9 of the P-type FET 6.

Reference numeral 16 denotes a side wall made of an insulating film formed by adhering to the side cross section of the gate electrode 9 of the memory cell forming FET 4. In the semiconductor device thus formed, the N-type FET 4 for forming the memory cell is formed.
Does not have a TEOS film formed on the gate electrode 9,
The surface step X of the memory cell forming FET 4 corresponds to the film thickness of the gate electrode 9.

Further, in the memory cell forming FET 4, only the low concentration impurity region 12 is formed in the source / drain region from the one main surface of the semiconductor substrate 1 to a relatively shallow position, and the high concentration impurity region is not formed. Even if the impurity ions are simultaneously implanted into the gate electrode 9, they are not implanted deep enough to reach the channel region, and the impurities contained in the gate electrode 9 and the impurities implanted into the source / drain regions are not The same conductivity type does not deplete the gate electrode 9 itself.

Further, N-type and P-type FEs for forming peripheral circuits
Since T5 and T6 need to form a high concentration impurity region from the surface of the source / drain region to a relatively deep position, the TEOS film 10 has a structure formed on the gate electrode 9, and the gate electrode 9 and the channel region are formed. Impurities are not implanted at the same time as the source / drain implantation.

Particularly, in the P-type FET 6 for forming the peripheral circuit, the gate electrode is the gate electrode 9 of the N-type FETs 4 and 5.
On the gate electrode 9 even if it is made of the same material as, that is, phosphorus-doped polysilicon (including N-type impurities).
Since the OS film 10 is formed, the gate electrode 9
It is possible to suppress the depletion due to the implantation of P-type impurities due to the source / drain implantation into the inside, and the FET characteristics are not deteriorated.

Next, a method of manufacturing this semiconductor device will be described. First, as shown in FIG. 2, a P-type semiconductor substrate 1
A P well 2 and an N well 3 are formed on one main surface, and then a region to be an inactive region is selectively LOCOS-oxidized to form an element isolation region 7. The active region on the surface of the semiconductor substrate 1 by the element isolation region 7 is, for example, an active region 4a in which an N-type FET 4 serving as an access transistor of a memory cell such as a DRAM is formed, a peripheral circuit forming N-type FET.
5, the P-type FET 6 is formed into the active regions 5a and 6a.

Thereafter, as shown in FIG. 3, the semiconductor substrate 1
A gate insulating film 8 having a thickness of about 100 to 120 Å is formed on the surface of a region which will be an active region by thermal oxidation. Further, on the element isolation region 7 and the gate insulating film 8, the FET 4,
The polysilicon film 9a containing phosphorus, which will be the common gate electrode 9 of 5 and 6, is 1000 to 2000 Å by using the CVD technique.
And then the TEOS film 10 is laminated so as to have a thickness of about 1000 Å.

Next, as shown in FIG. 4, a resist pattern 17 in the shape of the respective gate electrodes 9 is formed on the active regions 5a and 6a of the peripheral circuit forming N-type FET 5 and P-type FET 6, respectively.
Are formed by photolithography, and at the same time F for forming memory cells
A resist pattern 17a covering the formation area of ET4 is formed. Thereafter, as shown in FIG. 5, dry etching is performed on the oxide film to form the TEOS film 1 located under the resist pattern 17 and on the active region 4a of the FET 4 for forming the memory cell.
Other TEOS films are selectively removed, leaving 0, and the resist patterns 17 and 17a are removed.

Next, a resist pattern (not shown) is formed so as to cover the formation regions of the peripheral circuit forming FETs 5 and 6.
The TE on the formation region of the memory cell formation FET 4 is selectively
The OS film 10 is selectively removed. Thereafter, as shown in FIG. 6, a resist pattern 18 in the shape of the gate electrode 9 is formed on the active region 4a of the memory cell forming FET 4 by photolithography, and at the same time, the formation region of the peripheral circuit forming FETs 5 and 6 is covered. A resist pattern 18a is formed.

Then, as shown in FIG. 7, the polysilicon film 9a is etched using the resist patterns 18 and 18a as etching masks to form a memory cell forming FET.
4 gate electrodes 9 are formed, and resist patterns 18 and 1 are formed.
8a is removed.

Next, as shown in FIG. 8, a resist mask 19 is formed on the formation region of the P-type FET 6, and the N-type FET is formed.
N-type impurities, that is, impurity ions such as phosphorus and arsenic are implanted into the formation regions 4 and 5 to form the N-type low-concentration impurity regions 12 in regions other than the lower part of the gate electrode 9 in the active regions 4a and 5a. Then, the resist mask 19 is removed. In this ion implantation process, the TEOS film is not stacked on the gate electrode 9 on the memory cell active region 4a, but the ion implantation conditions are low energy and low concentration (about 100 minutes of the high concentration impurity regions 13 and 15). Since it is about 1), it does not adversely affect the FET characteristics.

Thereafter, as shown in FIG. 9, the semiconductor substrate 1
A TEOS film 11a is laminated on the entire surface of the substrate using the CVD technique. Next, as shown in FIG. 10, the TEOS film 11a is etched by anisotropic etching to form the sidewall 11 having the sidewall width d on the sidewalls of the gate electrode 9 and the TEOS film 10. At the same time, a sidewall 1 is formed on the side section of the gate electrode 9 of the memory cell forming FET 4.
6 are formed.

After that, as shown in FIG. 11, the active region 5a of the N-type FET 5 for forming the peripheral circuit is exposed, the other region is covered with the resist mask 20, and arsenic is ion-implanted to form the active region 5a. A high-concentration impurity region 13 is formed in the semiconductor substrate 1 with the channel region below the gate electrode 9 interposed therebetween, and the high-concentration impurity region 12 and the low-concentration impurity region 12 form an LDD structure source / source.
A drain region 14 is formed. After that, the resist mask 20 is removed.

Next, as shown in FIG. 12, a resist mask 21 is patterned so as to cover a region other than the formation region of the peripheral circuit forming P-type FET 6, and then boron is implanted into the formation region of the FET 6. A P-type high concentration impurity region 15 is formed on the surface of the exposed region of the active region 6a.
Then, by removing the resist mask 21, it becomes possible to obtain a semiconductor device as shown in FIG.

In the semiconductor device thus formed, the high integration is required, and accordingly, the miniaturization in the height direction is required. Therefore, the memory cell forming FET 4 is required.
The surface level difference X reflects only the film thickness of the gate electrode 9, and does not include the thickness of the TEOS film 10 as in the conventional case. Therefore, the surface level difference X can be made extremely small and can be made in the height direction. The structure can be made finer, and a structure suitable for fine processing can be obtained.

Although the TEOS film is not formed on the gate electrode 9, even if impurities are implanted into the gate electrode 9 at the same time when the ions are implanted to form the low concentration impurity region 12, the implantation energy and Since the impurity concentration is low, the impurity does not penetrate through the gate electrode 9 and reach the channel region, and the FET characteristic does not change even if the impurity concentration of the gate electrode 9 is changed.

Also, peripheral circuit forming N-type and P-type F having high-concentration impurity regions 13 and 15 in the source / drain regions are provided.
Regarding ETs 5 and 6, when ion implantation is performed to form the high concentration impurity regions 13 and 15, T is formed on the gate electrode 9.
By stacking the EOS film 10, it is possible to prevent impurities from being injected into the channel region and suppress the fluctuation of the threshold voltage of the FET. Further, since the sidewall 11 is formed on the side cross section of the gate electrode 9 in the state where the TEOS film 10 is laminated, the sidewall width d can be set to a stable value.

Thus, the memory cell forming N-type FET 4, the peripheral circuit forming N-type, which are formed in the same semiconductor device,
It is possible to make the P-type FETs 5 and 6 into FETs each having a suitable structure.

It is also possible to obtain a semiconductor device having a similar structure by a method as shown in the following FIGS. 13 to 15 instead of the manufacturing method shown in FIGS. 4 to 6 above. First, as shown in FIG. 13, peripheral circuit forming N-type and P-type F
A resist pattern 17 in the shape of each gate electrode is formed on the active regions 5a and 6a of the ET by photolithography. After that, as shown in FIG. 14, oxide film dry etching is performed to remove TEO under the resist pattern 17.
The TE film is selectively removed while leaving the S film 10, and the resist pattern 17 is removed.

Next, as shown in FIG. 15, a resist pattern 18 in the shape of the gate electrode 9 is formed by photolithography on the active region 4a of the memory cell forming FET 4. Then, the resist pattern 18 and the T that has already been patterned
The polysilicon film 9a is etched using the EOS film 10 as an etching mask, the gate electrodes 9 of the respective FETs are patterned at the same time, and then the resist pattern 18 is removed to obtain the state shown in FIG. To do.

As described above, the patterning of the gate electrode 9 can be performed simultaneously by using the resist mask 18 and the etching mask of the TEOS film 10 made of different substances. By this step, the number of patterning steps of the gate electrode 9 can be performed. There is an effect that can reduce.

Embodiment 2 Next, a second embodiment will be described. In the first embodiment described above, the sidewall 11 is formed also on the side wall of the gate electrode 9 of the memory cell forming N-type FET 4, but the structure of the second embodiment is as shown in FIG. N type F for memory cell formation
No sidewall is formed on the side wall of the gate electrode 9 of the ET 4, and the TEOS film 10 a is laminated on the N-type FET 4 forming region 4 to have a uniform thickness. Therefore, the surface step X2 of the memory cell forming FET 4 reflects the film thickness of the gate electrode 9. This figure 1
6, the same reference numerals as those already used for the description indicate the same or corresponding portions.

Next, a method of manufacturing the semiconductor device shown in FIG. 16 will be described. First, the same manufacturing method as that of FIGS. 2 to 9 of the first embodiment is carried out, and then, as shown in FIG. 17, a resist mask 22 is formed in a region other than the region where the peripheral circuit forming N-type FET 5 is formed. Then, using this as a mask, arsenic or the like is ion-implanted to form a high-concentration impurity region 13 to be the source / drain region 14 of the N-type FET 5. After that, the resist mask 22 is removed.

Next, as shown in FIG. 18, a resist mask 23 is formed in a region other than the region in which the P-type FET 6 for forming the peripheral circuit is formed, and anisotropic P-type F etching is performed by dry etching.
Sidewalls 11 are formed on the side surfaces of the gate electrode 9 and the TEOS film 10 of ET6. Then, boron or the like is ion-implanted to form the high-concentration impurity regions 15 to be the source / drain regions. Next, by removing the resist mask 23, the semiconductor device shown in FIG. 16 can be formed.

In the usual step of forming the side wall 11, after forming the gate electrode 9, an insulating film is laminated on the entire surface of the FET, and then anisotropic oxide film etching is performed to form only the side cross section of the gate electrode 9. Although the sidewalls are formed while leaving the insulating film, this method causes etching to reach the surface of the active region 4a and gives etching damage, which may deteriorate the refresh characteristics of the DRAM memory cell. It was

However, in the semiconductor device having the structure shown in FIG. 16, in addition to the effect of the first embodiment, N for memory cell formation is formed.
Since the step of forming the sidewall on the side cross section of the gate electrode 9 of the type FET 4 is not included, it is possible to form the N type FET 4 for forming the memory cell having more stable characteristics.

Embodiment 3 Next, a third embodiment of the invention will be described. The semiconductor device formed according to the third embodiment shows a method of obtaining a semiconductor device having a structure similar to that of the semiconductor device of the type shown in the second embodiment.

In the first and second embodiments, even for FETs formed on the same semiconductor substrate, the material used as the etching mask when patterning the gate electrode is the memory cell forming FET 4 and the peripheral circuit forming FETs 5 and 6. It was different. In the method of manufacturing a semiconductor device according to the third embodiment, the gate electrodes of the memory cell forming FET 4 and the peripheral circuit forming FETs 5 and 6 formed on the same semiconductor substrate are patterned using etching masks made of the same material. Here is an example:

First, FIG. 19 shows a sectional view of a semiconductor device formed by the method of manufacturing a semiconductor device of the third embodiment. In the figure, the difference from FIG. 16 showing the second embodiment is that the side wall 11 attached to the cross section of the TEOS film 10a formed on the gate electrode 9 of the N-type FET 4 for forming the memory cell is the element isolation region. 7 is a point formed on 7. Further, in the reference numerals attached to the drawings, the same reference numerals as those already used in the first and second embodiments indicate the same or corresponding portions.

The semiconductor device of FIG. 19 is the same as that of the second embodiment.
Similar to the semiconductor device shown in FIG.
The surface step X2 of ET4, that is, only the film thickness of the gate electrode 9, has a structure capable of effective miniaturization in the height direction. In the N-type and P-type FETs 5 and 6 for forming the peripheral circuit, Since the TEOS film 10 is formed on the gate electrode 9, the structure is capable of suppressing the implantation into the gate electrode 9 during the source / drain implantation.

Next, a method of manufacturing the semiconductor device of FIG. 19 will be described. First, as shown in FIG. 20, as in the first embodiment, the P well 2 and the N well 3 are formed in the semiconductor substrate 1.
And the element isolation region 7 is formed by LOCOS oxidation. One main surface of the semiconductor substrate 1 is divided into a plurality of parts by the element isolation regions, and in FIG. 20, active regions 4a, 5a, 6a are formed in order from the left side. In the active region 4a, N serving as a memory cell access transistor is formed.
A type FET 4 is formed, and an N type FET 5 and a P type FET 6 for forming peripheral circuits are formed on 5a and 6a, respectively.

Thereafter, as shown in FIG. 21, the active region 4
The surfaces of a, 5a, and 6a are oxidized to form a gate insulating film 8 made of a silicon oxide film. Next, a polysilicon film 9a to be the gate electrode 9 is laminated to a predetermined thickness on the entire surface of the semiconductor substrate 1. Further, on the active region 4a, a resist pattern 24a is patterned in the shape of the gate electrode 9 of the N-type FET 4 to be formed here, and at the same time, the N-type FE is formed.
A resist pattern 24 is formed on a region other than the T4 forming region.
b is formed.

Next, as shown in FIG. 22, the polysilicon film 9a is anisotropically etched using the resist patterns 24a and 24b as etching masks to form the gate electrode 9 of the N-type FET for forming a memory cell. Then, the resist patterns 24a and 24b are removed.

After that, as shown in FIG. 23, N-type impurity ions are implanted into the active region 4a of the memory cell forming FET 4 to form the low-concentration impurity regions 12 to be the source / drain regions.

Next, as shown in FIG. 24, the semiconductor substrate 1
A TEOS film 10 is laminated to a predetermined thickness on the entire surface of the substrate, a resist pattern 25a is formed on a region where the memory cell forming FET 4 is formed, and peripheral circuit forming N type FETs 5 and P are formed.
On the formation region of the gate electrode 9 of the type FET 6, resist patterns 25b and 25c having the same dimensions as the design dimensions of the respective gate electrodes 9 are formed.

After that, as shown in FIG. 25, anisotropic etching is performed using the resist patterns 25a, 25b and 25c as etching masks, and the TEOS film 10 and the gate electrodes 9 of the peripheral circuit forming FETs 5 and 6 are designed as designed. After patterning, resist patterns 25a, 25b, 2
Remove 5c. At this stage, N-type F for memory cell formation
The TEOS film 10a remains on the ET4 formation region.

Next, as shown in FIG. 26, a resist pattern 26 is formed on a region other than the region where the peripheral circuit forming N-type FET 5 is formed, and impurity ions are added to the peripheral circuit forming N-type FET 5 forming region. Implantation is performed to form N-type low-concentration impurity regions 12a in the source / drain regions. After that, the resist pattern 26 is removed. Thus, the low-concentration impurity region 12a of the peripheral circuit forming N-type FET 5 and the low-concentration impurity region 12 of the memory cell forming N-type FET 4 are formed.
Can be formed in separate steps so as to have an optimum structure for each FET.

Thereafter, as shown in FIG. 27, a TEOS film 11a having a predetermined thickness is laminated on the entire surface of the semiconductor substrate 1.
Next, as shown in FIG. 28, anisotropic etching is performed on the TEOS film 11a to form the peripheral circuit forming FETs 5 and 6.
Gate electrode 9 and the TEOS film 1 laminated thereon
The sidewall 11 attached to the 0 side section is formed. At this time, the sidewalls 11 are also formed on the side cross section of the TEOS film 10a stacked on the formation region of the memory cell forming N-type FET 4.

Thereafter, as shown in FIG. 29, a resist pattern 27 is formed in a region other than the region where the peripheral circuit forming N-type FET 5 is formed, and the peripheral circuit forming N-type FET 5 is formed.
Impurity ion implantation is performed on the active regions of the above to form N-type high-concentration impurity regions 13. Thus, the source / drain region 14 having the LDD structure including the low-concentration impurity region 12 and the high-concentration impurity region 13 can be formed. Then, the resist pattern 27 is removed.

Next, as shown in FIG. 30, a resist pattern 28 is formed in an area other than the peripheral circuit forming P-type FET 6 forming area, and the peripheral circuit forming P-type FET 6 source / drain area is formed. Impurity ion implantation is performed,
A P-type high concentration impurity region 15 is formed. Then, by removing the resist pattern 28, the semiconductor device shown in FIG. 19 can be obtained.

As described above, the semiconductor device formed by the manufacturing method according to the third embodiment is an FET having the high-concentration impurity regions 13 and 15 in the source / drain regions, like the semiconductor devices according to the first and second embodiments. Since the TEOS film 10 is formed on the gate electrode 9 of, the impurity is not implanted into the gate electrode 9 during the ion implantation for forming the high concentration impurity regions 13 and 15, and , Surface step X2 after formation of the memory cell forming N-type FET 4
Is substantially a state in which only the film thickness of the gate electrode 9 is reflected, so that the surface step X2 is significantly smaller than the surface steps of the other peripheral circuit forming FETs 5 and 6, and the memory cell formation is It can be said that the N-type FET 4 for use has a structure miniaturized in the height direction.

According to this method of manufacturing a semiconductor device, the memory cell forming N-type FET 4 and the peripheral circuit forming N-type FET 4 are formed.
Both the gate electrodes 9 of the type FET 5 and the memory cell forming P-type FET 6 have an etching mask formed of a resist pattern. The processing technique using the resist pattern as the etching mask is a general processing technique that has existed in the past, and by using the etching mask, the semiconductor device can be easily formed.

Further, according to the method of manufacturing the semiconductor device, the N-type FET 4 for forming the memory cell and the N-type FET for forming the peripheral circuit are formed.
Since the low-concentration impurity regions 12 and 12a forming the source / drain regions of the type FET 5 are formed at different stages, there is an effect that the ion implantation conditions can be optimized for each FET.

Further, as in the second embodiment, TEOS is used.
Since the film 10a is formed on the entire surface of the formation region of the memory cell forming N-type FET 4, there is no step other than the patterning of the gate electrode 9 for etching the surface of the active region 4a, and the damage due to etching is extremely small. F
ET4 can be formed, and the refresh characteristic of the DRAM can be brought into a good state.

Other than the manufacturing method shown in the first to third embodiments, finally, as shown in FIGS. 1, 16 and 19, the gate electrode 9 is formed on the gate electrode 9 of the memory cell forming FET 4. The TEOS film having the same size as that of the semiconductor integrated circuit 9 is not formed, and the peripheral circuit forming FETs 5 and 6 on the same semiconductor substrate 1 are formed.
If the TEOS film 10 is formed on the gate electrode 9 and the side wall 11 is formed by adhering to the side cross section of the TEOS film 10, it can be formed by any manufacturing method. Also, the first to third embodiments
It goes without saying that you can expect almost the same effect as.

[0072]

According to the semiconductor device of the present invention,
The FET for forming the memory cell has TEOS on the gate electrode.
The first sidewall is formed only on the side cross section of the gate electrode without forming a film, and the FET for forming the peripheral circuit is attached to the side cross section of the gate electrode and the TEOS film laminated on the upper layer of this gate electrode. By adopting a structure for forming the second sidewall by using the above structure, the surface level difference in the memory cell formation region is reduced, and the ion implantation is performed when forming the high-concentration impurity regions forming the source / drain regions of the peripheral circuit forming FET. Even when the impurity is injected into the channel region and the gate electrode, it is possible to obtain a semiconductor device having stable FET characteristics, and the sidewall width of the peripheral circuit forming FET has little fluctuation. It becomes possible to

In the semiconductor device according to the present invention, a TEOS film having a predetermined thickness is laminated on the active region of the FET for forming the memory cell via the gate electrode, and the FET for forming the peripheral circuit has the gate. By adopting a structure in which a sidewall is formed by adhering to the side cross section of the electrode and the TEOS film laminated on the upper layer of the gate electrode, the surface step in the memory cell formation region is reduced, and the source / source of the FET for forming the peripheral circuit is formed. Impurities can be suppressed from being implanted into the channel region and the gate electrode even during ion implantation when forming the high-concentration impurity region forming the drain region, and a semiconductor device with stable FET characteristics can be obtained.
Further, it becomes possible to provide a structure in which the fluctuation of the sidewall width of the peripheral circuit forming FET is small. Further, since the side wall is not formed by adhering to the side cross section of the gate electrode of the memory cell forming FET, the etching for forming the side wall is not performed, so that the damage to the surface of the active region can be reduced and the DRAM This has the effect of suppressing deterioration of refresh characteristics.

Further, in the semiconductor device according to the present invention, in addition to the effects described above, the N-channel type transistor of the second FET for forming the peripheral circuit has the source / drain structure formed with the channel region sandwiched therebetween. By additionally forming a low-concentration impurity region, an LDD structure can be obtained, and the FET characteristics can be improved.

Further, in the semiconductor device according to the present invention, in addition to the above effects, a memory cell forming FET is provided.
And the low-concentration impurity regions formed in the N-channel type transistor of the peripheral circuit forming FET, respectively, have different structures, and the conditions suitable for the characteristics of the respective FETs can be obtained, and the FET characteristics can be improved. Is possible.

Further, in the method of manufacturing a semiconductor device according to the present invention, the etching mask used when patterning the gate electrodes of the memory cell forming FET and the peripheral circuit forming FET is the resist pattern in the memory cell forming FET and the peripheral portion. The FET for circuit formation is a TEOS film formed to have a predetermined size, and it is possible to perform etching at the same time using etching masks made of different substances. The TEOS film having the same shape as the gate electrode is formed on the gate electrode.
Since the gate electrode can be patterned at the same time regardless of whether the films are stacked or not, there is an effect that a structure suitable for each FET can be obtained without increasing the number of steps.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 9 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 11 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 12 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 13 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 14 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 15 is a diagram showing a manufacturing process according to the first embodiment of the present invention.

FIG. 16 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 17 is a diagram showing a manufacturing process according to the second embodiment of the present invention.

FIG. 18 is a diagram showing a manufacturing process according to the second embodiment of the present invention.

FIG. 19 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 20 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 21 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 22 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 23 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 24 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 25 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 26 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 27 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 28 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 29 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 30 is a diagram showing a manufacturing process according to the third embodiment of the present invention.

FIG. 31 is a sectional view showing a conventional technique.

FIG. 32 is a cross-sectional view showing a conventional technique.

[Explanation of symbols]

1. Semiconductor substrate 2. P-well 3. N well 4. N-type FET 5. N-type FET 6. P-type FET 7. Element isolation region 8. Gate insulating film 9. Gate electrode 9a. Polysilicon film 10, 10a, 11a. TEOS film 11, 16. Side wall 12, 12a. Low concentration impurity region 13, 15. High concentration impurity region 14. Source / drain regions 17, 17a, 18, 18a, 24a, 24b, 25
a, 25b, 25c, 26, 27, 28. Resist pattern 19, 20, 21, 22, 23. Resist mask

Claims (5)

[Claims] 1. A semiconductor device in which a first FET for forming a memory cell and a second FET for forming a peripheral circuit are formed on one main surface of a semiconductor substrate, wherein the first FET is:
A first gate electrode formed on at least one main surface of the semiconductor substrate via a first gate insulating film, and a first sidewall formed by adhering to a side cross section of the first gate electrode. The second FET has a low-concentration impurity region formed in the semiconductor substrate with a channel region below the first gate electrode interposed therebetween, and the second FET has a second gate on at least one main surface of the semiconductor substrate. A second gate electrode formed via an insulating film, a TEOS film laminated on the second gate electrode, the second gate electrode and the TE.
A high concentration impurity region formed in the semiconductor substrate sandwiching a channel region under the second gate electrode, the second sidewall being formed by adhering to a side cross section of the OS film; Semiconductor device. 2. In a semiconductor device in which a first FET for forming a memory cell and a second FET for forming a peripheral circuit are formed on one main surface of a semiconductor substrate, the first FET is:
At least one main surface of the semiconductor substrate, a first gate electrode formed via a first gate insulating film, and a channel region under the first gate electrode sandwiching the low gate electrode formed in the semiconductor substrate. A first T stacked on the high concentration impurity region, the first gate electrode, and the low concentration impurity region;
The second FET has an EOS film, and the second FET has a second gate electrode formed on at least one main surface of the semiconductor substrate via a second gate insulating film and on the second gate electrode. The laminated second TEOS film, the sidewall formed by adhering to the side cross section of the second gate electrode and the second TEOS film, and the channel region below the second gate electrode are sandwiched therebetween. A semiconductor device having a high-concentration impurity region formed in the semiconductor substrate. 3. The second FET includes at least an N-channel transistor, and the N-channel transistor includes a low-concentration impurity region formed in the semiconductor substrate with a channel region below the second gate electrode interposed therebetween. The semiconductor device according to claim 1, further comprising: 4. The semiconductor device according to claim 3, wherein the low concentration impurity regions of the first FET and the second FET have different structures. 5. A first step of forming an element isolation region on one main surface of a semiconductor substrate to form a plurality of electrically isolated active regions, and a first step of forming a memory cell on the active region. Second step of laminating a polysilicon film on the formation region of the second FET forming the FET and the peripheral circuit via the gate insulating film, and on the polysilicon film of the formation region of the second FET A third step of selectively forming a TEOS film in the shape of the gate electrode of the second FET,
Fourth step of selectively forming a resist pattern in the shape of the gate electrode of the first FET on the polysilicon film in the formation region of the first FET, using the TEOS film and the resist pattern as an etching mask Anisotropic etching is performed on the polysilicon film, and the polysilicon film is patterned into the shapes of the gate electrodes of the first and second FETs. Fifth step of obtaining the gate electrode and removing the resist pattern, a sixth step of forming a sidewall made of an insulating material on at least a side cross section of the second gate electrode, a formation region of the first FET The seventh step of forming a low-concentration impurity region in the semiconductor substrate with the channel region under the first gate electrode sandwiched therebetween, The method of manufacturing a semiconductor device, characterized in that across the second channel region under the gate electrode of the formation region of the T including an eighth step of forming a high-concentration impurity regions in the semiconductor substrate.