JPH09312280A - Dry etching - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of etch residue of p-type polycrystal silicon or excessive etching of an underlying layer on the side of an n-type polycrystalline silicon due to the difference in etching rate, in the case where the n-type silicon and p-type polycrystalline silicon of a dual gate structure are worked by the same etching process. SOLUTION: In this method, dry etching is performed such that films formed on a substrate and have different qualities are simultaneously etched in a plasma. In this case, the quantity of negative ions incident on the films to be etched in a direction of reducing the difference in etching rate between the part having the quality of one of the films to be etched (for example, n-type polycrystalline silicon film) and the part having the quality of the other of the films to be etched (for example, p-type polycrystalline silicon film) is controlled by changing the polycrystalline electron temperature.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method in a semiconductor device manufacturing technique.

[0002]

2. Description of the Related Art As ULSI is highly integrated, requirements for fine processing technology are becoming more and more severe.
Even in the dry etching process, a highly accurate processing method has been proposed without exception. In particular, in the step of forming the gate electrode, which has a great influence on the transistor characteristics, a high selection ratio and a high dimensional controllability are required to cope with an extremely thin gate insulating film. In recent years, due to such requirements, a processing method using chlorine radicals in high-density plasma has been established. With this method, it is possible to realize a highly anisotropic processing process using a very high silicon oxide selectivity and a silicon chloride (SiCl) -based sidewall protective film.

In the process of forming CMOS, miniaturization,
As high integration progresses, a so-called dual gate structure is adopted mainly for the purpose of suppressing the short channel effect. This is because the conventional gate structure uses tungsten polycide using n ⁺ -type polycrystalline silicon, whereas the electrode of the P-MOS transistor is formed of p ⁺ -type polycrystalline silicon and the N-MOS transistor is formed. Is formed of n ⁺ type polycrystalline silicon. This makes it possible to form a channel directly under the gate oxide film in both the P-MOS transistor and the N-MOS transistor.

[0004]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Due to the adoption of the rugate structure, p
⁺Type polycrystalline silicon and n⁺Type polycrystalline silicon and impurities
So-called non-doped polycrystalline silicon without doping
It will be in a state in which the console and the console are mixed. This is the impurity dopi
The required parts by ion implantation.
P.⁺Type polycrystal
Boron, boron difluoride in the area where silicon is formed
And so on, n⁺Type polycrystalline silicon is formed
The region to be doped is doped with phosphorus, arsenic or the like. Also above
Dope each impurity only in the vicinity of the transistor
Since most of the objects to be etched are
It becomes non-doped polycrystalline silicon. In addition, in fact,
The gate electrode has a tungsten polycide structure
Therefore, the lower polycrystalline silicon layer has the structure described above.
Often.

A case of processing the polycrystalline silicon films having different kinds and amounts of the doped impurities by etching will be described with reference to FIG.

As shown in FIG. 6A, an n ⁺ type polycrystalline silicon film 113n and a non-doped polycrystalline silicon film 1 are formed on a silicon substrate 111 with a silicon oxide film 112 interposed therebetween.
13, p ⁺ type polycrystalline silicon film 113p is formed. Further, each polycrystalline silicon film 113n, 113, 11
A tungsten silicide film 114 is formed on 3p and masks 115n, 115,
115p is formed.

In the etching of polycrystalline silicon, chlorine atoms (Cl), chlorine radicals (Cl *),
Chloride ion (Cl ^-) and the like are adsorbed. When chlorine ions (Cl ⁺ ) are incident on this surface, energy as lattice vibration is given. Silicon chloride (SiCl _x ) is formed as a reaction product, and it is released from the surface. It has a reaction mechanism called.

Here, the etching rate is determined by
It is considered to be the radical amount (Cl, Cl *, Cl ⁻ ) under the condition that the ion energy of is constant and sufficient. Especially, since Cl has a high electronegativity,
When there is no external energy input due to ion bombardment, electrons are easily attached to Cl ⁻ . Such negative ions are generally more reactive than neutral particles,
Therefore, the higher the concentration of Cl ^{− on} the surface, the higher the etching rate.

The amount of Cl ^{− on} the surface of polycrystalline silicon is n ⁺
In the case of type polycrystalline silicon (conventional case), conduction electrons in the polycrystalline silicon are donated to the adsorbed neutral chlorine atoms, resulting in a relatively large number. Therefore, the more electrons in the polycrystalline silicon, that is, the more impurities for making the n ⁺ type or the higher the degree of activation thereof, the more C
Since the production of l ⁻ increases, the etching rate also increases. On the contrary, in the case of non-doped polycrystalline silicon or p ⁺ type polycrystalline silicon, the contribution of Cl ⁻ is relatively small and the etching rate becomes slow.

Therefore, as shown in (2) of FIG.
When the n ⁺ -type polycrystalline silicon film 113n is etched, the non-doped polycrystalline silicon film 113 or p having a slower etching rate than the n ⁺ -type polycrystalline silicon film 113n is etched.
^{The +} type polycrystalline silicon film 113p is not completely etched.

For this reason, so-called over-etching is carried out in order to remove so-called stringers (residuals of etching) in the non-doped polycrystalline silicon film 113 and the p ⁺ -type polycrystalline silicon film 113p. During this etching, as shown in (3) of FIG. 6, extremely excessive over-etching is performed on the n ⁺ -type polycrystalline silicon film 113n, and the underlying silicon oxide film 11 is formed.
2, the silicon substrate 111 is removed in some cases.
Are scraped off, and a substrate dug 121 occurs. Alternatively, a shape abnormality such as a notch (not shown) may occur.

As described above, the etching rate difference depending on the film quality (p-type, n-type) of the polycrystalline silicon film is C, which is an etching species, depending on the amount of conduction electrons in the polycrystalline silicon film.
It occurs because the amount of negative radicals such as l ⁻ changes. In the case of the dry etching, the negative radical was generated only after the neutral radical received the conduction electron on the substrate surface by the tunnel effect. On the other hand, Cl ⁻ was almost absent because the electron temperature was relatively high in the plasma. Further, since the negative radicals are rejected by the sheath electric field, Cl ⁻ does not substantially enter the film to be etched from the plasma. As described above, a difference in etching rate occurs because the amount of negative radicals is not sufficient. Therefore, the technique of suppressing the etching rate of the n ⁺ -type polycrystalline silicon film and the p ⁺ -type polycrystalline silicon film to be as small as possible will be very important in the future development of ULSI.

[0013]

SUMMARY OF THE INVENTION The present invention is a dry etching method for solving the above-mentioned problems. That is, when simultaneously etching films to be etched having different film qualities formed on a substrate in plasma, an etching rate of a part having one film quality of the film to be etched and an etching rate of a part having the other film quality of the film to be etched Is a dry etching method in which the amount of negative ions incident on the film to be etched is controlled so as to reduce the difference between

In the above dry etching method, the amount of negative ions incident on the film to be etched is controlled so as to reduce the difference in etching rate due to the difference in film quality (p-type, n-type). The rate is controlled by the amount of negative ions. Therefore, the etching rate difference due to the film quality is reduced.

In the dry etching method, a negative bias generated in the plasma is introduced onto the film to be etched by applying a positive bias higher than the potential of the plasma to the substrate.

In the dry etching method in which a positive bias higher than the plasma potential is applied to the substrate as described above, negative ions are introduced onto the film to be etched so as to be attracted to the substrate to which the positive bias is applied. . Therefore, negative radicals are generated regardless of the surface reaction (electron donation) on the substrate and etching is performed.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An example of an embodiment of the dry etching method of the present invention will be described with reference to the timing chart of FIG. The vertical axis of FIG. 1 represents the source pulse electric field strength, the electron density of the etching atmosphere, the electron temperature of the etching atmosphere, the amount of negative ions in the etching atmosphere, and the bias pulse electric field strength in order from the top of the figure, and the horizontal axis represents the timing. Show.

By means of a dry etching apparatus for generating high density plasma, as films to be etched having different film qualities,
For example, in order to simultaneously etch polycrystalline silicon films having different conductivity types such as n-type, non-doped and p-type, the difference in etching rate depending on each film quality should be reduced.
It is necessary to control the amount of negative ions entering the polycrystalline silicon film. As the method, the negative ion concentration in the plasma is controlled by changing the electron temperature in the region where the plasma diffuses (spatial afterglow).
Alternatively, control is performed by changing the electron temperature in a pulse plasma region (temporal afterglow) generated at an electron temperature at which negative ions can exist. Since many negative ions are generated during the spatial or temporal afterglow, the negative ion concentration can be easily controlled by changing the electron temperature in such a region.

Specifically, as shown in FIG. 1, a source electric field introduced into an etching chamber (not shown) of a dry etching apparatus is a pulse electric field (hereinafter referred to as source pulse electric field), and for example, a pulse discharge off time toff. Is supplied by pulse discharge of 0.5 μs or more and 30 μs or less. This pulse discharge is desirably set so that the off time toff of the pulse discharge is 5.0 μs or more and 10 μs or less. In addition, hereinafter, “on” means a state where a pulse is applied, and “off” means a state where no pulse is applied. On the other hand, the off time of the pulse discharge tof
When f is shorter than 0.5 μs, the negative ions are turned on again before they are sufficiently generated, and the etching rate is lowered. The off time toff of the pulse discharge is 30 μm.
If it is longer than s, the electron density is lowered and the etching rate is lowered. The application time ts of the source pulse electric field is appropriately selected within the on / off cycle T.

The bias electric field supplied to the substrate is also a pulse electric field (hereinafter referred to as a bias pulse electric field), and when the source pulse electric field is off, for example, the last 3 μs (3 μs immediately before changing from off to on). The pulsed positive electric field is applied. The application time tb of the bias pulse electric field is appropriately selected within the off time toff of the pulse discharge in the on / off cycle T.

When the pulse electric field is applied as described above, the electron temperature and the electron density decrease and the amount of negative ions increases when the source pulse electric field is off. To be precise, the reaction of the elimination of the electron of the negative ion lowers the electron temperature. The electron temperature here is defined as an average when one cycle of pulse on / off is set. The electron temperature is set so as to be at least 1 eV to 5 eV during one discharge cycle, and preferably 1 discharge
It is set to be at least about 3 eV during the cycle. On the other hand, when the electron temperature is lower than 1 eV,
Since the dissociation itself does not proceed, the etching rate decreases. Further, when the electron temperature is higher than 5 eV, damage due to charge-up becomes large.

Then, by applying the bias pulse electric field to the substrate as a positive bias higher than the potential of plasma, the negative ions generated in the plasma are attracted to the substrate to which the positive bias is applied,
It is introduced on the polycrystalline silicon film. If a positive bias lower than the plasma potential is applied to the substrate, the negative ions generated in the plasma are introduced onto the polycrystalline silicon film because the force of attracting the negative ions to the substrate is not sufficient. It will be difficult.

The timing of applying the bias pulse electric field is preferably such that the negative ion concentration in the plasma becomes highest when the source pulse electric field is off. That is, for example, a positive bias pulse (in the case of pulse discharge) is synchronized with a positive time period of the RF bias cycle or a timing immediately before the source pulse discharge, which has the highest negative ion concentration when the source pulse discharge is off, is turned on. ) Is applied to the substrate, the negative ions are efficiently introduced onto the substrate. Therefore, since negative radicals are generated and etching is performed regardless of the surface reaction (electron donation) on the substrate, the difference in etching rate due to the difference in film quality is reduced.

By applying the electric field as described above, the concentration of negative ions on each polycrystalline silicon film is adjusted such that the non-doped polycrystalline silicon film portion and the p ⁺ type polycrystalline silicon film are different from the n ⁺ type polycrystalline silicon film. Even in the film part, it does not become significantly low (the relative difference cannot be 0, but the apparent difference becomes smaller by introducing a larger amount of negative ions than the change product). Therefore, regardless of whether it is an n ⁺ -type polycrystalline silicon film or a p ⁺ -type polycrystalline silicon film, it is possible to proceed etching almost uniformly.

Further, since the bias applied to the substrate is pulsed, damage to the substrate is reduced.

Next, the ICP (Inductively Coup) shown in FIG.
An example of a manufacturing process for forming a dual gate by applying the etching method described in the above embodiment using a led plasma) dry etching apparatus will be described with reference to the manufacturing process diagram of FIG. First, the ICP dry etching apparatus will be described with reference to the schematic configuration diagram of FIG.

As shown in FIG. 2, the ICP dry etching apparatus 31 is provided with a chamber 32 for forming an atmosphere for etching an object to be etched. A coil 33 is provided on the outer circumference of the chamber 32, and a high frequency power source 34 for applying a high frequency electric field of 13.56 MHz is connected to the coil 33. An electrode 35 is provided inside the chamber, and the electrode 35
An object to be etched 51 is formed on the upper side (a silicon substrate 11 described later).
The polycrystalline silicon film 13 and the WSi ₂ film 14 which have been formed thereon) are placed thereon. A high frequency bias power source 36 is connected to the electrode 35.

The high frequency power supply 34 and the high frequency bias power supply 36 are both power supplies for which continuous or pulse application methods can be selected. The duty is determined by controlling the on / off time of each pulse to 0.5 μs or more and 30 μs or less, preferably 5 μs or more and 10 μs or less. Shall not occur. Further, the high frequency power source 34 and the high frequency bias power source 36 are connected to a phase matching unit 37 for controlling the phase of the pulse supplied from each power source.

A gas supply system (not shown) for introducing an etching gas into the chamber 32 and a gas exhaust system (exhaust in the figure) for exhausting the gas in the chamber 32 are provided in the chamber 32. Pipe 39 is shown).

In the ICP dry etching apparatus having the above structure, a high frequency electric field of 13.56 MHz is applied to the coil 33 to generate plasma in the chamber 32 and process the film to be etched. Next, as an example, a method for processing a tungsten polycide electrode will be described with reference to FIG.

As shown in FIG. 3A, a gate oxide film 12 is formed on a silicon substrate 11 which is a substrate, and a non-doped polycrystalline silicon film 13 which is a film to be etched is further formed on the gate oxide film 12. Form. After that, the non-doped polycrystalline silicon film 13 is formed by the ion implantation method.
Selectively doped to form a n ⁺ -type polycrystalline silicon film 13n, also non-doped polycrystalline silicon film 13 on the p ⁺ -type impurity [e.g. difluoride the n ⁺ -type impurity [e.g. phosphorus (P)] to Boron (BF ₂ )] is selectively doped to form the p ⁺ -type polycrystalline silicon film 13p. Therefore, n ⁺ type polycrystalline silicon film 13n, non-doped polycrystalline silicon film 13 and p ⁺ type polycrystalline silicon film 13p are formed.

As an example of the above-mentioned ion implantation conditions, in the case of ion implantation of n ⁺ -type impurities, acceleration voltage =
10 keV (projection range Rp = 8.5 nm), dose =
When 5 × 10 ¹⁵ pieces / cm ² is set and ion implantation of p ⁺ type impurities is performed, acceleration voltage = 5 keV (projection range Rp =
8 nm) and the dose amount = 5 × 10 ¹⁵ pieces / cm ² .

Further, a tungsten silicide (WSi ₂ ) film 14 is formed on the polycrystalline silicon film 13, for example, by chemical vapor deposition (hereinafter referred to as CVD, chemical vapor deposition (CVD)).
abbreviated as r Deposition) method.

Subsequently, a resist pattern 15 is formed on the gate electrode formation region by resist coating and a lithographic technique.

Then, the WSi is etched by etching using the resist pattern 15 as an etching mask.
_{2 The} film 14 and the polycrystalline silicon films 13n, 13 and 13p are processed. As the etching apparatus for performing this processing, for example, the ICP dry etching apparatus described with reference to FIG. 2 was used.

In this etching, when the n ⁺ -type polycrystalline silicon film 13n, the undoped polycrystalline silicon film 13 and the p ⁺ -type polycrystalline silicon film 13p are simultaneously etched in plasma, the n ⁺ -type polycrystalline silicon film 13n is formed. The amount of negative ions incident on each polycrystalline silicon film 13 is controlled so as to reduce the difference between the etching rate and the etching rate of the p ⁺ -type polycrystalline silicon film 13p.

An example of the above etching conditions will be described below. Etching gas and flow rate: chlorine (Cl ₂ ): oxygen (O
₂ ) = 100 sccm [hereinafter, sccm represents volume flow rate (cm ³ / min) in standard state]: 5 sccm, etching atmosphere pressure: 0.5 Pa, substrate temperature: 0 ° C., source power: 1.0 kW, source power supply Input: ON: OFF = 3μs: 7μs pulse applied, bias power: 50W (However, when the source power is off, a positive electric field is applied to the silicon substrate 11 in a pulsed manner at 3μs immediately before turning on) did.

By applying the electric field as described above, the amount of negative ions increases when the source pulse electric field is turned off. Since the negative ions thus generated are incident on the substrate when the RF bias pulse is applied, it is possible to suppress a change in etching rate due to the film quality (conductivity type) of polycrystalline silicon to be small. That is, the negative ion concentration on each of the polycrystalline silicon films 13n, 13 and 13p does not become low even in the non-doped polycrystalline silicon film 13 and the p ⁺ -type polycrystalline silicon film 13p (the relative difference cannot be zero). However, by introducing a larger amount of negative ions than the change product, the apparent difference becomes smaller).

Therefore, n⁺Type polycrystalline silicon film 13
n, p⁺Type polycrystalline silicon film 13p, almost uniform
It becomes possible to proceed with the etching. As a result, the figure
As shown in (2) of Section 3,
The oxide film 12 and the silicon substrate 11 may not be dug.
In addition, the undoped polycrystalline silicon film 13 and p⁺Type
The etching residue of the crystalline silicon film 13p may occur.
Without n⁺Type polycrystalline silicon film 13n, non-doped poly
Crystalline silicon film 13 and p ⁺Type polycrystalline silicon film 13
A pattern can be formed by each of p. Yo
Are formed of polycrystalline silicon films with different conductivity types.
Excessive underlayer loss or polycrystalline
Good shape without any etching residue of the recon film
It has become possible to achieve.

The difference in film quality of the polycrystalline silicon film related to the etching rate is caused not only by the conductivity type described above but also by the dose amount. Here, the relationship between the etching rate and the dose amount of the polycrystalline silicon film will be described with reference to FIG. 4A shows a polycrystalline silicon film doped with phosphorus (P), and FIG. 4B shows a polycrystalline silicon film doped with boron difluoride (BF ₂ ).
In each figure, the vertical axis represents the etching rate and the horizontal axis represents the dose amount.

As shown in (1) of FIG. 4, as the dose of phosphorus to the polycrystalline silicon film is increased, the etching rate of the polycrystalline silicon film increases. Further, as shown in (2) of FIG. 4, as the dose amount of boron difluoride with respect to the polycrystalline silicon film is increased, the etching rate of the polycrystalline silicon film decreases.

As described above, the etching rate also changes depending on the type and amount of impurities contained in the polycrystalline silicon film. In particular, in the case of impurities of different conductivity types (phosphorus and boron), the difference in etching rate tends to increase as the dose amount increases. Therefore, it is important to perform the etching by reducing the difference in etching rate by the above-mentioned etching method.

Next, the tungsten polycide described with reference to FIG. 3 was replaced with an ECR (Electron Cycrotron Resonanc).
e) A case of processing with a dry etching device will be described.

First, the ECR dry etching apparatus will be described with reference to the schematic configuration diagram of FIG. As shown in FIG. 5, the ECR dry etching apparatus 41 includes a chamber 4 for forming an atmosphere for etching an object to be etched.
2 is provided. A waveguide 44 is connected to the upper portion of the chamber 42 through a quartz window 43, and the waveguide 44 is provided with a microwave generator 45. The microwave generator 45 generates a pulse microwave of 2.45 GHz, for example, and is connected to a power source 46.
A coil 47 for generating a magnetic field of 875 Gauss is provided on the outer circumference of the chamber 42, and a power source (not shown) is connected to the coil 47.

On the other hand, the electrode 4 is provided inside the chamber 42.
8 is provided on the electrode 48.
Is placed. An RF bias power source 49 is connected to the electrode 48. The RF bias power source 49 applies an alternating electric field of 800 kHz.

Although not shown, the chamber 42
A gas supply system for introducing an etching gas into the chamber 42 and a gas exhaust system for exhausting the gas in the chamber 42 are connected to the.

In the ECR dry etching apparatus 41 having the above structure, the waveguide 44 causes 2.45 GHz.
The microwave of (1) is introduced into the chamber 42 to generate high-density plasma by the resonance of the magnetic field of 875 Gauss from the coil 47, and the etching target 51 is processed.

A method of etching a polycrystalline silicon film similar to that described with reference to FIG. 2 using the ECR dry etching apparatus 41 will be described below. The etching conditions are, for example, etching gas and flow rate: Cl ₂ : O ₂ = 75 scc.
m: 6 sccm, pressure of etching atmosphere: 0.4 Pa, microwave: 800 W (ON: OFF = pulse application of 2 μs: 8 μs), RF power: 60 W, substrate temperature: 0 ° C.

Also in this case, the negative ion amount becomes high when the source pulse electric field is turned off for the same reason as above. The negative ions thus generated are incident on the substrate at the positive period of the RF bias (in this case, since the RF frequency is low, the negative ions move sufficiently to follow the fluctuation of the electric field, and the negative ions move on the substrate. Incident on the substrate), the change in etching rate due to the film quality (conductivity type) of polycrystalline silicon can be suppressed to a small level. Therefore, according to this method, excessive loss of the underlayer or etching residue of the polycrystalline silicon does not occur, so that the n-type polycrystalline silicon and p
Thus, the dual gate electrode made of the polycrystalline silicon can be processed in a good condition.

The present invention is not limited to the one described above, and the etching apparatus and etching conditions can be appropriately changed as long as they are conditions for increasing the negative ion concentration in the etching atmosphere. Further, the plasma generation method is not limited to the ICP method, the ECR method, etc., and a method using a helicon wave, a SWP (Surf
ACE Wave Plasma), magnetron method, etc. may be used. Even in each of the above-mentioned etching devices,
It is desirable that the electron temperature can be controlled to an arbitrary value within the range of 1 V or more and 5 eV or less. Further, such a high-density and low-electron-temperature plasma can also be realized by using a UHF band RF discharge, and in this case also, negative ions can be effectively utilized by using it together with a bias pulse or the like. It is possible.

[0051]

As described above, according to the present invention,
Since the amount of negative ions incident on the film to be etched is controlled in the direction of reducing the difference in etching rate due to the difference in film quality,
The etching rate is controlled by the amount of negative ions supplied from the plasma, and the difference in etching rate depending on the film quality can be reduced. Further, in the above dry etching method, the negative ions generated in the plasma are
Since a positive bias higher than the potential of plasma is applied to the substrate by applying it to the film to be etched, negative radicals are generated regardless of the surface reaction on the substrate and etching can be performed. Therefore, the difference in etching rate due to the difference in film quality is reduced. Therefore,
In the etching process in the manufacturing process of the semiconductor device of the 0.25 μm generation or later, good processing can be performed without causing a shape abnormality corresponding to a fine design rule.

[Brief description of drawings]

FIG. 1 is a timing chart of an embodiment according to the present invention.

FIG. 2 is a schematic configuration diagram of an ICP dry etching apparatus.

FIG. 3 is a manufacturing process diagram of an example in which the present invention is applied to a manufacturing process of a dual gate.

FIG. 4 is a relationship diagram between an etching rate and a dose amount.

FIG. 5 is a schematic configuration diagram of an ECR dry etching apparatus.

FIG. 6 is an explanatory diagram of a problem.

[Explanation of symbols]

11 Silicon Substrate 13 Non-Doped Polycrystalline Silicon Film 13n n ⁺ Type Polycrystalline Silicon Film 13p p ⁺ Type Polycrystalline Silicon Film

Claims (20)

[Claims] 1. A dry etching method in which films to be etched having different film qualities formed on a substrate are simultaneously etched in plasma, wherein an etching rate of a portion having one film quality of the film to be etched and another etching rate of the film to be etched are different from each other. A dry etching method characterized in that the amount of negative ions incident on the film to be etched is controlled so as to reduce the difference from the etching rate of the portion having film quality. 2. The dry etching method according to claim 1, wherein a portion having one film quality of the film to be etched and a portion having the other film quality of the film to be etched are composed of gates of different conductivity types. A dry etching method characterized by forming a dual gate. 3. The dry etching method according to claim 1, wherein the negative ion concentration in the plasma is controlled by changing an electron temperature in a region where the plasma diffuses, or negative ions are present. A dry etching method is characterized in that the electron temperature in a pulse plasma region generated at such an electron temperature is changed and controlled. 4. The dry etching method according to claim 2, wherein the negative ion concentration in the plasma is controlled by changing an electron temperature in a region where the plasma diffuses, or negative ions are present. A dry etching method is characterized in that the electron temperature in a pulse plasma region generated at such an electron temperature is changed and controlled. 5. The dry etching method according to claim 3, wherein the electron temperature is controlled by pulse discharge having a pulse discharge off time of 0.5 μs or more and 30 μs or less. 6. The dry etching method according to claim 4, wherein the electron temperature is controlled by pulse discharge having a pulse discharge off time of 0.5 μs or more and 30 μs or less. 7. The dry etching method according to claim 5, wherein the electron temperature is at least 1 eV to 5 eV during one discharge cycle. 8. The dry etching method according to claim 6, wherein the electron temperature is at least 1 eV or more and 5 eV or less during one discharge cycle. 9. The dry etching method according to claim 1, wherein the negative ions generated in the plasma are introduced onto the film to be etched by applying a positive bias higher than the potential of the plasma to the substrate. And a dry etching method. 10. The dry etching method according to claim 2, wherein the negative ions generated in plasma are introduced onto the film to be etched by applying a positive bias higher than the potential of plasma to the substrate. And a dry etching method. 11. The dry etching method according to claim 3, wherein the negative ions generated in the plasma are introduced onto the film to be etched by applying a positive bias higher than the potential of the plasma to the substrate. And a dry etching method. 12. The dry etching method according to claim 4, wherein the negative ions generated in plasma are introduced onto the film to be etched by applying a positive bias higher than the potential of plasma to the substrate. And a dry etching method. 13. The dry etching method according to claim 9, wherein the bias applied to the substrate is pulse-shaped. 14. The dry etching method according to claim 10, wherein the bias applied to the substrate is pulse-shaped. 15. The dry etching method according to claim 11, wherein the bias applied to the substrate is pulse-shaped. 16. The dry etching method according to claim 12, wherein the bias applied to the substrate is pulse-shaped. 17. The dry etching method according to claim 13, wherein the bias is applied to the substrate in synchronism with the negative ion concentration in the plasma being the highest. 18. The dry etching method according to claim 14, wherein the bias is applied to the substrate in synchronism with the negative ion concentration in the plasma being the highest. 19. The dry etching method according to claim 15, wherein the bias is applied to the substrate in synchronization when the negative ion concentration in the plasma is highest. 20. The dry etching method according to claim 16, wherein the bias is applied to the substrate in synchronization when the negative ion concentration in the plasma is highest.