JPH09311818A - Information processing method, device therefor, memory selecting method for the device, and circuit therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing method and a device therefor, a memory selecting method and circuit for the device which automatically switch a memory even at the time of loading plural memories whose address areas overlap, and execute a program stored in the memory. SOLUTION: At the time of supplying a power, when MPU 1 outputs a selection signal 9 at a high level and MPU 1 accesses the overlapped address area in mask ROM 4 and EPROM 5, a gate array (GA) 2 enables a chip selecting signal CS1 for selecting mask ROM 4. On the other hand, when the selecting signal 9 is at a low level and this overlapped address area is accessed, GA2 enables and outputs a chip select signal CS0 so as to select EPROM 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing method and apparatus having a plurality of memories which are accessed by a CPU and are arranged in address spaces at least partially overlapping with each other, a memory selecting method in the apparatus and a circuit thereof. Is.

[0002]

2. Description of the Related Art In a conventional control device that operates according to a control program stored in a memory, for example, a printing device that performs a printing operation in accordance with print information from a host computer, a mask that stores a control program that controls the operation of the entire printing device. It has a ROM or EPROM and a microprocessor (MPU) for controlling the operation of the entire recording apparatus according to a control program stored in the ROM.
Reads the control program stored in the mask ROM or EPROM, interprets the control program, and controls the entire printing apparatus according to the contents. Usually, in these storage devices, the mask R
There is one type of control program for controlling the recording device stored in the OM or EPROM.

In such a recording apparatus, a plurality of mask ROMs or EPROs storing different control programs are stored.
There are also recording devices with M. In this case, the mask RO
Mask ROM or EP in which the control program actually used is stored on the control board on which M or EPROM is mounted
A selection unit such as a switch for selecting the ROM is provided. The mask ROM or EPRO that is actually used by this switch or the like before the power is turned on or at the time of factory shipment.
M is selected, and when the power is turned on, the MPU reads the control program from the memory selected by the switch and controls the recording apparatus.

[0004]

As described above, in a conventional control device such as a recording device, a plurality of memories each storing a different control program can be mounted, and when the address areas of the respective memories overlap, it is necessary to previously You must select the memory to use. Therefore, it is necessary to provide a selection means for selecting the memory storing the program, and the provision of such means leads to an increase in cost. When a mask ROM or the like storing a new program is added due to a change such as a version upgrade of the control program, the memory for selecting the memory storing the program to be used is selected one by one. There was the trouble of having to specify.

The present invention has been made in view of the above-mentioned conventional example, and even if a plurality of memories having overlapping address areas are mounted, the memories can be automatically switched and the programs stored in the memories can be executed. An object of the present invention is to provide an information processing method and device, a memory selection method in the device, and a circuit thereof.

Another object of the present invention is to automatically determine the memory even if a new memory is mounted in an address area overlapping the address area of the mounted memory and store the memory in the memory. An information processing method and apparatus capable of selectively executing a given program, a memory selection method in the apparatus, and a circuit thereof are provided.

[0007]

In order to achieve the above object, an information processing apparatus according to the present invention has the following arrangement.
That is, an information processing apparatus that has a plurality of memories that are accessed by a CPU and that are arranged in an address space that at least partially overlaps, is output from the CPU when the CPU accesses the overlapping address space. It has a selecting means for selecting one of the plurality of memories according to a selection signal, and the CPU executes the program read from the memory selected by the selecting means.

In order to achieve the above object, the memory selection circuit of the present invention has the following configuration. That is, a memory selection circuit for selecting one of the first and second memories in which at least a predetermined address area is overlapped,
Decoding means for decoding an address signal from U to detect access to a predetermined address area, and a first signal according to a decoding result by the decoding means according to a selection signal output from the CPU. And a memory selection means for outputting a signal for selecting one of the second memories to the selected first or second memory.

In order to achieve the above object, the memory selection method of the present invention includes the following steps. That is, it is a memory selection method for selecting one of the first and second memories in which at least a predetermined address area is overlapped,
A detection step of decoding an address signal from U to detect access to a predetermined address area;
In response to a selection signal output from the PU, a signal for selecting one of the first and second memories according to the detection result in the detection step is set to the selected first or second memory. And the step of outputting to.

In order to achieve the above object, the information processing method of the present invention includes the following steps. That is, an information processing method in an information processing apparatus which can be mounted by a first memory and a second memory which are accessed by a CPU and which are arranged in address areas at least partially overlapping with each other. Is output at a predetermined level, an execution step of reading and executing a program from the first memory in a state where the selection signal of the predetermined level is output, and the execution step, A step of changing the signal level of the selection signal; a step of judging whether the second memory is good or bad by accessing a predetermined address of the second memory while the signal level is changed; , And if the program is judged to be good, the program stored in the second memory is executed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a control circuit of a recording apparatus according to an embodiment of the present invention. Although a recording apparatus is described in this embodiment, the present invention is not limited to this, and may be implemented in various information processing devices other than the recording apparatus, such as a personal computer.

In FIG. 1, reference numeral 1 denotes an MPU, which controls the operation of the entire apparatus by giving control signals and control instructions to each section based on the control program of the recording apparatus of this embodiment. Reference numeral 2 denotes a gate array IC (GA), which is provided with a logic circuit that controls each part according to an instruction from the MPU 1. Reference numeral 3 denotes a DRAM, which writes and reads various data under the control of the MPU 1. 4 is a mask RO
M stores a control program and control data for controlling the operation of the recording apparatus, and further, font data used for printing. Reference numeral 5 denotes an EPROM, which stores a control program and control data executed by the MPU 1 in addition to the mask ROM 4. 6 is EPRO
This is an IC socket for mounting the M5 on a recording device.
In addition, other parts necessary for the recording apparatus according to the present embodiment are omitted.

The above-mentioned MPU1, GA2, DRAM3,
Each unit such as the mask ROM 4 and EPROM 5 is connected to the MPU 1 via a data bus and an address bus, and data can be exchanged between the units via this data bus.

The address area of the EPROM 5 overlaps with the address area of the mask ROM 4 for storing the program and control data. In the overlapping address space, the chip select signal CS0 ( 7) and CS1 (8) select only one of the mask ROM 4 and the EPROM 5.

When the MPU 1 outputs the control program address to the address bus in order for the MPU 1 to access the control program stored in the mask ROM 4 or EPROM 5, the GA 2 outputs the address.
Decode the address to mask ROM 4 or EPR
Chip select signal (C
S0, CS1) is output. As described above, since the mask ROM 4 and the EPROM 5 have the same address area as seen from the MPU 1, whether the mask ROM 4 chip select signal CS1 (8) is output or the EPROM 5 chip select signal CS0 (7) is output. Is determined based on the selection signal 9 from the output port (P0) of MPU1.

Now, the effective address area of the EPROM 5 is set to 8
000H (H indicates a hexadecimal number) to 3FFFFH, and the effective address area of the mask ROM 4 is 8000H.
To 3FFFFFH. Now, chip select signals CS0 (7) and CS1 (8) output from GA2
Is determined as follows according to the chip select selection signal 9 (CSSEL) input from MPU1 to GA2.

That is, when the selection signal 9 (CSSEL) is at the low level, the MPU 1 operates from the address 8000H to 3F.
When accessing up to FFFH, signal CS0 (7)
Is enabled to select the EPROM 5, and when the MPU 1 accesses addresses 40000H to 3FFFFFH, the chip select signal CS1 (8) is enabled to select the mask ROM 4. When the selection signal 9 (CSSEL) is at a high level, when the MPU 1 accesses addresses 8000H to 3FFFFH, the chip select signal CS1 (8) is enabled to select the mask ROM 4, and the chip select signal CS0 is selected.
Do not enable (7). In this way, according to the level of the signal 9 input from the MPU 1 to the GA 2, the mask R
Either OM4 or EPROM5 is selected.

As shown in FIG. 1, the CSSEL terminal of GA2 is connected to the output port P0 of MPU1.
Either the mask ROM 4 or the EPROM 5 is selected according to the output state (signal level) of the output port P0 of U1. In the initial state after the MPU1 is reset, a high level signal is output to the output port P0. Therefore, after the reset, the MPU1 has the address 8000H.
3 to 3FFFFH, the chip select signal CS1 (8) is always enabled and only the mask ROM 4 is accessed.

Next, referring to the flowchart of FIG.
A control operation by the MPU 1 of the recording apparatus according to the present embodiment will be described.

First, in step S1, when the recording apparatus is powered on and the reset is released, the output port P of the MPU 1 is released.
Since a high level signal is output to 0, the MPU
1 is the address of the mask ROM 4 8000H to 3FFFF
Access the program area stored in H,
The control program stored there is read and MP
U1 and GA2 are initialized (step S2). After that, the process proceeds to step S3, and the mask ROM 4 and the DRAM
Check 3 above. These mask ROM4, DRAM
As a result of the check of No. 3, if there is no abnormality, the process proceeds to step S4, and the EPROM determination program stored in the mask ROM 4 is transferred to the DRAM 3.

DRAM of this EPROM determination program
When the transfer process to 3 is completed, the process proceeds to step S5, where MP
U1 sets the execution address of the operation program to the transfer destination address of the EPROM determination program, and thereafter, DR
The EPROM determination program stored in AM3 is read and executed.

Next, in step S6, the MPU 1 sets the output of the output port P0 to low level to set the signal level of the selection signal 9 to low level, and the chip select signal CS0 (7) for selecting the EPROM 5 is enabled. To set. Next, in step S7, E
To check whether the EPROM determination data is stored at an arbitrary address of the PROM 5, that address is read. Then, in step S8, it is determined whether the read data matches the judgment data. If the read data matches the judgment data, the EPR is performed via the IC socket 6.
It is determined that the OM5 is installed, and the process proceeds to step S9. In step S9, the MPU 1 checks whether the data is normally read from the other addresses of the EPROM 5, and if there is no abnormality, the process proceeds to step S11.
The read address of the program is returned to the address of the normal operation, and the normal operation is executed after step S12.

On the other hand, if the data read from the predetermined address of the EPROM 5 does not match the EPROM determination data in step S8, it is determined that the EPROM 5 is not mounted and the process proceeds to step S10. Then, the output signal level of the output port P0 is set to a high level to enable access to the mask ROM 4. Then, the process proceeds to step S11, the read address of the program is returned to the address of the normal operation, and the normal operation is executed in step S12.

FIG. 3 is a block diagram showing an example of the circuit configuration of the GA2 of this embodiment.

In the figure, 31 is a decoder for inputting address signals A18, A17, A16, A15 of the address bus,
A signal corresponding to the 4-bit data is output at a high level. The selection signal 9 is the MPU 1 as described above.
ROM 4 or EP output from the output port PO of
This is a signal for selecting one of the ROMs 5. When the signal level of the selection signal 9 is high and the addresses 8000H to 3FFFFH are output to the address bus, the AND circuit 32 is opened and the chip selection signal CS
1 is enabled. Conversely, when the level of the selection signal 9 is low, the AND circuit 33 is opened and the chip selection signal CS0 is enabled.

Further, the OR circuits 36 and 37 enable the chip selection signal CS1 when any of the address signals A21, A20, A19 and A18 is turned on "1", that is, when the MPU1 accesses the address 40000H or higher. This is a circuit for selecting the mask ROM 4. Incidentally, 3
Reference numerals 4 and 35 are inverter circuits.

Even if the present invention is applied to a system composed of a plurality of devices (for example, host computer, interface device, reader, printer, etc.), a device composed of one device (for example, copying machine, facsimile). Device).

Another object of the present invention is to supply a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or apparatus, and to supply a computer (or CPU) of the system or apparatus.
Or MPU) reads and executes the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the function of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

A storage medium for supplying the program code is, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD.
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

Further, by executing the program code read by the computer, not only the functions of the above-described embodiment are realized, but also the OS (operating system) running on the computer based on the instruction of the program code. ) And the like perform some or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in the memory provided in the function expansion board inserted into the computer or the function expansion unit connected to the computer, based on the instruction of the program code, This also includes a case where a CPU or the like included in the function expansion board or the function expansion unit performs some or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

When the present invention is applied to the above-mentioned storage medium, the storage medium stores the program code corresponding to the above-mentioned flow chart. Briefly, in the memory map example of FIG. Each module shown will be stored in the storage medium. That is, at least the program code of each module of the “instruction process module”, the “first execution process module”, the “determination process module”, and the “second execution process module” may be stored in the storage medium.

As described above, according to the present embodiment, it is possible to automatically select a ROM having a control program later in a recording apparatus capable of having a plurality of different control programs at the same address. Become.
Therefore, when the control program of the recording apparatus is upgraded, the ROM storing the latest program is automatically recognized, and there is no need to make a setting to select the upgrade program. Further, there is an effect that it is possible to surely prevent the situation where the operation by the control program of the additional ROM is not performed due to forgetting to set the memory selection.

[0036]

As described above, according to the present invention, even if a plurality of memories having overlapping address areas are mounted, the memories can be automatically switched and the program stored in the memories can be executed. effective.

Further, according to the present invention, even if a new memory is mounted in an address area overlapping the address area of the mounted memory, the memory is automatically judged and stored in the memory. The effect is that a program can be selectively executed.

[0038]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a control unit of a recording apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the recording apparatus according to the present embodiment.

FIG. 3 is a circuit block diagram showing a configuration of a gate array (GA) of the present embodiment.

FIG. 4 is a memory map diagram of a storage medium that stores a control program in the recording apparatus according to the present embodiment.

[Explanation of Codes] 1 Microprocessor (MPU) 2 Gate Array (GA) 3 DRAM Memory 4 Mask ROM 5 EPROM 6 IC Socket 31 Decoder

Claims (11)

[Claims] 1. An information processing apparatus having a plurality of memories which are accessed by a CPU and are arranged in at least a part of an overlapping address space, wherein the CPU has a function of accessing the overlapping address space. A selection unit that selects one of the plurality of memories according to a selection signal output from the CPU, and the CPU executes the program read from the memory selected by the selection unit. Information processing device. 2. The plurality of memories are arranged in a first memory storing a first program and an address space overlapping the address space of the first memory, and a second memory storing a second program. The information processing apparatus according to claim 1, further comprising: 3. The information processing apparatus according to claim 2, wherein the second memory is detachably attached to the information processing apparatus. 4. The information processing apparatus according to claim 2, further comprising a determination unit that determines whether or not the second memory is mounted. 5. The determination means is configured to determine the second memory based on data stored at a predetermined address of the second memory.
The information processing apparatus according to claim 4, wherein it is determined whether or not the memory is attached. 6. The information according to claim 4, wherein the CPU transfers a program stored in the first memory, which is the determining means, to a RAM and executes the program on the RAM. Processing equipment. 7. A memory selection circuit for selecting one of a first memory and a second memory in which at least a predetermined address area is overlapped, wherein the predetermined address area is accessed by decoding an address signal from a CPU. A signal for selecting either the first memory or the second memory according to a decoding result by the decoding means, according to a selection signal output from the CPU Done first
Or a memory selecting means for outputting to the second memory. 8. The memory selection according to claim 7, further comprising means for selecting a predetermined memory from among the first or second memories other than the predetermined address area. circuit. 9. A memory selection method for selecting one of a first memory and a second memory in which at least a predetermined address area is overlapped, wherein the predetermined address area is accessed by decoding an address signal from a CPU. And a signal for selecting one of the first and second memories according to the detection result in the detection step, according to a detection step of detecting that The first selected
Or a step of outputting to a second memory. 10. The method according to claim 9, further comprising the step of selecting a predetermined memory from among the first or second memories other than the predetermined address area.
Memory selection method described in. 11. A first and a second which are accessed by a CPU and are arranged in address areas at least partially overlapping with each other.
An information processing method in an information processing apparatus capable of mounting the memory, comprising an instruction step of instructing the CPU to output a selection signal at a predetermined level during an initial operation, and outputting the selection signal at the predetermined level. A first execution step of reading a program from the first memory and executing the program in the state of being performed, a changing step of changing the signal level of the selection signal in the execution step, and a state of changing the signal level in the state A judgment step of judging whether the second memory is good or bad by accessing a predetermined address of the second memory; and executing a program stored in the second memory when the judgment step judges that the second memory is good. And a second executing step for performing the information processing method.