JPH09307091A - Amplifying solid-state image pick up element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the local characteristic nonuniformity by a pixel by providing a ring-shaped gate electrode of a pixel transistor in a non-circular shape and uniformalizing the minimum potential under the gate electrode over the whole circumference of the gate electrode. SOLUTION: On a semiconductor area, a non-circular ring-shaped gate electrode 33A which transmits light through a gate insulating film is formed. On the inner side and outer side of the ring-shaped electrode 33A, a pixel MOS transistor 36A which forms one pixel by forming a source area 34 and a drain area 35 by self-alignment is provided. Namely, the pixel MOS transistor 36A is provided by forming its ring-shaped gate electrode 33A in a non-circular shape and uniformalizing the minimum potential under the gate electrode 33A over the whole circumference of the gate electrode 33A. The local characteristic nonuniformity by the pixel is reduced by uniformalizing the minimum potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid state image pickup device, and more particularly to a gate structure of its pixel transistor.

[0002]

2. Description of the Related Art In recent years, in response to a demand for higher resolution of a solid-state imaging device, an amplification type solid-state imaging device which has no smear and can realize fine pixels has been developed in place of a CCD solid-state imaging device. This amplification type solid-state imaging device includes a MOS type transistor for amplifying an optical signal for each pixel,
A signal is read out by using the electric charge accumulated in the pixel by photoelectric conversion as the current modulation of the transistor.

[0003]

11 and 12 show the following.
The comparative example of an amplification type solid-state image sensor is shown. This amplification type solid-state photography
As shown in FIG. 12, the image element 1 has a first conductivity type, for example, p.
Type silicon semiconductor substrate 2 on the second conductivity type, that is, n-type half
The conductor region, ie the overflow barrier region 3 and the p-type
A semiconductor well region 4 is formed, and a p-type semiconductor wafer is formed.
P-type semiconductor leaving a channel region 5 on the surface of the el region 4
P-type sensor well having a higher impurity concentration than the well region 4
A region 6 is formed and SiO is formed on the channel region 5. _TwoEtc.
A circular shape that allows light to pass through the gate insulating film 7
A ring-shaped gate electrode 8 having a center circle shape is formed, and
Areas corresponding to the inside and outside of the ring-shaped gate electrode 8
N-type source region 10 and drain region 11 are formed in the region
The MOS type transistor (one pixel
Below, referred to as pixel MOS transistor) 12 is configured.
You. The ring-shaped gate electrode 8 absorbs light as much as possible.
A thin or transparent material is chosen to avoid
The film polycrystalline silicon is used.

This pixel MOS transistor 12 is shown in FIG.
As shown in FIG. 3, the source regions 1 of the pixel MOS transistors 12 corresponding to each column are arranged in a matrix.
0 is connected to a common signal line 16 formed of, for example, the first layer Al formed along the vertical direction, and is arranged at a position corresponding to each row of the pixel MOS transistors 12 so as to be orthogonal to the signal line 16, for example, the second layer. A vertical selection line 17 is formed in Al along the horizontal direction.

[0005] Two horizontally adjacent pixels M
The inter-pixel wiring layer 15 is connected to the ring-shaped gate electrode 8 of the OS transistor 12, and the intermediate portion of the inter-pixel wiring layer 15 is connected to the vertical selection line 17. 18 is an inter-pixel wiring layer 15
And a vertical selection line 17 and a contact portion 19 between the source region 10 and the signal line 16.

Further, a drain power supply line 20 made of, for example, the first layer Al connected to the drain region 11 is formed between each two pixel MOS transistors 12 not connected to the inter-pixel wiring layer 15. Reference numeral 21 is a contact portion between the drain region 11 and the drain power supply line 20.

In this pixel MOS transistor 12, as shown in FIG. 12, the light transmitted through the ring-shaped gate electrode 8 generates electrons and holes, of which the holes h serve as signal charges to form the ring-shaped gate electrode. It is accumulated in the sensor well region 6 below. When a high voltage is applied to the ring-shaped gate electrode 8 through the vertical selection line 17 and the pixel MOS transistor 12 is turned on, the channel current Id flows to the p ⁻ channel region 5 on the surface, and the channel current Id is the signal charge h.
The channel current Id is output through the signal line 16 and the amount of change is output as a signal.

Incidentally, in the pixel MOS transistor 12, shown in FIG. 13 in order to make the accumulated signal charge h uniform over the channel and at the same time make the channel current flowing at the time of reading the pixel signal uniform over the entire gate. As described above, the gate electrode 8 is formed in the concentric shape as much as possible.

In FIG. 13, chain lines a and b indicate equipotential lines, and a shaded region 22 indicates a deep potential. The deep potential region 22 is evenly distributed over the entire circumference of the ring-shaped gate electrode 8. Has been formed.

However, if the pixel pitch is the same in both the horizontal and vertical directions, the gate electrode 8 may simply have the concentric shape shown in FIG. 13, but the pixel size in the horizontal direction is different from that in the vertical direction. In the solid-state imaging device, in order to maximize the ratio of the pixel transistor region and improve the sensitivity, the dynamic range, and the sampling characteristics, as shown in FIG. 14, the gate electrode 8 ′ having an oval ring shape (or an elliptical ring shape) is simply used. I was trying. This is an elliptical ring shape in which the channel length L ₁ is simply made constant in order to obtain a uniform channel current.

In this elliptic ring-shaped gate structure, as shown by equipotential lines c, d, and e in FIG.
Due to the three-dimensional effect, the lower sensor potential well becomes shallower in the curved portion AB than in the straight portion CD (small in absolute voltage value), resulting in a non-uniform potential. In FIG. 14, the shaded area 23 indicates the deepest potential.

FIG. 15 shows how the potential becomes non-uniform in FIG. A region where the curvature of the gate electrode 8'is small, that is, a region where the curve of the electrode shape is acute, is three-dimensionally affected by the drain region 11. For this reason, the potential in the sensor well region of the curved portion AB becomes shallow due to being dragged by the drain voltage. As a result, more electric charge is stored in the region 23 of the linear portion CD. In particular, in the case of a minute signal charge, since the charge is stored only in the region 23 of the linear portion CD, this output signal is not an output that reflects the entire channel.

Depending on the reading method, the linear portion CD where the charge is stored regulates the current or the curved portion regulates, and the output signal value is locally determined. Therefore, there is a problem that variations in pixel signal output are enlarged.

In order to avoid these problems, if the shape of the gate electrode is formed concentrically in the horizontally long unit pixel as in FIG. 13, the effective sensor area (that is, the gate area) becomes small, so that the sensitivity also decreases. Resulting in.

As described above, in the amplification type solid-state image pickup device in which the unit pixel sizes in the horizontal direction and the vertical direction are different from each other, the original sensitivity cannot be fully utilized and sufficient pixel characteristics cannot be obtained.

In view of the above points, the present invention solves the deterioration of sensitivity variation, and particularly in a solid-state image pickup device in which the unit pixel size varies depending on the direction from the pixel center, an amplification type which secures a large sensitivity and a dynamic range. A solid-state imaging device is provided.

[0017]

In the amplification type solid-state imaging device according to the present invention, the ring-shaped gate electrode of the pixel transistor is made non-circular, and the minimum potential under this gate electrode is made uniform over the entire circumference of the gate electrode. . In this way, the minimum potential under the non-circular ring-shaped gate electrode is made uniform over the entire circumference of the gate electrode, so that characteristic variations are reduced.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The amplification type solid-state imaging device according to the present invention has a structure in which a ring-shaped gate electrode of a pixel transistor has a non-circular shape, and a minimum potential under the gate electrode is made uniform over the entire circumference of the gate electrode. To do.

According to the present invention, in the amplification type solid-state imaging device, the gate length of a portion of the gate electrode having a small curvature or a portion corresponding to a corner is set to be larger than that of the other portions.

According to the present invention, in the amplification type solid-state image pickup device, the impurity concentration of the lower portion of the portion corresponding to the corner of the gate electrode having a small curvature or the corner portion is set higher than that of the lower portion of the other portion of the gate electrode. And

According to the present invention, in the above amplification type solid-state imaging device, the gate length of a portion of the gate electrode having a small curvature or a portion corresponding to a corner is set to be larger than that of the other portion, and the curvature of the gate electrode is The impurity concentration of the lower portion of the small portion or the portion corresponding to the corner is set to be higher than that of the other portion of the gate electrode.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

The amplification type solid-state image pickup device of this embodiment is, for example, an amplification type solid-state image pickup device having unit pixels of different sizes in the horizontal direction and the vertical direction, or a polygonal unit pixel, depending on the curvature of the gate electrode. , Or the gate length is changed according to the corner or non-corner, or according to the curvature,
Alternatively, the impurity (so-called channel impurity concentration) in the region used for accumulating signal charges under the gate electrode is changed according to the corner and the non-corner, or both the gate length and the impurity concentration are changed. .

FIG. 1 shows a basic configuration example common to each embodiment of the amplification type solid-state image pickup device according to the present invention. As shown in FIG. 1, an amplification type solid-state imaging device 31 according to the present example is a non-circular ring-shaped gate electrode capable of transmitting light on a semiconductor region through a gate insulating film, for example, a ring having different vertical and horizontal lengths. -Shaped gate electrode, in this example, an elliptical ring-shaped gate electrode 33 is formed, and a source region 34 and a drain region 35 are formed by self-alignment in portions corresponding to the inside and outside of the ring-shaped gate electrode 33. As a result, a pixel MOS transistor 36 that becomes one pixel is configured.

A plurality of pixel MOS transistors 36 are arranged in a matrix, and the pixel MOS transistors corresponding to each column are arranged.
The source region 34 of the transistor 36 is connected to a common signal line 37 formed of, for example, the first layer Al formed in the vertical direction, and the pixel MOS is formed so as to be orthogonal to the signal line 37.
For example, in the position corresponding to each row of the transistors 36, the second
A vertical selection line 38 made of the layer Al is formed along the horizontal direction.

Then, two pixels M adjacent in the horizontal direction
Each ring-shaped gate electrode 3 of the OS transistor 36
3 is connected to the inter-pixel wiring layer 39, and the inter-pixel wiring layer 3
A vertical selection line 38 is connected to the middle portion of the line 9.

Further, a drain power supply line 40 made of, for example, the first layer Al and connected to the drain region 35 is formed between each two adjacent pixel MOS transistors 36 to which the inter-pixel wiring layer 39 is not connected. 41 is a drain power supply line 4
0, the drain contact portion between the drain region 35, 42
Is a source contact portion between the source region 34 and the signal line 37, and 43 is a contact portion between the inter-pixel wiring layer 39 and the vertical selection line 38.

The present invention is particularly characterized by the pixel MOS transistor 36 of the amplification type solid-state image pickup device 31.

2 and 3 show a first embodiment of an amplification type solid-state image pickup device according to the present invention, particularly a pixel MOS transistor thereof. In the first embodiment, the gate length is optimized according to its curvature. 2 is a plan view showing only the pixel MOS transistor of one pixel, omitting the signal line, vertical selection line, inter-pixel wiring layer and drain power supply line in FIG. 1, and FIG. 3 shows a cross section taken along line III-III in FIG. .

In this example, as shown in FIGS. 2 and 3, a second conductivity type or n type semiconductor layer, that is, overflow barrier regions 52 and p are formed on a silicon semiconductor substrate 51 of the first conductivity type, for example, p type. The type semiconductor well region 53 is formed. Further, a p-type sensor well region 55 having an impurity concentration higher than that of the p-type semiconductor well region 53 is formed while leaving the channel region 54 on the surface of the p-type semiconductor well region 53, and a gate made of SiO ₂ or the like is formed on the channel region 54. An elliptic (or elliptical) ring-shaped gate electrode 33A capable of transmitting light is formed through the insulating film 56.

This elliptical ring-shaped gate electrode 33A
Of the n-type source region 34 by ion implantation by self-alignment so as to sandwich the gate electrode on the semiconductor surfaces corresponding to the inner side and the outer side, respectively, in the present example, to the semiconductor surface reaching from the sensor well region 55 to the p-type semiconductor well region 53. And a drain region 35 is formed. The drain region 35 is formed all over the pixels.

In this example, in particular, in the elliptical gate electrode 33A, the gate length L ₁ of the curved portion is set to be larger than the gate length L ₂ of the straight portion (L ₁ > L ₂ ). In order to increase the gate length L ₁ of the curved portion, there is no margin on the drain region 35 side, so the gate length is extended on the source region 34 side. Further, since the curvature changes, the gate length is continuously changed accordingly.
The thickening width of the gate length at this time has different optimum values depending on the absolute value of the potential and the reference gate length, so that optimization is performed by a three-dimensional simulation or the like. In this way, the pixel MOS transistor 26A according to the first embodiment is configured.

The smaller the curvature of the gate electrode, that is, the sharper the curve of the electrode shape, the three-dimensionally the short channel effect becomes stronger due to the voltage of the drain region 35, and as a result, the sensor potential is dragged by the drain voltage and becomes shallower. Therefore, the above-described first embodiment is based on the principle that the gate length is made longer to suppress the three-dimensional effect of the drain and deepen the sensor potential.

According to the amplification type solid-state imaging device having the pixel MOS transistor 36A according to the first embodiment, the gate length L ₁ of the curved portion of the gate electrode 33A in the pixel MOS transistor 36A is changed to the gate length L _{2 of the} straight portion. By making it larger, the three-dimensional effect of the voltage of the drain region 35 on the portion of the sensor well region corresponding to the curved portion is suppressed. Therefore, as shown in the potential distribution (equipotential line) in plan view of FIG. 4 and the potential diagram of FIG. 5, the same sensor potential well, that is, the minimum potential φ, is used in the linear portion CD and the curved portion AB.
A sensor potential well having _m and having a uniform or nearly uniform state over the entire circumference of the gate electrode can be obtained.
In FIG. 4, g and h indicate equipotential lines, and the shaded region 61 indicates a deep potential.

Therefore, the local characteristic variation for each pixel is reduced. Compared to the second embodiment described below, the first embodiment does not require additional steps for mask alignment and ion implantation, does not cause misalignment, and is easy to manufacture.

6 to 8 show a second embodiment of the amplification type solid-state image pickup device according to the present invention, particularly the pixel MOS transistor thereof. In the second embodiment, the impurity concentration in the sensor well region is changed according to the shape of the gate electrode.
6 is a plan view showing only the pixel MOS transistor of one pixel by omitting the signal line, vertical selection line, inter-pixel wiring layer and drain power supply line in FIG. 1, and FIG. 7 is a cross-sectional view taken along line VII-VII of FIG. 8 shows a cross section on the line VIII-VIII in FIG.

In this example, an elliptic (or elliptical) ring-shaped gate electrode 33B is formed in which the gate length L ₃ is kept constant over the whole area.

The portion of the sensor well region corresponding to the curved portion of the gate electrode 33B (hatched portion in FIG. 6).
55A is ion-implanted with an impurity which is several percent higher than that of the sensor well region portion (the portion without hatching in FIG. 6) 55B corresponding to the linear portion selectively through the resist mask, that is, boron which is a p-type impurity. After implantation, the impurity concentration of the sensor well region 55A corresponding to the curved portion is set higher than the impurity concentration of the sensor well region 55B corresponding to the linear portion. In this way, the pixel MOS transistor 36B according to the second embodiment is configured.

Other configurations are the same as those in FIGS. 2 and 3 described above, and therefore, corresponding parts will be denoted by the same reference numerals and redundant description will be omitted. The gate electrode 3 is formed by ion implantation of the above impurities.
The portion 55 of the sensor well region corresponding to the curved portion of 3B
The potential of A can be deepened.

According to the amplification type solid-state image pickup device having the pixel MOS transistor 36B according to the second embodiment, the impurity concentration of the sensor well region 55A corresponding to the curved portion of the gate electrode 33B in the pixel MOS transistor 36B is adjusted. , The three-dimensional influence of the voltage of the drain region 35 on the portion 55A of the sensor well region corresponding to the curved portion is set by setting the impurity concentration higher than that of the portion 55B of the sensor well region corresponding to the straight portion of the gate electrode 33B. Suppressed. Therefore, as shown in the potential distribution (equipotential lines) in plan view of FIG. 9 and the potential diagram of FIG. 10, the straight line portion CD and the curved portion AB have the same sensor potential well, that is, the minimum potential φ _m , and the gate A sensor potential well that is uniform or nearly uniform is obtained over the entire circumference of the electrode 33B. In FIG. 9, i and j have equipotential lines, and the hatched region 62 indicates a deep potential.

Therefore, similar to the first embodiment, the local characteristic variation for each pixel is reduced.

As described above, in the embodiment according to the present invention, the gate length or the amount of impurities doped in the sensor well region is optimized to make the gate electrode 33A or 33B.
The potential of the lower sensor well region 55 can be made uniform over the entire circumference of the gate electrode 33A or 33B. Therefore, there is no bias in the area where the signal charge is accumulated, and even if the signal of the sensor accumulated charge is read as the channel current or the channel surface voltage, a uniform signal for the entire gate can be obtained. Can obtain a constant output. Since the charge accumulation and the read channel current are made uniform, the variation for each pixel is relatively averaged and reduced. In the above-mentioned embodiment, the method of the first embodiment is excellent because it is a method that does not increase the number of steps.

On the other hand, if the correction cannot be completed by only changing the gate length of the first embodiment or changing the dose amount of the sensor well region of the second embodiment, both are performed simultaneously. That makes it more effective.

In the above example, the present invention is applied to a pixel MOS transistor having a gate electrode that is different in vertical and horizontal lengths, for example, an elliptical gate electrode. , Its corners,
By changing the gate length or the impurity dose amount with respect to other parts, an amplification type solid-state image pickup device having the same effect can be obtained.

In the above example, the present invention is applied to the n-channel pixel MOS transistor, but it can also be applied to other p-channel pixel MOS transistors.

In addition, Charge Modulation Device Image S
Bulk channel type like ensor (CMD), Bulk Charg
The present invention can be applied to an amplification type solid-state imaging device using pixel transistors of different channel types such as an e Modulated Device (BCMD).

[0047]

According to the present invention, the minimum potential is also applied to an amplification type solid-state image pickup device having a so-called non-circular pixel transistor such as a pixel transistor having different horizontal and vertical sizes or a polygonal pixel transistor. Are substantially uniformed, and local characteristic variations among pixels are reduced. Further, in the case of the structure in which the gate length is changed according to the curvature, there is an advantage that the manufacturing can be performed without increasing the manufacturing process.

[Brief description of drawings]

FIG. 1 is a plan view showing a basic configuration example of an amplification type solid-state imaging device according to the present invention.

FIG. 2 is a plan view of a first embodiment showing only a pixel MOS transistor according to the present invention.

FIG. 3 is a sectional view taken along the line III-III in FIG.

FIG. 4 is a plan view showing a potential distribution (equipotential lines) in the pixel MOS transistor according to the first example.

5 is a potential part showing a potential distribution between a curved line portion AB and a straight line portion CD in FIG.

FIG. 6 is a plan view of a second embodiment showing only a pixel MOS transistor according to the present invention.

7 is a sectional view taken along line VII-VII of FIG.

8 is a cross-sectional view taken along the line VIII-VIII in FIG.

FIG. 9 is a plan view showing a potential distribution (equipotential lines) in the pixel MOS transistor according to the second example.

10 is a potential diagram showing a potential distribution between a curved line portion AB and a straight line portion CD in FIG.

FIG. 11 is a configuration diagram of an amplification type solid-state imaging device according to a comparative example.

FIG. 12 is a cross-sectional view of a pixel MOS transistor of a comparative example.

FIG. 13 is a pixel MO having a circular ring-shaped gate electrode.
Potential distribution in S-transistor (equipotential line)
FIG.

FIG. 14 is a pixel M having an elliptic ring-shaped gate electrode.
The potential distribution map in an OS transistor.

15 is a potential diagram showing a potential distribution between a curved line portion AB and a straight line portion CD in FIG.

[Explanation of symbols]

33, 33A, 33B oval ring-shaped gate electrode,
34 source region, 35 drain region, 37 signal line, 38 vertical selection line, 40 drain electrode line, L ₁ ,
L ₂ , L ₃ gate length, 55, 55A, 55B sensor well area

Claims (4)

[Claims] 1. An amplification type solid-state imaging device, wherein a ring-shaped gate electrode of a pixel transistor has a non-circular shape, and a minimum potential under the gate electrode is made uniform over the entire circumference of the gate electrode. 2. The amplification type solid-state imaging device according to claim 1, wherein a gate length of a portion of the gate electrode having a small curvature or a portion corresponding to a corner is set to be larger than that of the other portion. element. 3. The impurity concentration of the lower portion of the portion of the gate electrode having a small curvature or the portion corresponding to the corner is set to be higher than that of the lower portion of the other portion of the gate electrode. Item 2. The amplification type solid-state imaging device according to item 1. 4. A gate length of a portion of the gate electrode having a small curvature or a portion corresponding to a corner is set to be larger than that of the other portion, and a portion of the gate electrode having a small curvature or a corner is provided. The amplification type solid-state imaging device according to claim 1, wherein the impurity concentration of the lower portion of the portion to be formed is set to be higher than the lower portion of the other portion of the gate electrode.