JPH09306871A - Method and apparatus for manufacturing semiconductor device - Google Patents

Method and apparatus for manufacturing semiconductor device

Info

Publication number
JPH09306871A
JPH09306871A JP8117589A JP11758996A JPH09306871A JP H09306871 A JPH09306871 A JP H09306871A JP 8117589 A JP8117589 A JP 8117589A JP 11758996 A JP11758996 A JP 11758996A JP H09306871 A JPH09306871 A JP H09306871A
Authority
JP
Japan
Prior art keywords
electrode
film
semiconductor element
oxide film
natural oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8117589A
Other languages
Japanese (ja)
Other versions
JP3334489B2 (en
Inventor
Kazuhiko Matsumura
和彦 松村
Hiroaki Fujimoto
博昭 藤本
Tetsuo Kawakita
哲郎 河北
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11758996A priority Critical patent/JP3334489B2/en
Publication of JPH09306871A publication Critical patent/JPH09306871A/en
Application granted granted Critical
Publication of JP3334489B2 publication Critical patent/JP3334489B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To form a high-connectability metal film by electroless plating while preventing a natural oxide film from being formed on Al electrodes of a semicon ductor device. SOLUTION: A natural oxide film on Al electrodes 2 is uniformly removed by dry etching and then plating is made in an inert atmosphere to perfectly prevent the natural oxide film on the electrodes 2 from being formed again. This eliminates the need of treatments such as Zn grain film forming to avoid forming the natural oxide film. Thus it is possible to form electrodes having a good adhesion property and high connectability by electroless plating.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子のベアチ
ップ実装に用いる接合用電極の形成方法と電極形成装置
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bonding electrode used for mounting a bare chip on a semiconductor element and an electrode forming apparatus.

【0002】[0002]

【従来の技術】近年、半導体素子のAl電極上に無電解
めっき法によって接合用電極を形成する電極形成方法に
おいては、形成工程のすべてを湿式工程により電極形成
している。
2. Description of the Related Art In recent years, in an electrode forming method for forming a bonding electrode on an Al electrode of a semiconductor element by an electroless plating method, all the forming steps are performed by a wet process.

【0003】以下図面を参照しながら、上記した従来の
無電解めっき法による電極形成方法の一例について説明
する。
An example of an electrode forming method by the above-mentioned conventional electroless plating method will be described below with reference to the drawings.

【0004】図5は無電解めっき法による電極の形成を
行なう前のAl電極付近の半導体素子の断面図を示した
ものであり、図6は上記の図5に示した半導体素子に対
して無電解めっき法により電極を形成する工程断面図を
示したものである。図5及び図6において、1は半導体
素子のAl電極、2は自然酸化膜、6は半導体素子、2
8は保護膜、33はシリコン酸化膜、3はZn粒子膜、
4はNi膜、5はAu膜を示している。
FIG. 5 shows a cross-sectional view of the semiconductor element in the vicinity of the Al electrode before the formation of the electrode by the electroless plating method, and FIG. 6 shows the semiconductor element shown in FIG. It is a sectional view showing a step of forming an electrode by an electrolytic plating method. 5 and 6, 1 is an Al electrode of a semiconductor element, 2 is a natural oxide film, 6 is a semiconductor element, 2
8 is a protective film, 33 is a silicon oxide film, 3 is a Zn particle film,
Reference numeral 4 is a Ni film, and 5 is an Au film.

【0005】次に以下では、図6を参照しながら、半導
体素子に対して無電解めっき法により電極を形成する従
来の方法について説明する。
A conventional method for forming electrodes on a semiconductor element by electroless plating will be described below with reference to FIG.

【0006】まず、図6(a)は、半導体素子6上に形
成されたAl電極1のウエットエッチング工程を示した
ものである。この工程において、Al電極1の表面に形
成された自然酸化膜2をリン酸や水酸化ナトリウムの水
溶液中に浸漬することによって、除去する。次に図6
(b)に示すようにAl電極1上にZn粒子膜を形成す
る。上記した図6(a)の工程によって自然酸化膜を除
去したが、そのまま放置すると再度Al電極1上に自然
酸化膜が軽視得されてしまうため、このAl電極1上へ
の自然酸化膜の再形成を防止するために、室温に保持し
たZnを含有するアルカリ性(pH13〜14)の溶液
中に半導体素子を30秒浸漬することにより、Alと溶
液中のZnイオンの置換反応を利用してAl電極1の表
面に膜厚300〜500Å程度のZn粒子膜3を形成す
る。
First, FIG. 6A shows a wet etching process of the Al electrode 1 formed on the semiconductor element 6. In this step, the natural oxide film 2 formed on the surface of the Al electrode 1 is removed by immersing it in an aqueous solution of phosphoric acid or sodium hydroxide. Next, FIG.
As shown in (b), a Zn particle film is formed on the Al electrode 1. The natural oxide film was removed by the process of FIG. 6 (a) described above, but if it is left as it is, the natural oxide film will be neglected again on the Al electrode 1. In order to prevent the formation, by immersing the semiconductor element in an alkaline (pH 13 to 14) solution containing Zn kept at room temperature for 30 seconds, the substitution reaction between Al and Zn ion in the solution is utilized to form Al. A Zn particle film 3 having a film thickness of about 300 to 500 Å is formed on the surface of the electrode 1.

【0007】次に図6(c)に示すようにAl電極1上
に無電解めっき法によりNiめっきを形成する。上記の
図6(b)の工程において形成されたZn粒子膜3が無
電解Niめっき液中で溶解することで、Znと無電解N
iめっき液中のNiイオンの置換反応によりNiが析出
した後に無電解Niめっき液の自己還元反応によりNi
上にNiが自己析出し、Ni膜4が形成される。さらに
図6(d)に示すように、形成されたNi膜4上に無電
解めっき法によりAu膜を形成する。これは、Ni膜4
単独ではNiの酸化膜の存在により電気的な接続性が悪
いことを改善するために行なわれる工程であり、電気的
な接続性を高める目的でAu膜5をNiと無電解Auめ
っき液中のAuイオンとの置換反応によって形成する。
Next, as shown in FIG. 6C, Ni plating is formed on the Al electrode 1 by electroless plating. The Zn particle film 3 formed in the above step of FIG. 6B is dissolved in the electroless Ni plating solution, whereby Zn and electroless N
After Ni is deposited by the substitution reaction of Ni ions in the i plating solution, Ni is deposited by the self-reduction reaction of the electroless Ni plating solution.
Ni is self-deposited on the upper surface and a Ni film 4 is formed. Further, as shown in FIG. 6D, an Au film is formed on the formed Ni film 4 by electroless plating. This is the Ni film 4
This is a process performed by itself to improve the poor electrical connectivity due to the presence of the Ni oxide film. For the purpose of enhancing the electrical connectivity, the Au film 5 and Ni in an electroless Au plating solution are used. It is formed by a substitution reaction with Au ions.

【0008】なお、上記の図6(a)から図6(d)の
工程を通常は大気中で電極形成を行っている。
Incidentally, the electrodes are usually formed in the air in the steps of FIGS. 6 (a) to 6 (d).

【0009】[0009]

【発明が解決しようとする課題】上記したように、半導
体素子のAl電極上に化学反応を利用した無電解めっき
法によって金属膜を形成するには、Al電極表面に強固
な自然酸化膜が存在するため、Al電極表面で無電解め
っきの反応を起こさせるためには、化学反応を妨げるA
l電極表面の自然酸化膜の除去が必須である。
As described above, in order to form a metal film on an Al electrode of a semiconductor element by an electroless plating method utilizing a chemical reaction, a strong natural oxide film exists on the Al electrode surface. Therefore, in order to cause a reaction of electroless plating on the surface of the Al electrode, A
It is essential to remove the natural oxide film on the l-electrode surface.

【0010】しかしながら上記のような従来の無電解め
っき法を利用した電極形成では、ウエットエッチングで
自然酸化膜の除去を行うため、エッチング状態が自然酸
化膜の膜厚や密度の状態により一定しない。また、空気
中の酸素、または溶液や洗浄水中の溶存酸素により、自
然酸化膜を除去したAl電極表面への自然酸化膜の再形
成が生じてしまうために、Zn粒子膜3形成の処理工程
が必要不可欠となる。さらに、上記Zn粒子膜3により
Al電極と無電解めっきによる金属膜との密着性が悪く
なるという問題点を有していた。
However, in the electrode formation using the conventional electroless plating method as described above, since the natural oxide film is removed by wet etching, the etching state is not constant depending on the thickness and density of the natural oxide film. Further, since the natural oxide film is reformed on the Al electrode surface from which the natural oxide film has been removed due to oxygen in the air or dissolved oxygen in the solution or the cleaning water, the treatment step for forming the Zn particle film 3 is performed. It becomes indispensable. Further, the Zn particle film 3 has a problem that the adhesion between the Al electrode and the metal film formed by electroless plating is deteriorated.

【0011】[0011]

【課題を解決するための手段】上記問題点を解決するた
めに本発明の半導体素子への電極形成方法は、ドライエ
ッチングによる半導体素子のAl電極上の自然酸化膜除
去と不活性雰囲気に制御した環境下での半導体素子の搬
送と無電解めっき法によって金属膜を形成する工程を備
えたものである。
In order to solve the above problems, in the method of forming an electrode on a semiconductor device of the present invention, the natural oxide film on the Al electrode of the semiconductor device is removed by dry etching and controlled to an inert atmosphere. It is provided with the steps of transporting the semiconductor element under the environment and forming the metal film by the electroless plating method.

【0012】そして、上記の構成により、本発明は、不
活性雰囲気中でめっき工程を処理することによりAl電
極の自然酸化膜の再形成を完全に防止するとともに、自
然酸化膜の形成防止のためのZn粒子膜3形成等の処理
工程を省略することができる。このことにより、密着性
が良く、接続性の高い無電解めっきによる電極を形成す
ることができる。
With the above structure, the present invention completely prevents the re-formation of the natural oxide film of the Al electrode by treating the plating step in an inert atmosphere and at the same time, prevents the formation of the natural oxide film. The processing steps such as the formation of the Zn particle film 3 can be omitted. This makes it possible to form an electrode by electroless plating having good adhesion and high connectivity.

【0013】[0013]

【発明の実施形態】以下本発明の実施の形態における半
導体素子への接合用電極の形成方法について、図面を参
照しながら説明する。
BEST MODE FOR CARRYING OUT THE INVENTION A method for forming a bonding electrode on a semiconductor element according to an embodiment of the present invention will be described below with reference to the drawings.

【0014】(実施の形態1)図1は本発明実施の形態
1における接合用電極を有する半導体素子の断面図、図
2は本実施の形態における接合用電極を形成する装置の
概略図、図3は半導体素子に対する接合用電極形成の工
程断面図を示したものである。なお、図1〜図3におい
てにおいて、1はAl電極、6は半導体素子、7はNi
膜、8はAu膜を示している。
(First Embodiment) FIG. 1 is a sectional view of a semiconductor element having a bonding electrode according to the first embodiment of the present invention, and FIG. 2 is a schematic view of an apparatus for forming a bonding electrode according to the present embodiment. 3 is a process sectional view of forming a bonding electrode for a semiconductor element. 1 to 3, 1 is an Al electrode, 6 is a semiconductor element, and 7 is Ni.
A film, 8 is an Au film.

【0015】そこで以下では、まず図1に示した半導体
素子における接合用電極について説明する。半導体素子
の外部電極であるAl電極1上に無電解めっき法により
Ni膜を析出により形成し、更にその上にAu膜を無電
解で析出し接続用突起電極を形成した構成となってい
る。図1に示した半導体素子をベアチップ実装する場合
は、上記の接合用突起電極を直接回路基板にフリップチ
ップ実装で接続したり、またTCPにパッケージングす
る。
Therefore, first, the bonding electrodes in the semiconductor device shown in FIG. 1 will be described below. A Ni film is formed by deposition on an Al electrode 1 which is an external electrode of a semiconductor element by electroless plating, and an Au film is deposited on the Al film electrolessly to form a connecting projection electrode. When the semiconductor device shown in FIG. 1 is mounted on a bare chip, the above-mentioned bonding protruding electrodes are directly connected to the circuit board by flip-chip mounting or packaged in a TCP.

【0016】上記のように半導体素子は、通常外部と電
気的な接続をするための外部電極を有しており、通常、
樹脂パッケージ等にパッケージングする場合は、この外
部電極に金属ワイヤーを接続する。外部電極は、半導体
素子の配線に用いられるAlが用いられている。近年、
電子機器の小型、高機能化の要求から、従来の樹脂パッ
ケージに変わり、TCP(Tape Carrier
PKG)や、さらにベアチップを直接、回路基板に実装
するフリップチップ方式等の、高密度実装技術が必要と
されている。これらの、実装技術に用いる、半導体素子
の外部電極には、図1に示すような、接合用突起電極を
必要とする。
As described above, the semiconductor element usually has an external electrode for making an electrical connection to the outside.
When packaging in a resin package or the like, a metal wire is connected to this external electrode. As the external electrode, Al used for wiring of the semiconductor element is used. recent years,
Due to the demand for smaller and more sophisticated electronic equipment, TCP (Tape Carrier)
PKG), and further, a high-density mounting technology such as a flip-chip method for directly mounting a bare chip on a circuit board is required. These external electrodes of the semiconductor element used in the mounting technique require a protruding electrode for bonding as shown in FIG.

【0017】次に、図2及び図3を参照しながら、本発
明の実施の形態における半導体素子の製造方法を工程順
に説明する。
Next, with reference to FIGS. 2 and 3, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in the order of steps.

【0018】まず図3(a)は半導体素子上に形成され
たAl電極1のドライエッチング工程を示したものであ
る。上記の図3(a)の工程は、図2のドライエッチン
グ装置12内で行なわれる。なお、ドライエッチング装
置12は、17の真空ポンプ、18の電源、19の高周
波発生装置、Arやフレオンのスパッタガス29を吸入
するための20の吸入バルブを有している。
First, FIG. 3A shows a dry etching step of the Al electrode 1 formed on the semiconductor element. The above process of FIG. 3A is performed in the dry etching apparatus 12 of FIG. The dry etching apparatus 12 has 17 vacuum pumps, 18 power supplies, 19 high-frequency generators, and 20 suction valves for sucking Ar or Freon sputtering gas 29.

【0019】具体的には、ドライエッチング装置12の
電極27に半導体素子6を設置し、真空ポンプ17によ
りドライエッチング装置12内を真空に引き、吸入バル
ブ20よりArやフレオンのスパッタガス29をドライ
エッチング装置12内に充填し、電源18の電圧を上げ
高周波発生装置19によって高周波をかけながら、Ar
やフレオンのスパッタガス29によりAl電極1上の自
然酸化膜2が完全になくなるまでエッチングを行い、酸
化膜のないAl面11を露出させる。
Specifically, the semiconductor element 6 is installed on the electrode 27 of the dry etching apparatus 12, the inside of the dry etching apparatus 12 is evacuated by the vacuum pump 17, and the sputtering gas 29 of Ar or Freon is dried by the suction valve 20. It is filled in the etching device 12, the voltage of the power supply 18 is raised, and a high frequency is applied by the high frequency generator 19, while Ar
Etching is performed until the natural oxide film 2 on the Al electrode 1 is completely removed by a Freon sputtering gas 29 to expose the Al surface 11 having no oxide film.

【0020】次に図3(b)に示す状態で半導体素子6
の搬送を行なう。この工程では、図2の搬送路14内を
搬送する。そして搬送路14は、搬送路14内を真空に
引くための23の真空ポンプ、ドライエッチング装置1
2と搬送路14の接続部に24の第1ロードロック、無
電解めっき装置13と搬送路14の接続部に25の第2
ロードロック、搬送路14を真空状態から窒素やArガ
スの不活性雰囲気9にするための26のリークバルブと
を有している。
Next, in the state shown in FIG.
Is carried. In this step, the inside of the conveying path 14 of FIG. 2 is conveyed. The transfer path 14 includes a vacuum pump 23 for drawing a vacuum in the transfer path 14 and the dry etching apparatus 1.
2 at the connecting portion between the transport path 14 and 2 and 24 second load locks at the connecting portion between the electroless plating apparatus 13 and the transport path 14.
It has a load lock and 26 leak valves for changing the transfer path 14 from a vacuum state to an inert atmosphere 9 of nitrogen or Ar gas.

【0021】具体的には、半導体素子6をドライエッチ
ング装置12より搬送するとき、搬送路14内を真空ポ
ンプ23によって真空状態に保ち、第1ロードロックを
開き半導体素子6をドライエッチング装置12より搬送
する。半導体素子6が搬送路14内に搬送されると、第
1ロードロックを閉じ、リークバルブ26を開き窒素や
Arガスで搬送路14内を充填し、搬送路14と無電解
めっき装置13との気圧差のない状態にし、第2ロード
ロックを開き半導体素子6を無電解めっき装置13に搬
送する。すなわちこの工程では、窒素やArガスにより
1気圧の不活性雰囲気9に制御した環境下で半導体素子
6を酸化雰囲気中を通過することなしに、次の工程に移
るものである。
Specifically, when the semiconductor element 6 is transferred from the dry etching apparatus 12, the inside of the transfer path 14 is kept in a vacuum state by the vacuum pump 23, the first load lock is opened, and the semiconductor element 6 is transferred from the dry etching apparatus 12 to the dry etching apparatus 12. Transport. When the semiconductor element 6 is transferred into the transfer path 14, the first load lock is closed, the leak valve 26 is opened, and the transfer path 14 is filled with nitrogen or Ar gas. With no pressure difference, the second load lock is opened and the semiconductor element 6 is transported to the electroless plating apparatus 13. That is, in this step, the semiconductor element 6 is moved to the next step without passing through the oxidizing atmosphere under the environment in which the inert atmosphere 9 is controlled to 1 atm by nitrogen or Ar gas.

【0022】さらに図3(c)に示すように無電解めっ
き法によりNi膜を形成する。この工程は、図2の無電
解めっき装置13内で行う。そして無電解めっき装置1
3は不活性雰囲気9にするための窒素やArガスのガス
圧や温度を一定に制御する21の管理装置と22のめっ
き室とを有している。
Further, as shown in FIG. 3C, a Ni film is formed by electroless plating. This step is performed in the electroless plating apparatus 13 shown in FIG. And electroless plating apparatus 1
Reference numeral 3 has a management device 21 for controlling the gas pressure and temperature of nitrogen or Ar gas for making the inert atmosphere 9 constant, and a plating chamber 22.

【0023】具体的には、無電解めっき装置13内を窒
素ガスにより1気圧の不活性雰囲気9に制御した環境下
に設置した90℃の無電解Niめっき浴10中で2〜5
分の浸漬によって半導体素子6上のAl電極6の酸化膜
ないAl面11上に0.7〜1.2μmのNi膜8を形成
する。すなわちこの工程においては、半導体素子に無電
解Niめっき浴10に浸漬した直後は酸化膜のないAl
面11と無電解Niめっき液中のNiイオンとの間で置
換反応によるNiの析出反応があり、析出したNi表面
には、無電解Niめっき液中の還元剤の作用によりNi
が自己析出反応を起こしてNi膜7が成長する。以上の
工程までを図2の装置内で行う。
Concretely, 2 to 5 in an electroless Ni plating bath 10 at 90 ° C. installed in an environment in which the inside of the electroless plating apparatus 13 is controlled to an inert atmosphere 9 of 1 atm by nitrogen gas.
A Ni film 8 having a thickness of 0.7 to 1.2 μm is formed on the Al surface 11 of the Al electrode 6 on the semiconductor element 6 which has no oxide film by immersion for a minute. That is, in this step, immediately after the semiconductor element was immersed in the electroless Ni plating bath 10, Al without an oxide film was formed.
There is a Ni precipitation reaction due to a substitution reaction between the surface 11 and Ni ions in the electroless Ni plating solution, and the Ni surface thus deposited is affected by the action of the reducing agent in the electroless Ni plating solution.
Causes an autodeposition reaction to grow the Ni film 7. The above steps are performed in the apparatus shown in FIG.

【0024】次に図2(d)に示すように無電解めっき
法によりAu膜8を形成する。この工程においては、A
l電極1上にはNi膜7を形成しているため、Al電極
1上の自然酸化膜の再形成を完全に防止しているため、
大気中での処理も可能となる。また、Ni膜7が大気中
での酸化による接続性の低下を防止する目的で無電解A
uめっき浴34中でNi膜7上にAu膜8を0.1〜0.
2μm形成する。
Next, as shown in FIG. 2D, an Au film 8 is formed by electroless plating. In this process, A
Since the Ni film 7 is formed on the 1-electrode 1, the re-formation of the natural oxide film on the Al electrode 1 is completely prevented.
Processing in the atmosphere is also possible. In addition, the Ni film 7 is electroless A for the purpose of preventing deterioration of connectivity due to oxidation in the atmosphere.
The Au film 8 is formed on the Ni film 7 in the u plating bath 34 in the range of 0.1 to 0.1.
2 μm is formed.

【0025】以上本実施の形態により、ドライエッチン
グによってAl電極上の自然酸化膜を除去し、不活性雰
囲気に制御した環境下で無電解めっきによって金属膜を
形成することにより、完全に自然酸化膜の形成を防止す
ることができるため、極めて容易にAl電極表面上に密
着性の高い金属膜を形成することができる。
As described above, according to the present embodiment, the natural oxide film on the Al electrode is removed by dry etching, and the metal film is formed by electroless plating in an environment controlled to an inert atmosphere. Since it is possible to prevent the formation of Al, it is possible to extremely easily form a highly adherent metal film on the surface of the Al electrode.

【0026】(実施の形態2)以下本発明実施の形態2
における半導体素子の製造方法について、図面を参照し
ながら説明する。
(Second Embodiment) The second embodiment of the present invention will be described below.
The method of manufacturing the semiconductor element in the above will be described with reference to the drawings.

【0027】図4は本実施の形態における半導体素子の
製造工程を装置に基づいて示した断面図である。
FIG. 4 is a sectional view showing the manufacturing process of the semiconductor device according to the present embodiment based on the apparatus.

【0028】まず図4(a)に示すように、半導体素子
上に形成されたAl電極のドライエッチングを行なう。
このドライエッチング装置は、17の真空ポンプ、18
の電源、19の高周波発生器、Arやフレオンのスパッ
タガス29を吸入するための20の吸入バルブとを有し
ている。
First, as shown in FIG. 4A, the Al electrode formed on the semiconductor element is dry-etched.
This dry etching apparatus includes a vacuum pump 17
Power source, 19 high-frequency generators, and 20 suction valves for sucking Ar or Freon sputter gas 29.

【0029】具体的にはドライエッチング装置の電極2
7に半導体素子6を設置し、真空ポンプ17によりドラ
イエッチング装置12内を真空に引き、吸入バルブ20
よりArやフレオンガスをドライエッチング装置12内
に充填し、電源18の電圧を上げ高周波発生装置19に
よって高周波を掛けながらArやフレオンのスパッタガ
ス29でAl電極1上の自然酸化膜2が完全になくなる
までエッチングを行い、酸化膜のないAl面11を露出
させる。なお、このドライエッチング装置内に半導体素
子を搬送するための、搬送容器30が設置してある。
Specifically, the electrode 2 of the dry etching apparatus
7, the semiconductor element 6 is installed, the inside of the dry etching apparatus 12 is evacuated by the vacuum pump 17, and the suction valve 20
Further, Ar or Freon gas is filled in the dry etching apparatus 12, and the natural oxide film 2 on the Al electrode 1 is completely removed by the Ar or Freon sputter gas 29 while increasing the voltage of the power supply 18 and applying a high frequency by the high frequency generator 19. Etching is performed until the Al surface 11 having no oxide film is exposed. A transport container 30 for transporting the semiconductor element is installed in this dry etching apparatus.

【0030】次に図4(b)に半導体素子6の搬送容器
30への移動工程を示す。ドライエッチング終了後、ド
ライエッチング装置内と搬送容器30を窒素やArガス
で1気圧の不活性雰囲気9にし、半導体素子6を搬送容
器30に移動させ、第1ゲートを閉じ、搬送容器30内
を密閉する。
Next, FIG. 4B shows a step of moving the semiconductor element 6 to the transfer container 30. After the dry etching is completed, the inside of the dry etching apparatus and the transfer container 30 are brought to an inert atmosphere 9 of 1 atm with nitrogen or Ar gas, the semiconductor element 6 is moved to the transfer container 30, the first gate is closed, and the inside of the transfer container 30 is closed. Seal tightly.

【0031】続いて図4(c)に示すように無電解Ni
めっき工程を施す。搬送容器30をドライエッチング装
置より、大気中に設置した無電解Niめっき浴10まで
搬送した後で、無電解Niめっき浴10中で搬送容器3
0の第1ゲート31と第2ゲート32を開け、搬送容器
30内に無電解Niめっき液で充填する。無電解Niめ
っき浴10中で搬送容器30を解放するため、半導体素
子6の酸化膜のないAl表面11は大気中の酸素によっ
て酸化されることなく、90℃の無電解Niめっき浴1
0中で2〜5分の浸漬によって半導体素子6上のAl電
極6の酸化膜ないAl面11上に0.7〜1.2μmのN
i膜7を形成する。
Subsequently, as shown in FIG. 4 (c), electroless Ni
Perform the plating process. After the transport container 30 is transported from the dry etching apparatus to the electroless Ni plating bath 10 installed in the atmosphere, the transport container 3 is transported in the electroless Ni plating bath 10.
The first gate 31 and the second gate 32 of 0 are opened, and the transfer container 30 is filled with the electroless Ni plating solution. Since the transport container 30 is released in the electroless Ni plating bath 10, the oxide-free Al surface 11 of the semiconductor element 6 is not oxidized by oxygen in the atmosphere, and the electroless Ni plating bath 1 at 90 ° C.
By immersing the Al electrode 6 on the semiconductor element 6 in the atmosphere for 2 to 5 minutes, the N-layer of 0.7 to 1.2 μm is formed on the Al surface 11 without the oxide film.
The i film 7 is formed.

【0032】そして図2(d)に示すように無電解Au
めっき工程を施す。この工程においては、Al電極1上
にはNi膜7を形成しているため、Al電極1上の自然
酸化膜の再形成はないため、大気中での処理も可能とな
る。よって、Ni膜7が大気中での酸化による接続性の
低下を防止する目的で無電解Auめっき浴34中でNi
膜7上にAu膜8を0.1〜0.2μm形成する。
Then, as shown in FIG. 2D, electroless Au is used.
Perform the plating process. In this step, since the Ni film 7 is formed on the Al electrode 1, there is no re-formation of the natural oxide film on the Al electrode 1, and therefore the treatment in the atmosphere is possible. Therefore, in order to prevent the Ni film 7 from deteriorating the connectivity due to the oxidation in the atmosphere, the Ni film 7 is Ni in the electroless Au plating bath 34.
An Au film 8 having a thickness of 0.1 to 0.2 μm is formed on the film 7.

【0033】以上より、ドライエッチングによってAl
電極上の自然酸化膜を除去し、不活性雰囲気に制御した
容器で無電解めっき液中まで搬送後、無電解めっきによ
って金属膜を形成することにより、大気中の設置した無
電解めっき浴においても、Al電極表面上に密着性の高
い金属膜を形成することができる。
From the above, Al is formed by dry etching.
By removing the natural oxide film on the electrode and transporting it to the electroless plating solution in a container controlled to an inert atmosphere, and then forming a metal film by electroless plating, even in an electroless plating bath installed in the atmosphere , A metal film having high adhesiveness can be formed on the surface of the Al electrode.

【0034】さらに、本実施の形態によれば、ドライエ
ッチングの施された半導体装置を搬送容器を用いて搬送
しているため、めっきを行なう装置そのものは従来使用
されているものを用いることができ、上記した実施の形
態1の場合のように、ドライエッチング装置とめっき装
置とを融合化した新たな装置を作成する必要性はない。
Further, according to the present embodiment, since the semiconductor device which has been dry-etched is transported by using the transport container, the plating apparatus itself can be a conventionally used one. It is not necessary to create a new device in which the dry etching device and the plating device are integrated as in the case of the above-described first embodiment.

【0035】なお、上記の実施の形態1及び2におい
て、無電解めっき工程においてAl電極1上にNi膜7
を形成したが、Ni膜7はCu膜、Pd膜、Au膜とし
てもよい。
In the first and second embodiments, the Ni film 7 is formed on the Al electrode 1 in the electroless plating process.
However, the Ni film 7 may be a Cu film, a Pd film, or an Au film.

【0036】[0036]

【発明の効果】本発明は、ドライエッチングによりAl
電極上の自然酸化膜を均一に除去し、不活性雰囲気中で
ドライエッチング後のめっき工程を処理することで、A
l電極の自然酸化膜の再形成を完全に防止し、自然酸化
膜の形成防止のためのZn粒子膜3形成等の処理が必要
なくなる。このことにより、密着性が良く、接続性の高
い無電解めっきによる電極を形成することができる。
According to the present invention, Al is formed by dry etching.
By removing the native oxide film on the electrode uniformly and treating the plating process after dry etching in an inert atmosphere,
The re-formation of the natural oxide film of the l-electrode is completely prevented, and the process for forming the Zn particle film 3 for preventing the formation of the natural oxide film becomes unnecessary. This makes it possible to form an electrode by electroless plating having good adhesion and high connectivity.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態における半導体素子の断面
FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【図2】本発明の実施の形態における半導体素子を製造
する装置の概略図
FIG. 2 is a schematic diagram of an apparatus for manufacturing a semiconductor device according to an embodiment of the present invention.

【図3】本発明の実施の形態における半導体素子の製造
工程断面図
FIG. 3 is a sectional view of a semiconductor element manufacturing process in the embodiment of the present invention.

【図4】本発明の実施の形態における半導体素子の製造
工程断面図
FIG. 4 is a sectional view of a semiconductor element manufacturing process in the embodiment of the present invention.

【図5】従来の半導体素子の断面図FIG. 5 is a sectional view of a conventional semiconductor device.

【図6】従来の無電解めっき法による半導体素子の製造
工程断面図
FIG. 6 is a sectional view of a manufacturing process of a semiconductor element by a conventional electroless plating method.

【符号の説明】[Explanation of symbols]

1 Al電極 2 自然酸化膜 3 Zn粒子膜 4 Ni膜 5 Au膜 6 半導体素子 7 Ni膜 8 Au膜 9 不活性雰囲気 10 無電解Niめっき浴 11 酸化膜のないAl表面 12 ドライエッチング装置 13 無電解めっき装置 14 搬送路 17 真空ポンプ 18 電源 19 高周波発生装置 20 吸入バルブ 21 管理装置 22 めっき室 23 真空ポンプ 24 第1ロードロック 25 第2ロードロック 26 リークバルブ 27 電極 28 保護膜 29 スパッタガス 30 搬送容器 31 第1ゲート 32 第2ゲート 33 シリコン酸化膜 34 無電解Auめっき浴 1 Al electrode 2 Natural oxide film 3 Zn particle film 4 Ni film 5 Au film 6 Semiconductor element 7 Ni film 8 Au film 9 Inert atmosphere 10 Electroless Ni plating bath 11 Al surface without oxide film 12 Dry etching device 13 Electroless Plating device 14 Transport path 17 Vacuum pump 18 Power supply 19 High frequency generator 20 Intake valve 21 Management device 22 Plating chamber 23 Vacuum pump 24 First load lock 25 Second load lock 26 Leak valve 27 Electrode 28 Protective film 29 Sputter gas 30 Transport container 31 First Gate 32 Second Gate 33 Silicon Oxide Film 34 Electroless Au Plating Bath

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/92 604D 604Z 604E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/92 604D 604Z 604E

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】半導体素子上に形成されたAl電極表面に
存在する自然酸化膜をドライエッチングにより除去する
工程と、前記自然酸化膜の除去された前記Al電極を有
する半導体素子を不活性雰囲気環境下で搬送する工程
と、前記搬送の後不活性雰囲気環境下で前記半導体素子
の前記Al電極表面に無電解めっき法により金属膜を析
出させる工程とを有する半導体素子の製造方法。
1. A step of removing a natural oxide film existing on the surface of an Al electrode formed on a semiconductor element by dry etching, and a semiconductor element having the Al electrode from which the natural oxide film is removed, in an inert atmosphere environment. A method of manufacturing a semiconductor device, which comprises a step of transporting the semiconductor element below, and a step of depositing a metal film on the surface of the Al electrode of the semiconductor element by an electroless plating method in the inert atmosphere environment after the transport.
【請求項2】半導体素子上に形成されたAl電極表面に
存在する自然酸化膜を除去するドライエッチング手段
と、不活性雰囲気環境下で前記半導体素子における前記
自然酸化膜の除去された前記Al電極表面に無電解めっ
き法により金属膜を析出させる手段と、前記ドライエッ
チング手段から前記金属膜を析出させる手段へ前記半導
体素子を不活性雰囲気環境下で搬送する手段とを有する
半導体素子の製造装置。
2. A dry etching means for removing a natural oxide film existing on the surface of an Al electrode formed on a semiconductor element, and the Al electrode from which the natural oxide film is removed in the semiconductor element under an inert atmosphere environment. An apparatus for manufacturing a semiconductor element, comprising: a means for depositing a metal film on the surface by electroless plating; and a means for transporting the semiconductor element from the dry etching means to the means for depositing the metal film in an inert atmosphere environment.
JP11758996A 1996-05-13 1996-05-13 Semiconductor device manufacturing method and manufacturing apparatus Expired - Fee Related JP3334489B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11758996A JP3334489B2 (en) 1996-05-13 1996-05-13 Semiconductor device manufacturing method and manufacturing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11758996A JP3334489B2 (en) 1996-05-13 1996-05-13 Semiconductor device manufacturing method and manufacturing apparatus

Publications (2)

Publication Number Publication Date
JPH09306871A true JPH09306871A (en) 1997-11-28
JP3334489B2 JP3334489B2 (en) 2002-10-15

Family

ID=14715566

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11758996A Expired - Fee Related JP3334489B2 (en) 1996-05-13 1996-05-13 Semiconductor device manufacturing method and manufacturing apparatus

Country Status (1)

Country Link
JP (1) JP3334489B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1030356A2 (en) * 1999-02-16 2000-08-23 Sharp Kabushiki Kaisha Process of fabricating semiconductor device
JP2007103859A (en) * 2005-10-07 2007-04-19 Nec Electronics Corp Electronic circuit chip, electronic circuit device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1030356A2 (en) * 1999-02-16 2000-08-23 Sharp Kabushiki Kaisha Process of fabricating semiconductor device
EP1030356A3 (en) * 1999-02-16 2002-11-20 Sharp Kabushiki Kaisha Process of fabricating semiconductor device
JP2007103859A (en) * 2005-10-07 2007-04-19 Nec Electronics Corp Electronic circuit chip, electronic circuit device and manufacturing method thereof

Also Published As

Publication number Publication date
JP3334489B2 (en) 2002-10-15

Similar Documents

Publication Publication Date Title
US6396148B1 (en) Electroless metal connection structures and methods
US3761309A (en) Ctor components into housings method of producing soft solderable contacts for installing semicondu
US5683940A (en) Method of depositing a reflow SiO2 film
JP4239310B2 (en) Manufacturing method of semiconductor device
US6933614B2 (en) Integrated circuit die having a copper contact and method therefor
US4600600A (en) Method for the galvanic manufacture of metallic bump-like lead contacts
JP5487473B2 (en) Wiring board and manufacturing method thereof
US7294217B2 (en) Electrical interconnect structures for integrated circuits and methods of manufacturing the same
KR101094125B1 (en) Methods and systems for low interfacial oxide contact between barrier and copper metallization
KR20090092332A (en) Methods and systems for barrier layer surface passivation
JP3373499B2 (en) Semiconductor device manufacturing method and semiconductor device manufacturing apparatus
JPH11307481A (en) Equipment and method of electroplating
EP1388167B1 (en) Method of removing oxide from copper bond pads
JP3483490B2 (en) Method for manufacturing semiconductor device
JP3334489B2 (en) Semiconductor device manufacturing method and manufacturing apparatus
US7067423B2 (en) Electroless plating apparatus, semiconductor wafer having bumps, semiconductor chip having bumps, methods of manufacturing the semiconductor wafer and the semiconductor chip, semiconductor device, circuit board, and electronic equipment
JP3274381B2 (en) Method for forming bump electrode of semiconductor device
JP3038953B2 (en) Wiring formation method
KR100351237B1 (en) Apparatus for forming a copper wiring in a semiconducotr device and method of forming a copper wiring by utilaing the same
JP2002093837A (en) Method of manufacturing semiconductor device
JP2003035962A (en) Substrate treatment method and system
JPH10125682A (en) Electrode forming method of semiconductor element
JPH05251511A (en) Production of copper/polyimide laminate structure
JP2000309896A (en) Electroplating method
JPS62291123A (en) Semiconductor device and manufacture thereof

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070802

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080802

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080802

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090802

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090802

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100802

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110802

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110802

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120802

Year of fee payment: 10

LAPS Cancellation because of no payment of annual fees