JPH09305573A - Fft operation device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform fast Fourier transform(FFT) operation at high speed. SOLUTION: A butterfly computing element 4 executes butterfly operation of data inputted from terminals in0 and in1 and outputs two pieces of data provided as a result from a terminal out0 or out1 to both selectors 13-0 and 13-1. At the selector 13-0 or 13-1, any one of two pieces of data supplied from the terminals outO and out1 are selected so that two pieces of data to be simultaneously required for the next butterfly operation can be dividedly stored in memories 15-0 and 15-1, and the data are respectively simultaneously supplied and stored through a selector 14-0 or 14-1 into the memory 15-0 or 15-1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FFT operation device and method, and more particularly to an FFT that enables higher speed.
The present invention relates to a computing device and method.

[0002]

2. Description of the Related Art Recently, digitization is becoming widespread in broadcasting technology. FIG. 9 shows a DAB, which is one of digital radio broadcasts for digitizing and broadcasting audio signals.
It shows a configuration example of a (Digital Audio Broadcasting) receiver. The tuner 92 receives a signal of a predetermined broadcasting station (channel) from the signal received via the antenna 91, and outputs it to the A / D converter 93. A / D converter 9
3 performs A / D conversion of the input signal, and FFT (Fast F
Ourier Transform) circuit 94 performs an FFT operation in order to convert the data on the time axis input from A / D converter 93 into the data on the frequency axis of a plurality of subcarriers. The FFT circuit 94 is supplied with the symbol component after the guard interval component provided between the adjacent symbols on the time axis is removed.

Deinterleave circuit and error correction circuit 9
Reference numeral 5 performs deinterleave processing and error correction processing on the output of the FFT circuit 94. A part of the signal processed by the deinterleave circuit and the error correction circuit 95 is supplied to the decoding circuit 96, and the DQP
SK (Differential Quadrature Phase Shift Keying)
The demodulated left channel audio signal and right channel audio signal are output from the speakers 97 and 98, respectively. Further, the additional data output circuit 99 separates and outputs additional data such as program content and traffic information from the signal output from the deinterleave circuit and the error correction circuit 95.

FIG. 10 shows a conventional configuration example of such an FFT circuit 94. In this example, the input data is once stored in the input buffer 1 and then input to the input terminal in0 or in1 of the butterfly computing unit 4 via the selector 2 and the selector 3. The butterfly computing unit 4 is, for example, a butterfly computing unit having a radix of 2 (two-point DFT (Discrete Fourier Transfor
m)), a ROM (Read Only Memory) 5
The rotation operator data (twirling factor) stored in is properly read out, the butterfly operation is performed on the data input from the terminals in0 and in1, and the terminals out0 and out are output.
It is designed to output from 1.

The selector 6 selects the data output from the terminals out0 and out1 of the butterfly computing unit 4 and outputs it to the selector 7. The selector 7 outputs the data input from the selector 6 to the memory 8 or the output buffer 9. The memory 8 stores the data input from the selector 7, reads the data at a predetermined timing, and supplies the data to the selector 2.

The selector 2 selects the output from the input buffer 1 until all the data constituting the processing unit of the butterfly operation is selected from the input buffer 1, and all the data to be subjected to the butterfly operation is input from the input buffer 1. After input, select the data input from the memory 8,
The data is output to the selector 3. In this way, the butterfly computing unit 4 repeatedly executes the butterfly computing process on the butterfly computing result a predetermined number of times.

For example, as shown in the timing chart of FIG. 11, it is assumed that data 0 (butterfly operation result) is output from the terminal out0 of the butterfly operation unit 4 and data 1 (butterfly operation result) is output from the terminal out1. Then, the selector 6 operates with a clock having a half cycle of the output cycle of the butterfly computing unit 4, so that in the first half period of the output cycle of the butterfly computing unit 4, the selector 6 outputs the signal from the terminal out0. The selected data 0 is selected, and in the latter half period, the data 1 output from the terminal out1 is selected. This data 0 and data 1
Is selected by the selector 7 and supplied to the memory 8,
Written. That is, the two butterfly operation results output simultaneously by the butterfly operation unit 4 are parallel / serial converted by the selector 6 and supplied to the memory 8 via the selector 7 to be stored therein. The data stored in the memory 8 is read again and supplied to the terminals in0 and in1 of the butterfly computing unit 4 via the selectors 2 and 3.

That is, as shown in FIG. 11, writing and reading of data with respect to the memory 8 are performed at a cycle of 1/2 of the switching cycle of the selector 6. For example, when the data 0 is output from the selector 6, the data 0 is written in the memory 8 in the first half period, the data already stored in the memory 8 is read in the second half period, and the selector 2 Is input to, for example, the terminal in0 of the butterfly computing unit 4 via the selector 3.

Further, in the cycle in which the selector 6 outputs the data 1, the data 1 is output in the first half period.
Is written in the memory 8, and in the latter half period, predetermined data already stored in the memory 8 is read out and supplied to, for example, the terminal in1 of the butterfly computing unit 4 via the selectors 2 and 3.

Thereafter, similar processing is repeatedly executed.

[0011]

As described above, the conventional F
In the FT operation device (here, the FFT circuit 94), assuming that the frequency of the operation clock of the butterfly operation unit 4 is 1, as shown in FIG. 11, the frequency of the operation clock of the memory 8 is four times that frequency. And need to. In other words, assuming that the operation clock of the memory 8 is fixed, the operation in the butterfly operation unit 4 must be performed at a speed of 1/4 of the clock, which is one of the causes of hindering the speeding up of the operation. Was becoming.

The present invention has been made in view of such a situation, and makes it possible to perform a higher-speed operation.

[0013]

An FFT according to claim 1
The arithmetic unit is provided with an arithmetic means for performing a butterfly operation of a predetermined radix N and N storage means for storing data related to the butterfly operation, and simultaneously writes or reads data to or from the N storage means. And

According to a seventh aspect of the present invention, the FFT calculation method is characterized in that data is written in or read from N storage means at the same time.

In the FFT operation device according to the first aspect and the FFT operation method according to the seventh aspect, writing or reading of data to / from N storage means is performed simultaneously.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but before that, in order to clarify the correspondence between each means of the invention described in the claims and the following embodiments. The features of the present invention are described as follows by adding a corresponding embodiment (however, an example) in parentheses after each means.

That is, the FFT operation device according to the first aspect is an FF that performs an FFT (Fast Fourier Transform) operation.
A computing unit that is a T computing device and performs a butterfly computation of a predetermined radix N (for example, the butterfly computing unit 4 shown in FIGS. 2, 4 to 6, and 8 and the butterfly computing unit 54 shown in FIG. 7). And N storage means (for example, the memory 15-0 shown in FIG. 2) for storing data related to butterfly computation.
And 15-1, the input buffers 22-0 and 22-1 shown in FIG. 4, the output buffers 32-0 and 32-1 shown in FIG. 5, the memories 15-0 and 15-1 shown in FIG. 6, and the input buffer 22. -0, 22-1, output buffer 32-0,
And 32-1, the input buffers 52-0 to 52-3 shown in FIG. 7, the memories 58-0 to 58-3, and the output buffers 59-0 to 59-3, and the input buffer unit 71-0 shown in FIG. 71-1, memory units 72-0, 72-1,
Output buffer units 73-0 and 73-1) and write or read data to and from N storage means at the same time.

In the FFT operation device according to the sixth aspect, each of the N storage means has first and second storage means for storing data (for example, the input buffer 71- shown in FIG. 8).
0-2 and 71-0-3 and the input buffer 71-1-
2 and 71-1-3, memories 72-0-2 and 72
0-3, memories 72-1-2 and 72-1-3, output buffers 73-0-2 and 73-0-3, output buffers 73-1-2 and 73-1-3, etc. , While one of the first and second storage means is being written, the other is read.

According to a seventh aspect of the present invention, the FFT calculation method is a calculation means for performing a butterfly calculation of a predetermined radix N (for example, the butterfly calculation unit 4 shown in FIGS. 2, 4 to 6, and 8;
7 and the N storage means (for example, the memories 15-0 and 15-1 shown in FIG. 2) and the input buffer 22-0 shown in FIG. 22-1, output buffers 32-0 and 32-1 shown in FIG. 5, memories 15-0 and 15-1 shown in FIG. 6, and input buffers 22-0 and 22.
-1, output buffers 32-0 and 32-1, input buffers 52-0 to 52-3 shown in FIG. 7, memory 58-
0 to 58-3 and output buffers 59-0 to 59-3
-3, the input buffer units 71-0 and 71-1 shown in FIG.
Memory units 72-0 and 72-1 and output buffer unit 73-
0, and 73-1), and FFT (Fast Fou
An FFT calculation method of an FFT calculation device that performs a carrier transform), characterized in that writing or reading of data to N storage means is performed simultaneously.

Of course, this description does not mean that each means is limited to those described above.

Next, the basic principle of the present invention will be described. In the FFT butterfly operation, the radix is N
Then, one butterfly operation is performed on N pieces of input data, and N pieces of data obtained as a result of the butterfly operation are also obtained. Therefore, the input buffer that stores the first input data, the memory that stores the intermediate result of the butterfly operation, or the output buffer that stores the final result of the butterfly operation (hereinafter, these input buffers, memory, and If there is one output buffer (collectively referred to as a storage unit), it is necessary to perform butterfly calculation after reading data N times from the storage unit and to write the butterfly calculation result to the storage unit N times. Therefore, as described above, the speedup of the FFT calculation is hindered.

Therefore, in the present invention, when performing a radix-N butterfly operation, N storage units are prepared, and data is read from each of the N storage units simultaneously (in parallel) to perform the butterfly operation. , And the resulting N
Each of the butterfly calculation results is stored in N storage units.
Write at the same time (in parallel) so that FF
It is designed to speed up the T calculation.

Next, a method of arranging N storage units for simultaneously writing or reading N pieces of data in the N storage units as described above will be described with reference to FIG.

Incidentally, FIG. 1 shows the time thinning method (Cool
The signal flow in the case of performing 8-point FFT by the y-Tukey method) is shown. Also, in the figure, I0
Through I7, M0 through M7, or O0 through O7 represent addresses of the input buffer, the memory, or the output buffer. Further, in the figure, the BTF has a radix of 2
Represents the butterfly computation of. Therefore, two storage units are provided. That is, input buffers IB0 and IB1 are provided as input buffers, memories MEM0 and MEM1 are provided as memories, and output buffers OB0 and OB1 are provided as output buffers.

Now, eight input data to be subjected to FFT are time-sequentially i0 to i7, and the input data are F
The output data (final butterfly calculation result) obtained by FT is output from low frequency components o0 to o7.
And input data i0 to i7
Are input to the addresses I0 to I7, respectively, and the output data o0 to o7 are output from the addresses O0 to O7, respectively.

Then, as shown in FIG. 1A, it is assumed that input buffers IB0 and IB1, memories MEM0 and MEM1 or output buffers OB0 and OB1 are provided separately in the upper and lower parts of the signal flow.

In this case, the input data i0 to i7 are respectively stored in the addresses I0 to I3 of the input buffer IB0 or the addresses I4 to I7 of the input buffer IB1 and further read from each of them to be arranged in a so-called bit reverse order. After being replaced, the first butterfly operation is performed. The result of the first butterfly operation is stored in the memories MEM0 and MEM1 and further read from the memory MEM0 and MEM1 to perform the second butterfly operation,
The result of the calculation is again the memories MEM0 and MEM1.
Is stored. Then, this second butterfly operation result is read from the memories MEM0 and MEM1,
After the third butterfly operation, the output buffer O
Stored in B0 and OB1.

Now, as shown in FIG. 1A, when the input buffers IB0 and IB1, the memories MEM0 and MEM1 or the output buffers OB0 and OB1 are respectively arranged, the two input data to be subjected to the first butterfly operation are arranged. Are addresses I0 and I4, I1 and I5, I2 and I6,
Alternatively, since they are separately stored in I3 and I7, that is, because they are separately stored in the input buffer IB0 and the input buffer IB1, they can be read out at the same time and the butterfly operation can be performed. The two output data obtained as a result of the last butterfly operation (third butterfly operation) are separately supplied to the addresses O0 and O4, O1 and O5, O2 and O6, or O3 and O7. , The output buffers OB0 and OB1 are separately supplied, so that they can be stored (written) at the same time.

However, in this case, the two data to be subjected to the butterfly operation are both stored in the memory MEM.
Since it is stored in either 0 or MEM1, that is, for example, two pieces of data to be subjected to the second butterfly operation are the addresses M0 and M2 of the memory MEM0, the addresses M1 and M3 of the memory MEM0, and the memory MEM1. These two data cannot be read at the same time for the butterfly operation because they are stored at the addresses M4 and M6 or the addresses M5 and M7 of the memory MEM1, respectively.

Further, in this case, in the memories MEM0 and MEM1, 2 obtained as a result of the butterfly operation.
Each of the two pieces of data is stored at the original address where the two pieces of data read out for performing the butterfly operation were stored. That is, for example, the address M0
The two data obtained as a result of the second butterfly operation using the two data read from M and M2 are stored in the original addresses M0 and M2. The two data obtained as a result of the second butterfly operation using the two data read from the addresses M1 and M3 are stored in the original addresses M1 and M3. Hereinafter, similarly, the data read from the addresses M4 to M7 are also stored in the original addresses M4 to M7 after the second butterfly operation.

Therefore, 2 obtained as a result of the butterfly operation
Data cannot be written at the same time.

Therefore, for example, as shown in FIG. 1B, addresses M0, M3, M5, and M6 are arranged in the memory MEM0, and addresses M1, M2, M4, and M7 are arranged in the memory MEM1. To do so.

In this case, the target of the butterfly operation is 2
One piece of data is stored separately in the memories MEM0 and MEM1, that is, for example, the two pieces of data to be subjected to the second butterfly operation are the addresses M0 of the memory MEM0.
And memory MMEM1 address M2, memory MEM1 address M1 and memory MEM0 address M3, memory M
Address M4 of EM1 and address M of memory MEM0
6, or the address M5 of the memory MEM0 and the memory ME
These two data can be read at the same time, which are respectively stored in M7 of M1 and used for the butterfly operation.

Further, as described above, in the memories MEM0 and MEM1, each of the two data obtained as a result of the butterfly operation is the address at which the two data read for performing the butterfly operation are stored. Address), the two data obtained as a result of the butterfly operation can be written at the same time.

Therefore, only by performing the address control as described with reference to FIG. 1B, it is possible to speed up the FFT calculation by the same procedure as the conventional one and without increasing the capacity of the storage section. it can.

The embodiments described below are based on the above principle.

FIG. 2 shows the configuration of the first embodiment of the FFT operation device to which the present invention is applied. In addition, in FIG.
The same reference numerals are given to the portions corresponding to the case in 1, and the description thereof will be omitted below as appropriate.

The selector 10 is adapted to supply the input data, which is the object of the FFT, to either the selector 12-0 or 12-1. Selector 11-0
Alternatively, 11-1 selects one of the outputs of the memory 15-0 or 15-1 and selects the selector 12-0.
Or 12-1 is supplied respectively. In the selector 11-0, the memory 15-0
Alternatively, when one of the outputs of 15-1 is selected, the other of them is selected in the selector 11-1.

The selector 12-0 selects one of the outputs of the selector 10 or 11-0 and supplies it to the terminal in0 of the butterfly computing unit 4. The selector 12-1 is the selector 10 or 11-1.
One of the outputs of the above is selected and supplied to the terminal in1 of the butterfly computing unit 4.

The selector 13-0 or 13-1 selects the data output from one of the terminals out0 or out1 of the butterfly computing unit 4 and supplies it to the selector 14-0 or 14-1, respectively. Has been done. In the selector 13-0, the terminal o
When either one of the outputs ut0 and out1 is selected, the other of them is selected in the selector 13-1. As a result, the data output from the terminal out0 is stored in any of the memories 15-0 or 15-1 described later, and similarly, the data output from the terminal out1 is also stored in the memory 15-0 or the memory 15-0. It can be stored in any of 15-1.

The selector 14-0 or 14-1 outputs the output of the selector 13-0 or 13-1 to the memory 15-0.
Alternatively, it is supplied to 15-1 respectively or to the selector 16. Memory 15-
0 or 15-1 is the selector 14-0 or 14-1
The data supplied from the respective devices are stored, and the stored data are supplied to both the selectors 11-0 and 11-1. The selector 16 selects one of the outputs of the selector 14-0 or 14-1 and outputs it.

Next, the operation will be described. The input data is supplied to either one of the selectors 12-0 or 12-1 in the selector 10, and further,
From the selector 12-0 or 12-1, it is input to the terminal in0 or in1 of the butterfly computing unit 4, respectively. The butterfly computing unit 4 performs a butterfly computation on the data input from the terminals in0 and in1, and outputs two resulting data to the terminal out0 or out1.
From each, it outputs to both selectors 13-0 and 13-1.

In the selector 13-0 or 13-1, two pieces of data required at the same time for the next butterfly operation are
The terminals out0 and out1 of the butterfly computing unit 4 are separately stored in the memories 15-0 and 15-1.
Any one of the two data supplied from is selected and supplied to the memory 15-0 or 15-1 via the selector 14-0 or 14-1. The memory 15-0 or 15-1 simultaneously stores the data supplied via the selector 14-0 or 14-1. Therefore, the two data output from the terminals out0 and out1 of the butterfly computing unit 4 are stored in the memories 15-0 and 15-1 without any waiting time.

Two pieces of data, which are separately stored in the memories 15-0 and 15-1 and are to be subjected to the next butterfly operation, are simultaneously read from each of them at a predetermined timing, and the selectors 11-0 and 11-1 is supplied.

The selector 11-0 or 11-1 selects one of the data read from the memory 15-0 or 15-1 to be input to the terminal in0 or in1 of the butterfly computing unit 4, and the selector Output to 12-0 or 12-1 respectively. The selector 12-0 or 12-1 selects the output of the selector 10 until all the input data forming the processing unit of the butterfly operation is supplied from the selector 10, and the butterfly operation unit 4
Are supplied to the terminals in0 and in1 respectively.

Then, the selector 12-0 or 12-1
After all the input data to be subjected to the butterfly operation are supplied from the selector 10, the data supplied from the selector 11-0 or 11-1 is selected and supplied to the terminal in0 or in1 of the butterfly operation unit 4, respectively. To do.
Therefore, in this case, the data read simultaneously from the memories 15-0 or 15-1 are simultaneously supplied to the butterfly computing unit 4, and as a result, the butterfly computing unit 4
Then, the butterfly operation can be performed immediately.

In this way, the butterfly computing unit 4 repeatedly executes the butterfly computation on the butterfly computation result a predetermined number of times.

When the butterfly operation processing is performed a predetermined number of times, that is, when the final butterfly operation result is obtained, thereafter, the selector 13-0 or the selector 13-0 in the selector 14-0. Or 13-1
The data (final butterfly operation result) supplied from each is supplied to the selector 16. Selector 16
Then, the outputs of the selectors 14-0 and 14-1, that is,
Two data output simultaneously from the terminals out0 or out1 of the butterfly computing unit 4 are
Serial converted and output.

FFT for performing FFT operation as described above
In the arithmetic unit, the selectors 13-0, 13-1, 14-
0 and 14-1 operate at the same clock as the clock of the butterfly computing unit 4, whereby the memory 15-0
And 15-1 are supplied with the butterfly operation result by the butterfly operation unit 4 at such clock timing.

That is, as shown in the timing chart of FIG. 3, when data 0 and data 1 are output from the terminals out0 and out1 of the butterfly computing unit 4, respectively, the selector 13-0 or 13-1 operates as a butterfly. With the same clock as the clock of the arithmetic unit 4, one or the other of them is simultaneously selected.

In the embodiment shown in FIG. 3, the selector 13-
0, the data 0 and 2 output from the terminal out0
Is selected, and the terminal out1 is selected in the selector 13-1.
Although the data 1 and 3 output from are selected, the data numbers attached to the drawing are attached to identify the data for convenience of explanation. The output of the container 4 is the selectors 13-0 and 13
In -1, it does not represent how it is actually selected.

The data selected by the selector 13-0 or 13-1 is simultaneously supplied to the memory 15-0 or 15-1 via the selector 14-0 or 14-1, respectively. The memory 15-0 or 15-1 stores the data from each of the selectors 13-0 or 13-1 at the same time with a clock having a half cycle of the clock of the butterfly computing unit 4, or has already stored it. The data is read simultaneously and supplied to the selectors 11-0 and 11-1.

That is, the memory 15-0 or 15-1 is
When data 0 or 1 is output from the selector 13-0 or 13-1, respectively, the butterfly computing unit 4
In the first half of the clock cycle, the data 0 or 1 is stored simultaneously, and in the second half, the data required for the next butterfly operation are read out simultaneously and supplied to the selectors 11-0 and 11-1. Similarly, when the data 2 or 3 is output from the selector 13-0 or 13-1, respectively, the data 2 or 3 is simultaneously stored in the first half, and is required for the butterfly operation next in the latter half. Data is read at the same time.

As described above, in this embodiment, since the writing and reading of data with respect to the memories 15-0 and 15-1 are simultaneously performed, as is apparent from the timing chart of FIG. When the operating clocks of 15-0 and 15-1 are set to 1, the operating clock of the butterfly computing unit 4 can operate with a clock having a frequency of 1/2 thereof. Therefore, simply in FIG.
The speed can be doubled compared to the case shown in FIG.

Although the input buffer 1 and the output buffer 9 shown in FIG. 10 are omitted in the embodiment shown in FIG. 2, the input buffer 1 and the output buffer 9 may be used. good.

FIG. 4 shows the configuration of the second embodiment of the FFT operation device to which the present invention is applied. It should be noted that in the figure, portions corresponding to those in FIG. 2 or FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

The selector 21 is adapted to supply the input data, which is the object of the FFT, to either the input buffer 22-0 or 22-1. The input buffer 22-0 or 22-1 stores the input data supplied from the selector 21 and simultaneously reads the already stored input data to select the selector 12-0 or 12-.
1 is supplied to each.

In this embodiment, the selector 12-0
In addition to the input data, the data read from the memory 8 is also supplied to the input buffers 12 and 12-1. In the selector 12-0 or 12-1, the input buffer 22
Either the input data read out from −0 or 22-1 or the data supplied from the memory 8 is selected and supplied to the butterfly computing unit 4.

In this embodiment, the input data is selected by the selector 21, so that the two input data to be subjected to the first butterfly operation are separately supplied to the input buffers 22-0 and 22-1. It Therefore,
In this case, two pieces of input data to be subjected to the butterfly operation are separately stored in the input buffers 22-0 and 22-1.

As described above, the input buffers 22-0 and 22
The two input data to be subjected to the butterfly operation, which are stored separately as −1 and −1, are simultaneously read out from the respective input data, and are input through the selector 12-0 or 12-1 to the terminal in0 or in1 of the butterfly operation unit 4. Is supplied to each.

Therefore, in this case, there is no waiting time required for aligning the two input data to be subjected to the butterfly operation. That is, in the case shown in FIG. 10, in the butterfly computing unit 4, after either one of the two input data to be subjected to the butterfly computing is supplied from the input buffer 1 via the selectors 2 and 3. ,further,
Although it is necessary to wait for the other input data to be supplied from the input buffer 1 via the selectors 2 and 3 to perform the butterfly operation, in this embodiment, the two input data are input to the input buffer 22. Since it is simultaneously read from −0 and 22-1, it is not necessary to wait for such a waiting time. As a result, the processing speed can be increased.

FIG. 5 shows the configuration of the third embodiment of the FFT operation device to which the present invention is applied. It should be noted that in the figure, portions corresponding to those in FIG. 2 or FIG. 10 are denoted by the same reference numerals, and description thereof will be omitted below as appropriate.

In this embodiment, the selector 14-0
One of the two outputs 14 and 14-1 (the output that has been supplied to the memories 15-0 and 15-1 in FIG. 2) is supplied to the selector 31. , The selector 31 selects the output of each of the selectors 14-0 or 14-1 at the timing of a clock having a half cycle of the clock of the butterfly computing unit 4, and supplies it to the memory 8 for storage. ing.

The other of the two outputs of the selectors 14-0 and 14-1 (the selector 16 in FIG. 2).
Output supplied to the output buffer 32-0 or 32-1 is supplied to the output buffer 32-0 or 32-1. The outputs of -1 are stored simultaneously. Further, the output buffers 32-0 and 32-1 are configured to read the stored data (final result of the butterfly operation) and supply it to the selector 33. The selector 33 is similar to the selector 16 in FIG.
The output 2-1 is parallel / serial converted and output.

In this embodiment, the output of the butterfly computing unit 4 is passed through the selectors 13-0 and 13-1 and the selectors 14-0 and 14-1 until the final butterfly computing result is obtained. , Is supplied to the selector 31, and further supplied from the selector 31 to the memory 8 and stored therein. Then, the data stored in the memory 8 is input to the butterfly computing unit 4 via the selectors 2 and 3, and the process of performing the butterfly computation on the data is repeated.

Then, when the butterfly computing unit 4 obtains two pieces of data as the final butterfly computing result, the selectors 13-0, 13-1, and 1 respectively.
Output buffer 32-0 via 4-0 and 14-1 as appropriate
Alternatively, it is simultaneously supplied and stored in 32-1. The data stored in the output buffer 32-0 or 32-1 is read simultaneously, for example, and the selector 33
It is parallel / serial converted and output.

Therefore, in this case, the butterfly calculator 4 can output the two data obtained as the final result of the butterfly calculation without waiting time.
That is, in the case shown in FIG. 10, since the two data output from the butterfly computing unit 4 via the selectors 6 and 7 are serial data, the previously output data is supplied to the output buffer 9. It is necessary to wait for the data to be stored in the output buffer 9 and store the data output later in the output buffer 9 in the present embodiment.
Since one input data is written to the output buffers 32-0 and 32-1 at the same time, it is not necessary to wait for such a waiting time. As a result, the processing speed can be increased (in other words, the output buffers 32-0 and 32-1).
Is the clock of the output buffer 9 of FIG.
A clock with a frequency of / 2 is fine).

FIG. 6 shows the configuration of a fourth embodiment of the FFT operation device to which the present invention is applied. In addition, in FIG.
The parts corresponding to those in FIG. 4 or FIG. 5 are designated by the same reference numerals. That is, this embodiment has a configuration in which the embodiments of FIGS. 2, 4 and 5 are combined. Therefore, this FFT operation device has all the effects of these embodiments and can perform the butterfly operation at the highest speed.

Next, FIG. 7 shows the configuration of a fifth embodiment of the FFT operation device to which the present invention is applied. This embodiment has the same basic configuration as that of the fourth embodiment of FIG. 6 and is different only in that a butterfly operation whose base is 4 is performed.

That is, the selector 51 of FIG. 7 corresponds to the selector 21 of FIG. 6, and corresponds to the input buffers 52-0 to 52-5 of FIG.
2-3 are input buffers 22-0 and 22-1 of FIG.
It corresponds to. In addition, the selectors 53-0 to 53 of FIG.
Reference numeral 3-3 corresponds to the selectors 12-0 and 12-1 in FIG. 6, and the butterfly computing unit 54 in FIG. 7 corresponds to the butterfly computing unit 4 in FIG. Furthermore, the ROM 45 of FIG.
Corresponds to the ROM 5 of FIG. 6 and corresponds to the selector 56-0 of FIG.
To 56-3 are selectors 13-0 and 13- of FIG.
Corresponds to 1. Further, the selectors 57-0 to 57-3 of FIG. 7 correspond to the selectors 14-0 and 14-1 of FIG. 6, and the memories 58-0 to 58-3 of FIG. 7 are the memories 15-0 of FIG. And 15-1. Further, the output buffers 59-0 to 59-3 shown in FIG.
7 corresponding to the output buffers 32-0 and 32-1 of FIG.
The selectors 60-0 to 60-3 of FIG.
Corresponding to 1-0 and 11-1. The selector 61 of FIG. 7 corresponds to the selector 33 of FIG.

In the FFT operation device configured as described above, the selector 51 supplies input data in units of four, which is the target of the first butterfly operation, to the input buffers 52-0 to 52-3 separately. , Input buffer 52-
Input data from the selector 51 is stored in each of 0 to 52-3. Then, in the input buffers 52-0 to 52-3, the stored input data, that is, the four input data that are the targets of the first butterfly operation are read out at the same time, and are read via the selectors 53-0 to 53-3. The signals are supplied to the terminals in0 to in3 of the butterfly computing unit 54 at the same time. Therefore, the butterfly computing unit 54 can start the butterfly computing without waiting time.

The butterfly computing unit 54 uses the rotation operator data (twiddle factor) stored in the ROM 55 to perform a butterfly computation with a base of 4 on the data input to the terminals in0 to in3, and obtains the result. 4 data (butterfly calculation results) are output to the terminal out
Output from 0 to out3. This terminal out0 to o
All the data output from ut3 is the selector 56
-0 to 56-3.

In the selectors 56-0 to 56-3, the butterfly calculator 54 of the butterfly calculator 54 is arranged so that the four pieces of data required simultaneously for the next butterfly calculation are separately stored in the memories 58-0 to 58-3, respectively. Terminals out0 to ou
Any one of the four data supplied from t3 is selected and supplied to the memories 58-0 to 58-3 via the selectors 57-0 to 57-3, respectively. The memories 58-0 to 58-3 are selectors 57-0 to 57-.
The data supplied via 3 are stored simultaneously. Therefore, the four data output from the terminals out0 to out3 of the butterfly computing unit 54 are respectively stored in the memories 58-0 to 58-3 without waiting time.

As described above, the memories 58-0 to 58
-4, each of the four pieces of data, which are separately stored and are to be subjected to the next butterfly operation, are simultaneously read out from each of them at a predetermined timing, and all of them are selected by the selector 60.
0 to 60-3.

The selectors 60-0 to 60-3 among the data read from the memories 58-0 to 58-3, respectively, have terminals in0 to in3 of the butterfly computing unit 54.
Select what should be input to each and select 53-
0 to 53-3 respectively. Selector 53-0
To 53-3 are input buffers 52-0 to 52- in which all the input data constituting the processing unit of the butterfly operation are input.
The output of the input buffers 52-0 to 52-3 is selected and supplied to the terminals in0 to in3 of the butterfly computing unit 54, respectively.

Then, the selectors 53-0 to 53-3
After all the input data to be subjected to the butterfly operation are supplied from the input buffers 52-0 to 52-3, the data supplied from the selectors 60-0 to 60-3 is selected, and the butterfly operation unit 54 It is supplied to the terminals in0 to in3, respectively. Therefore, in this case, the memory 58-0
The data read simultaneously from each of the to 58-3 are simultaneously supplied to the butterfly computing unit 54, and as a result, the butterfly computing unit 54 can immediately perform the butterfly computation.

In this way, the butterfly computing unit 54 repeatedly executes the butterfly computation on the butterfly computation result a predetermined number of times.

When the butterfly operation processing is performed a predetermined number of times, that is, when the final butterfly operation result is obtained, the selectors 56-0 to 57-3 thereafter select the selector 56-0. The data supplied from the output buffers 59 to 56-3 are simultaneously supplied to the output buffers 59-0 to 59-3 and stored therein. Therefore, in this case, the butterfly computing unit 54 can output the four data obtained as the final result of the butterfly computing without waiting time.

The data stored in the output buffers 59-0 to 59-3 are read out simultaneously, for example, and the selector 6
In 1, parallel / serial conversion is performed and output.

As described above, even when the FFT operation is performed by the butterfly operation whose base is 4, the processing speed can be increased.

Next, FIG. 8 shows the configuration of a sixth embodiment of the FFT operation device to which the present invention is applied. In the figure,
The parts corresponding to those in FIG. 6 are designated by the same reference numerals. That is, this FFT operation device is composed of the input buffers 22-0 and 22-1, the memories 15-0 and 15-.
1, instead of the output buffer 32-0 or 32-1
Input buffer units 71-0 and 71-1, memory unit 72-
0, 72-1, output buffer unit 73-0, or 73-
1 is respectively provided, and the FFT operation device of FIG. 6 has the same configuration.

The input buffer section 71-0 includes a selector 71.
-0-1, input buffers 71-0-2, 71-0-3,
And a selector 71-0-4. The selector 71-0-1 alternates the data input to the input buffer unit 71-0 with the input buffers 71-0-2 and 71-0-2.
-0-3.

Input buffers 71-0-2 and 71-0-3
Means that the data supplied from the selector 71-0-1 is stored, the stored data is read out, and
It is designed to supply to 0-4.

The selector 71-0-4 is connected to the input buffer 7
The data supplied from 1-0-2 and 71-0-3 are alternately selected and output.

The selector 71-0-4 is adapted to select one of the input buffers 71-0-2 or 71-0-3 which is not supplied with data from the selector 71-0-1. ing. Therefore, the input buffer unit 71
At −0, the input buffer 71-0-2 or 71
When data is being written to any one of −0-3, data is read from the other.

Input buffer section 71-1 and memory section 72-
0, 72-1, output buffer unit 73-0, or 73-
1 is also the selector 71-0- of the input buffer unit 71-0.
1, input buffers 71-0-2, 71-0-3, and selector 71-0-4 corresponding to selector 71-0-4.
1, input buffers 71-1-2 and 71-1-3, selector 71-1-4, selector 72-0-1, memories 72-0-2 and 72-0-3, and selector 72-0.
-4, selector 72-1-1, memories 72-1-2, 7
2-1-3, selector 72-1-4, selector 7
3-0-1, output buffers 73-0-2, 73-0-
3 and selector 73-0-4 or selector 73
-1-1, output buffers 73-1-2, 73-1-3,
And selector 73-1-4.

In the FFT operation device configured as described above, the input buffer 71-0-2 or 71-0-
When data is being written to any one of the three, data is read from the other, so that data writing and reading are simultaneously performed with respect to the input buffer unit 71-0. be able to. The same applies to the input buffer unit 71-1, the memory units 72-0 and 72-1 and the output buffer units 73-0 and 73-1 that are configured similarly to the input buffer unit 71-0. Therefore, in this case, the processing speed can be further increased as compared with the case of FIG. 6 in which data reading and writing are performed separately (in other words, the input buffer units 71-0, 71-1, Memory units 72-0, 72-1,
The clock of the output buffer unit 73-0 or 73-1 is input to the input buffers 22-0 and 22-1, the memory 15-.
0, 15-1, output buffer 32-0, or 32-1
A clock with half the frequency of each clock is fine).

The FFT arithmetic unit to which the present invention is applied has been described above. Such an FFT arithmetic unit performs digital signal processing in addition to the DAB receiver shown in FIG. 9 as described above, for example. It is widely applicable to devices. Further, the data to be subjected to the FFT is not limited to the audio signal, but may be a video signal or other digital signal.

In the present embodiment, the case of performing the FFT processing has been described, but the present invention is also applicable to the case of performing the inverse FFT processing (for performing the inverse FFT processing, for example, the ROM 5 ( 55), it is only necessary to change the twiddle factor to be stored, and therefore, in the present specification, F
In the broad sense, FT includes inverse FFT).

In this embodiment, the case where the radix N is 2 and 4 is taken as an example, but the present invention can be applied to other radices.

Further, in the embodiment of FIG. 2 and the like, the two outputs of the butterfly computing unit 4 are connected to the selectors 13-0 and 13-1.
3-1 and the selector 13-0 or 13-
In 1, select either one or the other,
The selector 14-0 or 14-1 is supplied to the selector 14-0 or 14-1, and the selector 14-0 or 14-1 outputs the output of the selector 13-0 or 13-1 to the memory 15-.
0 or 15-1, respectively, or the final butterfly calculation result is output. However, in addition, for example, the terminal o of the butterfly calculator 4 is used.
The output of ut0 or out1 is supplied to the selector 13-0 or 13-1, respectively, and the terminal out0 or o of the selector 13-0 or 13-1 is supplied.
The output of ut1 is supplied to both the selectors 14-0 and 14-1 or is output as the final butterfly operation result, and the selector 14-
It is also possible to adopt a configuration in which the output of either one or the other of the selectors 13-0 or 13-1 is selected in 0 or 14-1 and supplied to the memory 15-0 or 15-1 respectively. is there.

However, in the case of applying the latter configuration to the embodiments shown in FIGS. 5 and 6, for example, the butterfly computing unit 4
The final butterfly operation result output from the terminal out0 or out1 of the output buffer 32-0, respectively.
Alternatively, since it can only be stored in 32-1, the final butterfly operation result output from the terminals out0 and out1 is output buffer 32-0 or 32.
In order to be able to store in any of -1, it is necessary to have the configuration (the former configuration) described in the present embodiment.

[0093]

According to the FFT operation device of the first aspect and the FFT operation method of the seventh aspect, since data is written or read to / from N storage means at the same time, the operation can be performed at high speed. It becomes possible to perform FFT calculation.

[Brief description of drawings]

FIG. 1 is a diagram showing a signal flow for explaining the principle of the present invention.

FIG. 2 is a block diagram showing a configuration of a first embodiment of an FFT operation device to which the present invention is applied.

FIG. 3 is a timing chart for explaining the operation of the embodiment of FIG.

FIG. 4 is a block diagram showing a configuration of a second embodiment of an FFT operation device to which the present invention has been applied.

FIG. 5 is a block diagram showing a configuration of a third embodiment of an FFT operation device to which the present invention has been applied.

FIG. 6 is a block diagram showing a configuration of a fourth embodiment of an FFT operation device to which the present invention has been applied.

FIG. 7 is a block diagram showing a configuration of a fifth embodiment of an FFT operation device to which the present invention has been applied.

FIG. 8 is a block diagram showing a configuration of a sixth embodiment of an FFT operation device to which the present invention has been applied.

FIG. 9 is a block diagram showing a configuration example of a DAB receiving device.

10 is a block diagram showing a configuration example of an FFT circuit 94 of FIG.

11 is a timing chart explaining the operation of the FFT circuit 94 of FIG.

[Explanation of symbols]

2,3 selector, 4 butterfly computing unit, 6,7
Selector, 8 memory, 10, 11-0, 11-
1, 12-0, 12-1, 13-0, 13-1, 14-
0, 14-1 selector, 15-0, 15-1 memory, 16, 21 selector, 22-0, 22-1
Input buffer, 31 selector, 32-0, 32-
1 output buffer, 33 selector, 51, 52-
0 to 52-3, 53-0 to 53-3 selectors,
54 butterfly computing unit, 56-0 to 56-3, 5
7-0 to 57-3 selector, 58-0 to 58-
3 memories, 59-0 to 59-3 output buffers,
60-0 to 60-3, 61 selector, 71-0
Input buffer unit, 71-0-1 selector, 71-0
-2, 71-0-3 Input buffer, 71-0-4
Selector, 71-1 input buffer unit, 71-1-
1 selector, 71-1-2, 71-1-3 input buffer, 71-1-4 selector, 72-0 memory unit, 72-0-1 selector, 72-0-2, 72
-0-3 memory, 72-0-4 selector, 72
-1 memory unit, 72-1-1 selector, 72-
1-2, 72-1-3 memory, 72-1-4 selector, 73-0 output buffer section, 73-0-1
Selector, 73-0-2, 73-0-3 output buffer, 73-0-4 selector, 73-1 output buffer section, 73-1-1 selector, 73-1-2,
73-1-3 output buffer, 73-1-4 selector

Claims (7)

[Claims] 1. An FFT operation device for performing FFT (Fast Fourier Transform) operation, comprising: operation means for performing butterfly operation of a predetermined radix N; and N storage means for storing data related to the butterfly operation. An FFT operation device characterized in that writing or reading of the data with respect to the N storage means is performed at the same time. 2. The FFT operation device according to claim 1, wherein the N storage means store the output of the operation means and feed back to the input of the operation means. 3. The FFT operation device according to claim 1, wherein the N storage means store an input to the operation means and supply the input to the operation means. 4. The FFT operation device according to claim 1, wherein the N storage means store an output as a final result of the butterfly operation of the operation means. 5. The N storage means stores the output of the arithmetic means and feeds back to the input of the arithmetic means, and stores the input to the arithmetic means and supplies the input to the arithmetic means. The FFT operation device according to claim 1, further comprising three types: an output of the operation means and an output of the operation result as the final butterfly operation result. 6. Each of the N storage means has first and second storage means for storing the data, and one of the first and second storage means is written to. The FFT operation device according to claim 1, wherein when the other is present, reading is performed from the other. 7. An FFT operation of an FFT operation device, which comprises an operation means for performing a butterfly operation of a predetermined radix N and N storage means for storing data related to the butterfly operation, and which performs an FFT (Fast Fourier Transform) operation. A method for performing FFT calculation, comprising: simultaneously writing or reading the data to or from the N storage means.