GB2328765A

GB2328765A - Bit reversing using an offset

Info

Publication number: GB2328765A
Application number: GB9718417A
Authority: GB
Inventors: Rainer Makowitz; Michael Mayr
Original assignee: Motorola GmbH
Current assignee: Motorola Solutions Germany GmbH
Priority date: 1997-08-29
Filing date: 1997-08-29
Publication date: 1999-03-03
Anticipated expiration: 2017-08-29
Also published as: GB9718417D0; GB2328765B

Abstract

A memory addressing method for bit-reversing data samples using a buffer, uses alternate linear and bit-reversed addressing schemes for writing sets of data samples into the buffer, and reading sets of data samples from the buffer. An address offset is included in both addressing schemes and re-ordering of the read data samples of each set takes place, in dependence upon the value of the address offset, in order to produce sets of output data samples which are bit-reversed and offset.

Description

MEMORY ADDRESSING METHOD AND SYSTEM Field of the Invention This invention relates to memory addressing methods, and particularly but not exclusively to memory addressing methods for addressing fast fourier transform data samples.

Background of the Invention In many video applications, such as digital television broadcasting, Orthogonal Frequency Division Multiplexing (OFDM) is used. In order to demodulate an incoming digital signal according to OFDM, a Fast Fourier Transform (FFT) function must be performed on the signal. Typically the FFT comprises an algorithm for producing transform data samples, and a re-ordering step. The re-ordering step is necessary because the algorithm delivers the samples in abit-reversed" order. For example, the first data sample, which should be at address "001" (position 1) actually arrives from the algorithm at "100" (position 4), as the bit-reverse of"001" is "100".

A number of methods are known for performing the bit reversal of the samples. A first method involves the use of a memory buffer which is twice the size of the samples. In a first cycle, data is written into a first portion of the memory buffer, and at the same time read from a second portion of the memory buffer. In a second cycle, data is written into the second portion and read from the first portion. The writing step in each case is addressed in linear order, and the reading step is addressed in bit-reversed order.

A second, more memory efficient method involves the use of a memory buffer having the same size as the samples. In this method the memory read/write operation toggles between linear and bit-reversed addressing order, such that each set of samples are either written into the memory with bitreversed addressing and then read with linear addressing, or viceversa.

A problem with this second arrangement is that it may be desirable to introduce an address offset at the same time as the re-ordering step, in order to facilitate convenient post-transform processing of the samples.

This offset is easily achievable using the first method. However the second, memory efficient method is not compatible with such an offset.

This invention seeks to provide a memory addressing method and system which mitigate the above mentioned disadvantages.

Summarv of the Invention According to a first aspect of the present invention there is provided a memory addressing method for bit-reversing sets of data samples using a buffer, comprising the steps of: addressing the buffer using an alternate one of linear and bit-reversed addressing schemes, in order to write a set of data samples to the buffer and to read a set of data samples from the buffer; re-ordering the set of data samples read from the buffer in dependence upon the value of the address offset to produce a set of output data samples, such that the set of output data samples are bit-reversed and offset.

According to a second aspect of the present invention there is provided an addressing system for bit-reversing data, comprising: a buffer arranged to store sets of data samples; an address module, coupled to address the buffer using linear and bit-reversed addressing schemes; an address offset unit, coupled to provide an offset value to the address module; and, a re-ordering unit, coupled to re-order data samples read from the buffer in dependence upon the value of the address offset, for providing a set of output data samples, wherein the address module is arranged to address the buffer using the linear and bit-reversed addressing schemes alternately, such that the set of output data samples are bit-reversed and offset.

Preferably the system forms part of a set-top box for a television set. The address offset preferably has a predetermined value N/M, where N is the number of data samples per set, and wherein the re-orderingscheme is arranged to reverse the order of M data samples of each set.

Preferably the address offset has a value equal to half of the number of data samples in each set, and the re-ordering scheme is arranged to reverse the order of each pair of data samples of each set. The data samples are preferably fast fourier transform samples.

In this way bit-reversed, offset data samples are provided, without the need for a large memory buffer which is twice the size of a set of samples.

Brief Description of the Drawings An exemplary embodiment of the invention will now be described with reference to the drawings in which: FIG. 1 shows a diagram of a prior art set-top box for a television.

FIG. 2 shows a preferred embodiment of a memory addressing system in accordance with a first aspect of the invention.

FIG. 3 shows a preferred memory addressing method in accordance with a second aspect of the invention.

Detailed Description of a Preferred Embodiment Referring to FIG. 1, there is shown a set-top box 5 for a television set (not shown). The system 5 comprises a front-end terrestrial unit 6, a core 7, and an antenna 8.

The front end unit 6 has an OFDM demodulator 10 and a tuner 15. The OFDM demodulator 10 is coupled to receive a baseband signal from the tuner 7, which in turn, is coupled to receive an RF signal from the antenna 8.

The OFDM demodulator 10 has an inphase/quadrature separator module 20 coupled to receive the baseband signal from the tuner 15, for providing digital data signals. The output of the inphase/quadrature separator module 20 is coupled to a FFT module 30. The FFT module 30 has a butterfly computation unit 32 and a bit-reversal unit 35, to perform butterfly computations and bit-reversal of the incoming digital data signals respectively, to produce frequency domain data samples.

The frequency domain data samples are forwarded to a synchronisation and channel correction unit 40 of the OFDM 10, before being sent on to the core 7, where they are then further processed. The core typically includes a microprocessor 50 and an MPEG decoder 60.

Referring now also to FIG. 2, there is shown a bit-reversal unit 100, suitable for use with the set-top box 5 of FIG. 1, in place of the prior art bit-reversal unit 35.

The bit-reversal unit has a memory buffer 150 of N addresses, a data input terminal 105, coupled to receive data samples from the butterfly computation unit 32 of the OFDM 10, for storage in the memory buffer 150, and a data output terminal 195, for providing data samples received from the memory buffer 150.

A binary counter 110 of the bit-reversal unit 100 is arranged to generate linearly rising addresses, up to the highest address N. An offset unit 120 is coupled to receive these linearly rising addresses, for providing addresses with an address offset of N/2.

A reverse unit 130 is coupled to receive the offset addresses from the offset unit 120, for generating bit-reversed addresses in dependence upon the received offset addresses.

A control unit 140 is selectively coupled to the reverse unit 130 and to the offset unit 120, in order to receive one of the offset addresses and the bitreversed addresses. In a first cycle of addressing, cycle I, the control unit 140 is coupled to receive the offset addresses only, from the offset unit 120.

In a second cycle of addressing, cycle II, the control unit 140 is coupled to receive the bit-reversed and offset addresses, from the reverse unit 130.

In this way a two cycle addressing scheme is produced, as shown in table 1 below.

Binary Couner Oiibet N2) Cycle I Cycle II (bi+ (uptown) reversal) 000 100 100 001 001 101 101 101 010 110 110 011 on 111 111 111 100 000 000 000 101 001 001 100 110 010 010 010 111 011 011 110 Tabe 1: Cvcle I and Cvcle II Addre9sine schemes for ET-3 The control unit 140 is coupled to address the memory buffer 150 via two address units 160 and 170. In this way the memory buffer 150 is addressable using first and second cycles (addressing schemes). In both cases the addressing of a memory location involves both the writing of incoming data to the location (write), and the reading of stored data from the location (read).

The data samples read from the memory buffer 150 are provided to a reorder unit 180, which comprises two registers, an X-register 185 and a Y register 190. The X-register 185 is coupled to selectively receive the data samples from the memory buffer, and is arranged to store a data sample and to selectively provide the stored data sample to the Y-register 190. The Y-register 190 is coupled to selectively receive either the stored data sample from the X-register 185, or the data sample from the memory buffer 150, in dependence upon the least significant bit (LSB) of the read address. The Yregister 190 is further arranged to store the data sample and to provide the stored data sample to a data output terminal 195, which provides the stored data sample to the synchronisation channel correction unit 40 of the OFDM 10.

If the LSB of the address of the incoming data sample is 1, it is stored in the X-register 185. If the LSB of the address of the incoming data sample is 0, it is stored in the Y-register 190.

In operation, and referring now also to FIG. 3 and to table 2 below, there is shown a method of addressing the memory buffer 150.

Data Input Memory Output Part Final order (I) order (n) Result Result a(000) 100 b 001 f e e (100) 101 f 101 e f c(010) 110 d 011 h g g(110) 111 h 111 g h b(001) 000 a 000 b a f(101) 001 e 100 a b d (011) 010 c 010 d c h (111) 011 g 110 c d Table a:Data order and Addessitlg From the start block 200, data samples are received from the butterfly computation unit 32 via the data input terminal 105. These data samples, shown in the first column of table 2, are not in their required order, and the data bits (shown in brackets) must be reversed to arrive at the correct order.

A first set of incoming data samples are selected to be written into the memory buffer 150 according to address cycle I (the left path from block 220). In cycle I, they encounter the offset (block 230), derived in table 1 and shown in the second column of table 2. Thus the first set of data samples are stored in the memory buffer 150 in the order shown in column 3 of table 2.

Assuming that the memory buffer 150 contained no meaningful data before the first set of data samples were written, the output of the memory buffer 150 during the first occurrence of cycle I is not meaningful, and re-ordering block 250 of FIG. 3 can be ignored.

At block 260, assuming that more data samples are incoming, the method returns to block 220, where a second set of incoming data samples are written into the memory buffer according to address cycle II, derived in table 1 and shown in the fourth column of table 2 (block 240). At the same time, the first set of data samples are read from the memory buffer 150 also according to address cycle II (see fourth column of table 2), where they then have the order as shown in the fifth column of table 2.

The read data samples are then provided to the re-order unit 180, (block 250) where the X-register 185 and the Y-register 190 serve to reverse the order of each pair of data samples. For example, the X-register 185 receives the first data sample (f), and stores it, after which the Y-register 190 receives the second data sample (e). The X-register 185 then receives the third data sample (h), upon which 'f is sent to the Y-register 190, which simultaneously writes 'e' to the data output terminal 195. 'g is then received by the Y-register 190, which simultaneously writes Y to the data output terminal 195. Therefore the order of the data samples when received by the data output terminal 195 is 'e','f,'g','h' etc..

This process is repeated for each pair of data samples, such that the first sample of a pair is stored in the X-register 185, while the second sample of the pair is stored in the Y-register. In this way, the data samples are reordered and also offset by N/2 (see table 2, column 6).

The above method is repeated for every incoming set of data samples, toggling between cycle I and cycle II addressing, until no more data samples are received, at which point the end block 270 is reached.

The N/2 offset is useful because it greatly improves the efficiency and perlFrmance of the tuner 15 in conjunction with the synchronisation and channel correction unit 40. In the prior art, a discrete offset was typically provided. According to the above method, the bit-reversal and an offset of Niff2 are provided in one simple arrangement, which uses a memory buffer of size N, together with two registers.

It will be appreciated that alternative embodiments to the one described above are possible. For example, the re-order unit 180 could be replaced by a different arrangement which performs substantially the same function.

Furthermore, the number of data values N and the corresponding size of the memory buffer 150 may be different to those described above. In addition, the bit-reversal method described above could be applied to fields other than FFT.

Finally, the offset value may be different from the N/2 value described above.

If the offset value is N/M, where M is an integer, then the re-order unit 180 will be arranged to re-order each set of M data samples.

Claims

1. A memory addressing method for bit-reversing sets of data samples using a buffer, comprising the steps of: addressing the buffer using an alternate one of linear and bit-reversed addressing schemes, in order to write a set of data samples to the buffer and to read a set of data samples from the buffer; re-ordering the set of data samples read from the buffer in dependence upon the value of the address offset to produce a set of output data samples, such that the set of output data samples are bit-reversed and offset

2. An addressing system for bit-reversing data, comprising: a buffer arranged to store sets of data samples; an address module, coupled to address the buffer using linear and bitreversed addressing schemes; an address offset unit, coupled to provide an offset value to the address module; and, a re-ordering unit, coupled to re-order data samples read from the buffer in dependence upon the value of the address offset, for providing a set of output data samples, wherein the address module is arranged to address the buffer using the linear and bit-reversed addressing schemes alternately, such that the set of output data samples are bit-reversed and offset.

3. The system of claim 2 wherein the system forms part of a set-top box for a television set.

4. The method of claim 1 or system of claims 2 or 3 wherein the address offset has a predetermined value N/M, where N is the number of data samples per set, and wherein the re-ordering scheme is arranged to reverse the order of M data samples of each set.

5. The method or system of any preceding claim wherein the address offset has a value equal to half of the number of data samples in each set, and the re-ordering scheme is arranged to reverse the order of each pair of data samples of each set.

6. The method or system of any preceding claim wherein the data samples are fast fourier transform samples.

7. A method substantially as hereinbefore described and with reference to FIG. 3 of the drawings.

8. A system substantially as hereinbefore described and with reference to FIGs. 2 and 3 of the drawings.