JPH09305520A - Device state establishing method for peripheral device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To always report the proper device state of a peripheral device to a user by establishing the device state of the peripheral device after no change in the state of a parallel port interface control signal for a prescribed period is monitored. SOLUTION: A data transfer control part 7 of a parallel port control signal 6 performs the hand shake of data transfer of a parallel port interface. Besides, a device state monitor part 8 monitors the timer interruption and the state change interruption of the parallel port interface control signal for prescribed time so that the stabilization of device state of the peripheral device is waited. Corresponding to the combination of SLCT, PE, *FAULT and BUSY as one part of the parallel port interface control signal, a device state discriminating part 9 establishes the device state of the peripheral device such as on-line, off-line, error generation and power supply stop and reports the device state to the user.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining a device state of a peripheral device in a system in which a host device and a peripheral device are connected by a parallel port interface, and more particularly, to always determine a correct device state of the peripheral device. , Always be able to inform the user of the correct peripheral device status.

[0002]

2. Description of the Related Art FIG. 5 shows a block diagram of a conventional device state confirmation processing of a peripheral device. In the figure, 1 is a host device, 2 is a parallel port control device for controlling a parallel port interface which is one of the interfaces for connecting the host device 1 and the peripheral device 3, and 3 is a printer device having a parallel port interface. And peripheral devices such as a scanner device. 4, 5 are a part of the parallel port interface signal lines, 4 are data lines, 5 is SL
Signal lines such as CT, PE, * FAULT and BUSY are shown.

Reference numeral 56 is a parallel port control processing unit,
When the application program accesses the peripheral device 3 such as a print request to the printer device or a read request of image data from the scanner device, the operating system controls the parallel port control device 2 to perform data transfer processing to the peripheral device 3. One processing unit.

The parallel port control processing unit 56 includes a data transfer control unit 57 for performing a handshake for data transfer of the parallel port interface, SLCT, PE, *.
Online by combining some parallel port interface control signals such as FAULT and BUSY
The device state determination unit 59 is configured to determine the device state of the peripheral device such as offline, error occurrence, power off, and notify the user of the device state.

FIG. 3 is a flow chart of a device state confirmation process of a conventional peripheral device. The device status confirmation process is executed to confirm whether the printer device or scanner device is in an operable state prior to the data transfer process when the application program issues a print request to the printer device or an image data read request from the scanner device. To be done.
It is also executed when confirming whether the print request or the read request is normally completed.

The operation will be described below with reference to this flowchart.

In step S301, the device state determination unit 59
Read the parallel port interface control signals such as SLCT, PE, * FAULT, BUSY,
Confirm the device status of peripheral devices such as online, offline, error occurrence, power off.

[0008]

However, in the conventional technique shown in FIG. 3, the device state of the peripheral device 3 may not be correctly determined. FIG. 4 shows the timing when the device state is not correctly determined.

FIG. 4 is an example of a timing chart of the parallel port interface control signal when the peripheral device is powered off. When the peripheral device 3 is in the normal operation state, it is a part of the parallel port interface control signal SLC.
The T, PE, * FAULT, and BUSY signals are in the states of SLCT being H, PE being L, * FAULT being H, and BUSY being L. At this time, if the power outlet of the peripheral device 3 is accidentally unplugged, SLCT, PE, * FAUL
The T and BUSY signals are in an indefinite state for a predetermined time t. After that, SLCT, PE, * FAULT, BUSY
Signals are L for SLCT, L for PE, * FAULT for L,
BUSY is in the L state.

SLCT, PE, * FAULT, BUSY
When the device state confirmation process of the peripheral device is performed during the predetermined time t when the signal is indefinite, the device state confirmation process of the incorrect peripheral device is performed, and the user is notified of the incorrect device state of the peripheral device. Become.

That is, if the peripheral device's device state determination process is performed immediately after the peripheral device 3 is powered off, there is a problem that the incorrect peripheral device state is notified to the user.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and in a system in which a host device 1 and a peripheral device 3 are connected by a parallel port interface, parallel port interface control is performed. A method for determining a device state of a peripheral device in which the correct device state of the peripheral device 3 can be always determined by determining the device state of the peripheral device 3 after monitoring that the signal state has not changed for a predetermined period. I will provide a.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, in a system in which a host device 1 and a peripheral device 3 are connected via a parallel port interface, the peripheral port interface control signal is monitored for a predetermined period of time and then the peripheral device is monitored. By determining the device state of the device 3, it is possible to always determine the correct device state of the peripheral device 3.

[0014]

The present invention will be described in detail below with reference to examples.

FIG. 1 is a block diagram of a device state confirmation processing of the peripheral device of the present invention. In the figure, 1 to 5 are the same as those in FIG. 5, and the description thereof is omitted here. A parallel port control processing unit 6 controls the parallel port control device 2 when the application program accesses the peripheral device 3 such as a print request to the printer device or a read request of image data from the scanner device. 3 is a processing unit of an operating system that performs a data transfer process for the data.

The parallel port control processing unit 6 monitors the data transfer control unit 7 which performs a handshake for data transfer of the parallel port interface, the timer interrupt and the state change interrupt of the parallel port interface control signal for a predetermined time. As a result, the device state monitoring unit 8 that waits for the device state of the peripheral device to stabilize, and SLCT and P that are part of the parallel port interface control signal.
A combination of E, * FAULT, and BUSY configures the device status of the peripheral device such as online, offline, error occurrence, power off, etc. and notifies the user of the device status.

FIG. 2 is a flow chart of the device state confirmation processing of the peripheral device of the present invention. Hereinafter, the operation will be described with reference to this flowchart.

From step S201 to step S204, processing is performed by the device state monitoring unit 8, and step S2
05 is processed by the device state determination unit 9.

First, in step S201, a timer interrupt in which a time for monitoring the state change of the parallel port interface control signal is set is registered. The time for monitoring the state change is set to a value larger than a predetermined time t during which the parallel port interface control signal becomes indefinite due to power failure of the peripheral device or the like.

A step S202 sets the parallel port control device 2 in an interrupt enable state in which a timer interrupt and a parallel port interface control signal state change interrupt are permitted.

A step S203 waits for generation of a timer interrupt or a parallel port interface control signal state change interrupt.

A step S204 decides whether the interrupt generated in the step S203 is a timer interrupt. If it is a timer interrupt, the process proceeds to step S205. If it is not a timer interrupt, it means that there is a state change within the time for monitoring the state change of the parallel port interface control signal, and the process returns to step S201 to monitor the state change of the parallel port interface control signal again.

In step S205, the device state determination unit 9 reads the parallel port interface control signals of SLCT, PE, * FAULT, and BUSY, and determines the device state such as online, offline, error occurrence, power off.

[0024]

The present invention is embodied in the form described above, and has the following effects.

A parallel port between the host device and the peripheral device
In a system connected by an interface, after monitoring that the state of the parallel port interface control signal has not changed for a predetermined period, by fixing the device state of the peripheral device, the correct device state of the peripheral device is always notified to the user. It becomes possible.

[Brief description of drawings]

FIG. 1 is a block diagram of a device state confirmation process of a peripheral device of the present invention.

FIG. 2 is a flowchart of a device state confirmation process of a peripheral device of the present invention.

FIG. 3 is a flowchart of a device state confirmation process of a conventional peripheral device.

FIG. 4 is a timing chart example of a parallel port interface control signal when the peripheral device is powered off.

FIG. 5 is a block diagram of a device state determination process of a conventional peripheral device.

[Explanation of symbols]

 1 Host device 3 Peripheral device

Claims (1)

[Claims] 1. A system in which a host device (1) and a peripheral device (3) are connected by a parallel port interface, and after monitoring that the state of a parallel port interface control signal has not changed for a predetermined period, the peripheral device ( 3) A method for determining a device state of a peripheral device, which comprises determining the device state.