JPH09298347A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH09298347A
JPH09298347A JP8132815A JP13281596A JPH09298347A JP H09298347 A JPH09298347 A JP H09298347A JP 8132815 A JP8132815 A JP 8132815A JP 13281596 A JP13281596 A JP 13281596A JP H09298347 A JPH09298347 A JP H09298347A
Authority
JP
Japan
Prior art keywords
circuit
layer
conductor pattern
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8132815A
Other languages
Japanese (ja)
Inventor
Kiyotada Yokoki
清忠 横木
Shinichi Hirota
伸一 弘田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP8132815A priority Critical patent/JPH09298347A/en
Publication of JPH09298347A publication Critical patent/JPH09298347A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent stray capacitance from being formed in circuits by forming a grounded third conductor pattern layer facing the opposite surface of a second conductor pattern layer to a circuit pattern of a first conductor pattern layer; the second layer having insulation regions facing at this circuit pattern. SOLUTION: The printed wiring board 50 mounts circuit parts 6 on parts mounting faces 51, 52 of the surfaces of boards. The mounting faces 51, 52 and conductor earth layers 53, 54 are laminated through insulative epoxy resin layers inserted therebetween to form a laminate structure printed wiring board. On one parts mounting face 51 the parts 6 are connected through conductors to a circuit pattern 6A to form VCO circuits. The lower earth layer 53 facing the circuit pattern 6A through an epoxy material forms insulation regions 53A by removing the conductor pattern at areas facing the VCO circuits 22.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はプリント配線板に関
し、例えばデイジタルコードレス電話の送受信部に設け
られるVCO(Voltage Controlled Oscillator) 回路等
の高周波発振回路に適用して好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and is preferably applied to a high-frequency oscillation circuit such as a VCO (Voltage Controlled Oscillator) circuit provided in a transmitting / receiving section of a digital cordless telephone.

【0002】[0002]

【従来の技術】従来、例えば携帯電話の送信回路や受信
回路に用いる電圧制御発振(VCO)回路のような高周
波(RF,Radio Frequency)回路を板厚の薄い多層基板上に
構築する場合、図3に示すような高周波用のプリント配
線板1が用いられている。この種のプリント配線板1
は、例えば4層の導体パターン層を有している。この場
合、プリント配線板1は表裏の表面層を部品面2及び3
として、それぞれ高周波回路6を設けるようにして、そ
の間に2層の導体パターン層でなるアース層4及び5を
絶縁性の基板材料であるエポキシ樹脂を間に挿んで積層
している。
2. Description of the Related Art Conventionally, when a high frequency (RF, Radio Frequency) circuit such as a voltage controlled oscillation (VCO) circuit used in a transmitting circuit or a receiving circuit of a mobile phone is constructed on a thin multi-layer substrate, A high frequency printed wiring board 1 as shown in FIG. 3 is used. This kind of printed wiring board 1
Has, for example, four conductor pattern layers. In this case, the printed wiring board 1 has front and back surface layers on the component surfaces 2 and 3
As the high frequency circuit 6, the ground layers 4 and 5 composed of two conductor pattern layers are laminated between them by interposing an epoxy resin which is an insulating substrate material therebetween.

【0003】このように部品面2及び3の間に2層のア
ース層を設けて、部品面2及び3にそれぞれ実装される
高周波回路6相互の電磁的な輻射を遮つている(シール
ド)。ここでアース層を二層としているのは、シールド
効果を高めるため、若しくはいずれか一方のアース層に
信号線を設ける場合があるからである。
In this way, two ground layers are provided between the component surfaces 2 and 3 to shield electromagnetic radiation from each other between the high frequency circuits 6 mounted on the component surfaces 2 and 3, respectively (shield). Here, the ground layer has two layers because the signal line may be provided on either one of the ground layers in order to enhance the shield effect.

【0004】[0004]

【発明が解決しようとする課題】ところで上述したよう
な従来のプリント配線板1においては、装置を小型化す
るために高周波回路6が形成されている部品面2及び3
と、すぐその下層のアース層4及び5とを極めて近接し
た状態で形成している。このため高周波回路6の回路パ
ターン6Aとアース層4又は5との間にエポキシ樹脂層
を挿んで設けられる層間に大きな浮遊容量CSTが発生す
るようになる。
By the way, in the conventional printed wiring board 1 as described above, the component surfaces 2 and 3 on which the high frequency circuit 6 is formed in order to downsize the device.
And the ground layers 4 and 5 immediately thereunder are formed very close to each other. Therefore, a large stray capacitance C ST is generated between layers provided by inserting the epoxy resin layer between the circuit pattern 6A of the high frequency circuit 6 and the ground layer 4 or 5.

【0005】この結果、プリント配線板1に例えばVC
O回路等の高周波回路を形成する場合、(1)電圧変化
に対する周波数変化が小さくなる(すなわちVCO 感度が
低くなる)又は、(2)制御電圧を変化させ、発振周波
数を変化さた場合の制御電圧に対する周波数変化が不連
続になり発振がとびとびになるというような問題があつ
た。本発明は以上の点を考慮してなされたもので、多層
に積層される導体パターン層間に導体パターン層上に形
成される回路に容量性の不具合を生じさせる浮遊容量が
発生するのを未然に防止し得るプリント配線板を提案し
ようとするものである。
As a result, for example, VC
When forming a high frequency circuit such as an O circuit, (1) the frequency change with respect to the voltage change becomes small (that is, the VCO sensitivity becomes low), or (2) the control when the oscillation frequency is changed by changing the control voltage. There is a problem that the frequency change with respect to the voltage becomes discontinuous and the oscillation becomes discontinuous. The present invention has been made in consideration of the above points, and it is possible to prevent stray capacitance from occurring between the conductor pattern layers which are laminated in multiple layers, which causes a capacitive defect in a circuit formed on the conductor pattern layers. It is intended to propose a printed wiring board that can be prevented.

【0006】[0006]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、表面導体層を含めて少なくとも三
層以上の導体パターン層が互いに絶縁層を挿んで積層さ
れたプリント配線板において、部品を実装するための回
路パターンが形成された第1の導体パターン層と、回路
パターンとの対面部分に対応した絶縁領域を有する第2
の導体パターン層と、該第2の導体パターン層の第1の
導体パターン層が形成された側に対して反対側の面に対
面し、アース接続されてなる第3の導体パターン層とを
備える。これにより回路の形成される第1の導体パター
ン層の回路パターンに対して第3の導体パターン層を対
面させて、導体パターン層間の間隔を拡げ、第1の導体
パターン層上に形成される回路に対して容量性の不具合
を生じさせるような浮遊容量を層間に発生させないよう
にすることができる。
In order to solve the above problems, according to the present invention, in a printed wiring board in which at least three or more conductor pattern layers including a surface conductor layer are laminated with insulating layers interposed therebetween, a component A first conductor pattern layer on which a circuit pattern for mounting the circuit pattern is formed, and a second conductive pattern layer having an insulating region corresponding to a portion facing the circuit pattern.
And a third conductor pattern layer facing the surface of the second conductor pattern layer opposite to the side where the first conductor pattern layer is formed and grounded. . Thereby, the third conductor pattern layer is made to face the circuit pattern of the first conductor pattern layer on which the circuit is formed, the gap between the conductor pattern layers is widened, and the circuit formed on the first conductor pattern layer. On the other hand, it is possible to prevent a stray capacitance that causes a capacitive defect from occurring between layers.

【0007】[0007]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

【0008】以下図面について、本発明の一実施例を詳
述する。
An embodiment of the present invention will be described in detail with reference to the drawings.

【0009】(1)デイジタルコードレス電話の送受信
回路構成 図1において、10は全体として携帯電話の送受信回路
を示し、VCO回路等の高周波回路によつて回路を形成
している。送受信回路10においては、アンテナ12で
受信した受信信号S1をバンドパスフイルタ(BPF,Band
Pass Filter) 13を介して帯域制限した後、スイツチ
(SW)14によつて伝送経路を受信部15側へ切り換
えて送出する。
(1) Configuration of Transmitter / Receiver Circuit of Digital Cordless Telephone In FIG. 1, reference numeral 10 indicates a transmitter / receiver circuit of a mobile telephone as a whole, and a circuit is formed by a high frequency circuit such as a VCO circuit. In the transmission / reception circuit 10, the reception signal S1 received by the antenna 12 is transmitted to the band pass filter (BPF, Band).
After the band is limited through the Pass Filter, the transmission path is switched to the receiving unit 15 side by the switch (SW) 14 and is transmitted.

【0010】受信部15においては、ローノイズアンプ
(LNA,Low Noise Amplifier) 16によつて増幅した受信
信号S1をBPF17を介した後、第1のミキサ18に
送出する。ミキサ18には、局部発振回路20より、バ
ツフアアンプ(BF,Buffer Amplifier) 21を介して局部
発振信号S2が送出される。ミキサ18では局部発振信
号S2と受信信号S1とが混合され、第1の中間周波信
号SIFに変換される。
In the receiving unit 15, a low noise amplifier
The reception signal S1 amplified by the (LNA, Low Noise Amplifier) 16 is sent to the first mixer 18 after passing through the BPF 17. A local oscillation signal S2 is sent from the local oscillation circuit 20 to the mixer 18 via a buffer amplifier (BF, Buffer Amplifier) 21. In the mixer 18, the local oscillation signal S2 and the reception signal S1 are mixed and converted into the first intermediate frequency signal S IF .

【0011】ここで局部発振回路20はスワロカウンタ
によつて形成され、VCO回路22によつて電圧制御し
た周波数をPLL(Phase Locked Loop) 回路23によつ
て位相ロツクしてローパスフイルタ(LPF,Low Pass Fil
ter)24を介してフイードバツクし、さらにBA25を
介してPLL回路23に戻すようにして、局部発振信号
S2を生成するようになされている。このようにVCO
回路22の発振周波数がLPF24を介した信号によつ
て制御されるため、周波数可変範囲に余裕があることが
望ましい。つまり必要とする周波数範囲内で安定な発振
を維持することと、発振周波数を電圧制御させていくと
きに発振が不連続にとぶようなことがないようにするこ
とが要求される。
Here, the local oscillator circuit 20 is formed by a swallow counter, and the frequency whose voltage is controlled by the VCO circuit 22 is phase-locked by a PLL (Phase Locked Loop) circuit 23 to low-pass filter (LPF, Low). Pass Fil
ter) 24 and feed back to the PLL circuit 23 via BA 25 to generate the local oscillation signal S2. Like this VCO
Since the oscillation frequency of the circuit 22 is controlled by the signal passed through the LPF 24, it is desirable that the frequency variable range has a margin. That is, it is required to maintain stable oscillation within the required frequency range and to prevent the oscillation from jumping discontinuously when the oscillation frequency is voltage controlled.

【0012】中間周波信号SIFは、BPF27を介して
狭帯域化された後、第2のミキサ28に送出される。ミ
キサ28には、水晶発振子等でなる局部発振回路29よ
り基準搬送波S3が送出され、中間周波信号SIFと混合
されることにより第2の中間周波信号SIF2 を生成す
る。このようなダブルスーパーヘテロダイン方式を採用
することにより、受信周波数の選択度を上げることがで
きる。中間周波信号SIF2 は、BPF30を介して、検
波器(DET,Detector)31に送出され、ここで位相検波さ
れた後、復調信号S10として後段に出力される。
The intermediate frequency signal S IF is narrowed by the BPF 27 and then sent to the second mixer 28. To the mixer 28 is the reference carrier wave S3 from the local oscillation circuit 29 comprising a crystal oscillator or the like is transmitted, to generate a second intermediate frequency signal S IF2 by being mixed with the intermediate frequency signal S IF. By adopting such a double super heterodyne system, the selectivity of the reception frequency can be increased. The intermediate frequency signal S IF2 is sent to the detector (DET, Detector) 31 via the BPF 30, where the phase detection is performed, and then the demodulated signal S10 is output to the subsequent stage.

【0013】一方、送信部35においては、入力端子IN
から入力された送信データS20を変調器(MOD,Modulat
or) 36によつて変調し、その結果得られる変調信号S
21をミキサ37に送出する。変調信号S21はミキサ
37において、BA38を介して局部発振回路20より
送出される局部発振信号S2と混合され、中間周波信号
IF3 に変換される。中間周波信号SIF3 は、BPF3
9を介して狭帯域化された後、電力増幅器(Power Ampl
itier )40によつて電力増幅され、SW14及びBP
F13を介してアンテナ12より送信されるものであ
る。
On the other hand, in the transmitter 35, the input terminal IN
Transmit data S20 input from the modulator (MOD, Modulat
or) 36, and the resulting modulated signal S
21 is sent to the mixer 37. The modulation signal S21 is mixed in the mixer 37 with the local oscillation signal S2 sent from the local oscillation circuit 20 via the BA 38, and converted into the intermediate frequency signal S IF3 . The intermediate frequency signal S IF3 is BPF3.
After the band is narrowed through 9, the power amplifier (Power Amplifier
Itier) 40 power is amplified by SW14 and BP
It is transmitted from the antenna 12 via F13.

【0014】(2)高周波用プリント配線板 上述したような送受信回路10の局部発振回路20の一
部を形成する高周波回路構成のVCO回路22は、およ
そ数GHz(ギガヘルツ)の高周波を発振させるもので図
2に示すような高周波用のプリント配線板50上に形成
される。このプリント配線板50は、プリント基板の表
裏両面の部品面51及び52に導体の回路パターンを形
成して、それぞれ基板表面の部品面51及び52に回路
部品6を実装する両面実装タイプのプリント配線板であ
る。このプリント配線板50は、部品面51及び52
と、導体のアース層53及び54とが間に絶縁性のエポ
キシ樹脂層を挿んで積層された多層構造のプリント配線
板として形成される。このようにプリント配線板50
は、部品面51及び52の間に二層のアース層53及び
54を設けて、アース層53及び54をアース接続させ
ることによりそれぞれの部品面51及び52に形成され
る回路間の電磁的な輻射による相互干渉をシールドして
いる。
(2) High Frequency Printed Wiring Board The VCO circuit 22 having a high frequency circuit structure forming a part of the local oscillation circuit 20 of the transmission / reception circuit 10 as described above oscillates a high frequency of approximately several GHz (gigahertz). Is formed on the high frequency printed wiring board 50 as shown in FIG. The printed wiring board 50 is a double-sided mounting type printed wiring in which circuit patterns of conductors are formed on the component surfaces 51 and 52 on both front and back surfaces of a printed circuit board, and the circuit components 6 are mounted on the component surfaces 51 and 52 on the board surface, respectively. It is a plate. This printed wiring board 50 has component surfaces 51 and 52.
And the ground layers 53 and 54 of the conductor are laminated by inserting an insulating epoxy resin layer therebetween to form a multilayer printed wiring board. In this way, the printed wiring board 50
Is provided with two layers of ground layers 53 and 54 between the component surfaces 51 and 52, and by connecting the ground layers 53 and 54 to the ground, electromagnetic waves between the circuits formed on the component surfaces 51 and 52, respectively. Shields mutual interference due to radiation.

【0015】プリント配線板50の一方の部品面51に
は、回路部品6が回路パターン6Aに導体接続されVC
O回路22を形成する。このとき部品面51上において
形成されたVCO回路22の回路パターン6Aにエポキ
シ材を挿んで対面する、直ぐ下層のアース層53はVC
O回路22に対面する部分の導体パターンをくり抜いて
絶縁領域53Aを形成している。これにより、部品面5
1とアース層53との間の絶縁層の間隔を部品面51と
アース層54にまで拡げて、この部分の層間に発生する
浮遊容量を十分に小さなものにさせている。これにより
VCO回路22のVCO 感度を高くし得るとともに、発振
周波数を電圧制御によつて変化させたときの発振のとび
を防止して連続的でかつ、リニアなVCO特性を実現し
得る。
On one component surface 51 of the printed wiring board 50, the circuit component 6 is conductor-connected to the circuit pattern 6A and VC
The O circuit 22 is formed. At this time, the ground layer 53 immediately below the VCCO circuit 22 formed on the component surface 51 by inserting an epoxy material and facing the circuit pattern 6A is VC.
The insulating pattern 53A is formed by hollowing out the conductor pattern in the portion facing the O circuit 22. As a result, the component surface 5
The gap between the insulating layer 1 and the ground layer 53 is expanded to the component surface 51 and the ground layer 54 so that the stray capacitance generated between layers in this portion is sufficiently small. This makes it possible to increase the VCO sensitivity of the VCO circuit 22 and prevent the oscillation from jumping when the oscillation frequency is changed by voltage control to realize a continuous and linear VCO characteristic.

【0016】以上の構成において、電波の受信時又は送
信時、受信部15又は送信部35に対して局部発振信号
S2を局部信号発振回路20より供給する。このとき局
部信号発振回路20ではLPF24を介して送出される
信号に基づいてVCO回路22によつて局部発振信号の
周波数を電圧制御する。ここで、VCO回路22が形成
されたプリント配線板50においては、部品面51に形
成されたVCO回路22上の回路パターン6Aに対し
て、絶縁層となるエポキシ材を挿んで対面される直ぐ下
層のアース層53の対面領域の導体パターンをくり抜い
た絶縁領域53Aを形成しておく。
In the above structure, the local oscillation signal S2 is supplied from the local signal oscillation circuit 20 to the receiving unit 15 or the transmitting unit 35 when receiving or transmitting a radio wave. At this time, in the local signal oscillation circuit 20, the frequency of the local oscillation signal is voltage-controlled by the VCO circuit 22 based on the signal transmitted through the LPF 24. Here, in the printed wiring board 50 on which the VCO circuit 22 is formed, the lower layer immediately facing the circuit pattern 6A on the VCO circuit 22 formed on the component surface 51 by inserting an epoxy material serving as an insulating layer. An insulating region 53A is formed by hollowing out the conductor pattern in the facing region of the ground layer 53.

【0017】これによりVCO回路22の回路パターン
6Aの形成部分に対しては、絶縁層及び絶縁領域53A
を挿んでアース層54を対面させるようにして、導体パ
ターン層間の間隔を拡げる。これによりプリント配線板
50に形成されるVCO回路22に容量性の不具合を生
じさせる層間の浮遊容量CSTを極めて小さいものとして
いる。さらにこの場合、アース接続された導体パターン
層によるアース層53及び54の二層としていること
で、アース層53の一部をくり抜いた場合でも、他方の
アース層54によつて部品面51及び52間の電磁的な
輻射に対して十分シールドさせている。
As a result, for the portion where the circuit pattern 6A of the VCO circuit 22 is formed, the insulating layer and the insulating region 53A are formed.
Is inserted so that the ground layer 54 faces each other, and the space between the conductor pattern layers is widened. As a result, the inter-layer stray capacitance C ST that causes a capacitive defect in the VCO circuit 22 formed on the printed wiring board 50 is made extremely small. Further, in this case, since the two ground layers 53 and 54 are formed by the conductor pattern layer connected to the ground, even when a part of the ground layer 53 is hollowed out, the other ground layer 54 allows the component surfaces 51 and 52. It is sufficiently shielded against electromagnetic radiation between.

【0018】これにより局部発振回路20において、V
CO回路22によつて発振周波数を電圧制御して、PL
L回路23のPLLにおいて周波数をロツクするまでの
ロツクアツプタイム(Lock up time)をプリント配線板5
0に発生する浮遊容量により遅延させることを防止し
得、VCO 感度を高くすることができる。さらにVCO回
路22において、制御電圧を連続的に変化させて発振周
波数を変えていく場合、発振周波数のとびがなく連続的
でかつ、リニアなVCO特性をもつような回路を構築し
得る。
As a result, in the local oscillator circuit 20, V
The oscillation frequency is controlled by the CO circuit 22, and the
In the PLL of the L circuit 23, the lock-up time until the frequency is locked is printed by the printed wiring board 5.
It is possible to prevent the delay due to the stray capacitance generated at 0 and increase the VCO sensitivity. Further, in the VCO circuit 22, when the control voltage is continuously changed to change the oscillation frequency, it is possible to construct a circuit having continuous and linear VCO characteristics with no oscillation frequency jump.

【0019】以上の構成によれば、絶縁層と交互に4層
の導体パターン層を積層したプリント配線板50におい
て、部品面51に絶縁層を挟んで対面する直ぐ下層のア
ース層53の部品面51上に形成されたVCO回路22
の回路パターン領域に対応する導体パターン領域をくり
抜いて絶縁領域53Aを形成したことによつて、VCO
回路22に対応する導体パターン層間を回路パターン6
A及びアース層53間から回路パターン6A及びアース
層54間として層間隔を拡げるようにする。この結果、
VCO回路22に容量性の不具合を生じさせる浮遊容量
STが低く抑えられ、電圧を連続的に変化させて発振周
波数を変えていくときのVCO特性を発振周波数のとび
がなく連続的でかつ、リニアな変化特性をもつものにす
ることができる。さらにこれに加えて分布定数回路であ
る浮遊容量の影響が少なくなるため、集中定数回路の理
論のみでVCO回路を容易に構築し得るという利点もあ
る。
According to the above construction, in the printed wiring board 50 in which four conductor pattern layers are laminated alternately with the insulating layers, the component surface of the ground layer 53 immediately below, which faces the component surface 51 with the insulating layer interposed therebetween, VCO circuit 22 formed on 51
The conductor pattern area corresponding to the circuit pattern area of
The circuit pattern 6 is provided between the conductor pattern layers corresponding to the circuit 22.
The layer interval is widened from between A and the ground layer 53 to between the circuit pattern 6A and the ground layer 54. As a result,
The stray capacitance C ST that causes a capacitive defect in the VCO circuit 22 is suppressed to a low level, and the VCO characteristics when the voltage is continuously changed to change the oscillation frequency are continuous without oscillation of the oscillation frequency, and It can have a linear change characteristic. In addition to this, since the influence of the stray capacitance, which is a distributed constant circuit, is reduced, there is an advantage that the VCO circuit can be easily constructed only by the theory of the lumped constant circuit.

【0020】なお上述の実施例においては、デイジタル
コードレス電話のVCO回路を形成する場合について述
べたが、本発明はこれに限らず、VCO回路等の発振回
路以外の増幅回路等にも適用し得る。さらに、デイジタ
ル回路に限ることなくアナログ回路でも良く、要は広く
一般に高周波用の回路を形成するものに適用し得、これ
により上述した実施例と同様の効果を得ることができ
る。さらに広く一般に高周波回路以外の回路にも適用し
得る。また上述の実施例においては、高周波回路の形成
された部品面に対面するアース層の導体パターンの一部
をくり抜いて絶縁領域とした場合について述べたが、本
発明はこれに限らず、例えば高周波回路の形成された領
域に対面するアース層のくり抜き部分にプリント配線板
の材料であるエポキシ樹脂等の絶縁性の材料を充填する
ようにしても良い。
In the above embodiment, the case where the VCO circuit of the digital cordless telephone is formed has been described, but the present invention is not limited to this, and can be applied to an amplifier circuit other than the oscillation circuit such as the VCO circuit. . Further, the circuit is not limited to a digital circuit, but may be an analog circuit, and the point is that it can be widely applied to those which generally form a high-frequency circuit, and thereby the same effect as that of the above-described embodiment can be obtained. Further, it can be widely applied to circuits other than the high frequency circuit. Further, in the above-described embodiment, the case where a part of the conductor pattern of the earth layer facing the component surface on which the high frequency circuit is formed is hollowed out to form an insulating region, but the present invention is not limited to this and, for example, a high frequency The hollowed-out portion of the ground layer facing the area where the circuit is formed may be filled with an insulating material such as an epoxy resin which is a material for the printed wiring board.

【0021】また上述の実施例においては、表裏両面の
部品面を含めて4層に導体パターン層を積層したプリン
ト配線板を用いた場合について述べたが、本発明はこれ
に限らず、要は基板表面層を含めて二層以上のアース層
を設けた(すなわち片面実装型のものも含む)多層基板
に適用することによつて上述した実施例と同様の効果を
得ることができる。
Further, in the above-mentioned embodiment, the case where the printed wiring board in which the conductor pattern layers are laminated in four layers including the front and back surfaces of the components is used is described, but the present invention is not limited to this, and the essential point is. By applying the present invention to a multi-layered substrate provided with two or more ground layers including the substrate surface layer (that is, including a single-sided mounting type), the same effects as those of the above-described embodiments can be obtained.

【0022】[0022]

【発明の効果】上述のように本発明によれば、表面導体
層を含めて少なくとも三層以上の導体パターン層が互い
に絶縁層を挿んで積層されたプリント配線板において、
部品を実装するための回路パターンが形成された第1の
導体パターン層と、回路パターンとの対面部分に対応し
た絶縁領域を有する第2の導体パターン層と、該第2の
導体パターン層の第1の導体パターン層が形成された側
に対して反対側の面に対面し、アース接続されてなる第
3の導体パターン層とを備えたことにより、回路の形成
される第1の導体パターン層の回路パターンに対して第
3の導体パターン層を対面させるようにして導体パター
ン層間の間隔を拡げ、第1の導体パターン層上に形成さ
れる回路に対して容量性の不具合を生じさせるような浮
遊容量の層間での発生を未然に防止し得るプリント配線
板を実現し得る。
As described above, according to the present invention, in a printed wiring board in which at least three or more conductor pattern layers including a surface conductor layer are laminated with insulating layers interposed therebetween,
A first conductor pattern layer on which a circuit pattern for mounting components is formed, a second conductor pattern layer having an insulating region corresponding to a portion facing the circuit pattern, and a second conductor pattern layer of the second conductor pattern layer. A first conductor pattern layer on which a circuit is formed, by including a third conductor pattern layer facing the surface opposite to the side on which the first conductor pattern layer is formed and grounded. Such that the third conductor pattern layer faces the third circuit pattern layer and the space between the conductor pattern layers is expanded to cause a capacitive defect in the circuit formed on the first conductor pattern layer. It is possible to realize a printed wiring board that can prevent generation of stray capacitance between layers.

【図面の簡単な説明】[Brief description of drawings]

【図1】デイジタルコードレス電話の送受信部の回路構
成を示すブロツク図である。
FIG. 1 is a block diagram showing a circuit configuration of a transmission / reception unit of a digital cordless telephone.

【図2】実施例によるプリント配線板の構成を示す断面
図である。
FIG. 2 is a cross-sectional view showing a configuration of a printed wiring board according to an example.

【図3】従来のプリント配線板の構成を示す断面図であ
る。
FIG. 3 is a cross-sectional view showing a configuration of a conventional printed wiring board.

【符号の説明】[Explanation of symbols]

1、50……プリント配線板、2、3、51、52……
部品面、4、5、53、6……高周波回路、54……ア
ース層、6A……回路パターン、53A……絶縁領域。
1, 50 ... Printed wiring board, 2, 3, 51, 52 ...
Component surface 4, 5, 53, 6 ... High-frequency circuit, 54 ... Ground layer, 6A ... Circuit pattern, 53A ... Insulation area.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】表面導体層を含めて少なくとも三層以上の
導体パターン層が互いに絶縁層を挿んで積層されたプリ
ント配線板において、 部品を実装するための回路パターンが形成された第1の
上記導体パターン層と、 上記回路パターンとの対面部分に対応した絶縁領域を有
する第2の上記導体パターン層と、 上記第2の導体パターン層の上記第1の導体パターン層
が形成された側に対して反対側の面に対面し、アース接
続されてなる第3の上記導体パターン層とを具えること
を特徴とするプリント配線板。
1. A printed wiring board in which at least three or more conductor pattern layers including a surface conductor layer are laminated with an insulating layer interposed therebetween, and a first circuit pattern for mounting components is formed. A conductor pattern layer, a second conductor pattern layer having an insulating region corresponding to a portion facing the circuit pattern, and a side of the second conductor pattern layer on which the first conductor pattern layer is formed. And a third conductor pattern layer facing the surface on the opposite side and grounded, the printed wiring board.
【請求項2】上記絶縁層は、 上記回路パターンの形状に対応して形成されることを特
徴とする請求項1に記載のプリント配線板。
2. The printed wiring board according to claim 1, wherein the insulating layer is formed corresponding to the shape of the circuit pattern.
【請求項3】上記第2の導体パターン層は、アース接続
されていることを特徴とする請求項1に記載のプリント
配線板。
3. The printed wiring board according to claim 1, wherein the second conductor pattern layer is grounded.
JP8132815A 1996-04-30 1996-04-30 Printed wiring board Pending JPH09298347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8132815A JPH09298347A (en) 1996-04-30 1996-04-30 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8132815A JPH09298347A (en) 1996-04-30 1996-04-30 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH09298347A true JPH09298347A (en) 1997-11-18

Family

ID=15090226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8132815A Pending JPH09298347A (en) 1996-04-30 1996-04-30 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH09298347A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002152611A (en) * 2000-11-09 2002-05-24 Sony Corp Tuner device and receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002152611A (en) * 2000-11-09 2002-05-24 Sony Corp Tuner device and receiver

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