JPH09297991A - Synchronous semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To determine the operating timing of an output buffer by enabling an output control signal to be arbitrarily set by prescribed input signals to select an optimum pulse from among plural pluses of synchronizing clocks. SOLUTION: A data latching circuit 601 latches readout data S1 read out on data busses 119 to apply them to an output circuit 123. The circuit 123 is activated by an output control signal ϕa synchronized with a clock signal CLK and reads out the data S1 to output them in the form of data D0. In this case, a memory control signal generating circuit 125 and an output clock delay control circuit 607 are provided in this DRAM and the circuit 125 outputs a memory control signal S3 controlling the inside of the memory and a drive signal S4 by inputting signals CLK, the inverse of RAS and the inverse of CAS to be inputted from the outside. The circuit 607 receives signals CLK, the inverse of RAS, S4 and external input signals SEL0 and SEL1 to generate the output control signal ϕa controlling the output circuit 123 optimally by arbitrarily selecting the signals SEL0, SEL1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory, and more particularly to a synchronous dynamic random access memory (hereinafter referred to as DRAM) having a feature in output control.

[0002]

2. Description of the Related Art A conventional synchronous semiconductor memory is disclosed in Japanese Patent Laid-Open No.
No. 1-39295 and JP-A No. 62-275384. The synchronous semiconductor memory has a memory cell array. A decoder is connected to the input of this memory cell. A latch circuit and an output buffer are connected to the output of the memory cell array.

When reading data from the memory cell array, an address inputted from the outside is decoded by a decoder,
A memory cell in the memory cell array is selected. The data stored in the selected memory cell is temporarily latched by the latch circuit. After that, the data latched in synchronization with the synchronization clock is read out from the output buffer. In the above-mentioned synchronous static random access memory (hereinafter referred to as SRAM), since only one pulse of the synchronous clock is input to the output buffer during one memory access period, the read data is accurately output from the output buffer in synchronization with this pulse. can do.

On the other hand, in the DRAM, a plurality of continuous pulses of the synchronous clock are input to the output buffer during one memory access period. When the conventional synchronization method is applied to the DRAM, it is necessary to determine in advance which pulse of the synchronization clock the read data is output from the output buffer.

[0005]

However, in the DRAM, since an address is input and data is read or written during one memory access period, the timing of inputting read data to the latch circuit may be delayed. There is a nature. Therefore, the operation timing of the output buffer cannot be accurately controlled in the DRAM to which the conventional synchronization method is applied. An object of the present invention is to provide a synchronous DRAM that selects an optimum pulse from a plurality of pulses of a synchronous clock input to an output buffer during one memory access period and determines the operation timing of the output buffer. It is in.

[0006]

In a synchronous semiconductor memory according to the present invention, a memory cell array having a plurality of memory cells, a circuit for selecting a specific memory cell from the memory cells, and a memory cell are provided. A means for transferring data, a data output circuit for receiving data from the transfer means and outputting the received data in response to a control signal, a clock signal and an input signal, and synchronizing with the received clock signal, respectively. And a control signal generation circuit that generates a plurality of control signals having different timings, selects one of the plurality of control signals in response to the state of the received input signal, and outputs the selected control signal to the data output circuit.

[0007]

The control signal generating circuit outputs one of the plurality of control signals having different timings to the data output circuit according to the state of the input signal, so that the control signal having the optimum timing can be selected.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a synchronous DR showing an embodiment of the present invention.
It is a schematic block diagram of AM. This synchronous DRA
The M has an address input circuit 101 that receives addresses A0 to An input from the outside and outputs an X address and a Y address. Address input circuit 101
Is a latch circuit 103 for inputting addresses A0 to An in synchronization with the synchronization clock CLK, and the latch circuit 1
It is composed of an address buffer 105 which generates an X address and a Y address based on the output of 03. An X address decoder 107 and a Y address decoder 109 are connected to the output of the address buffer 105. The outputs of the X address decoder 107 and the Y address decoder 109 are
Memory cells (not shown) to which a plurality of word lines 111 and bit lines 113 are respectively connected are connected to a memory cell array 115 arranged in a matrix. A memory cell is connected to each intersection of the word line 111 and the bit line 113. X address decoder 107
Selects one word line among the plurality of word lines 111. The Y address decoder 109 has a plurality of bit lines 113.
Select one bit line inside.

The bit line 111 is connected to the data bus 119 via an input / output circuit 117 for reading / writing. The data bus 119 is connected to the data latch circuit 601. The data latch circuit 601 latches the read data read on the data bus 119. Then, the data latch circuit 601 latches the read data S1.
To the output circuit 123. The output circuit 123 is activated by the output control signal φa synchronized with the clock signal CLK, and outputs the read data S1 in the form of read data D0 to the outside. In this embodiment, the output circuit 123 is composed of an output buffer. In addition, the DRAM of this embodiment
Is provided with a memory control signal generation circuit 125 and an output clock delay control circuit 607. The memory control signal generation circuit 125 uses a clock signal CL input from the outside.
K, the row address strobe signal / RAS, and the column address strobe signal / CAS are input, and various memory control signals S3 and drive signals S4 for controlling the memory internal circuit are output. Memory control signal generation circuit 1
Reference numeral 25 denotes a latch circuit 131 that latches the row address strobe signal / RAS and the column address strobe signal / CAS in response to the clock signal CLK, and the output of the latch circuit 131, and receives the memory control signal S3 and the drive signal S4. And a signal generation circuit 133 that generates the signal. The drive signal S4 is sent to the output clock delay control circuit 607.

The output clock delay control circuit 607 has external input terminals 603 and 605. External input terminal 6
Reference numerals 03 and 605 are terminals for inputting external input signals SEL0 and SEL1 for designating a delay clock, respectively.
The output clock delay control circuit 607 controls the clock signal CL.
K, the row address strobe signal / RAS, the drive signal S4 from the memory control signal generating circuit 125, and the external input signals SEL0 and SEL1 are received, and the output circuit 12
An output control signal .phi.a for operating 3 is generated.

FIG. 2 is a circuit diagram showing a configuration example of the output clock delay control circuit 607 shown in FIG. The output clock delay control circuit 607 is composed of a shift register section 609 and a logic circuit section 611. The shift register unit 609 includes an inverter 613 that inverts the drive signal S4 that falls in synchronization with the fall of the row address strobe signal / RAS, and a row address strobe signal / RA.
A reset pulse generation circuit 615 that outputs a reset signal S8 having a one-shot pulse in synchronization with the fall and rise of S, and five flip-flops (hereinafter referred to as FF) that shift the output of the inverter 613 in synchronization with the clock signal CLK. ) 617, 619, 621, 623
And 625. The output of the inverter 613 is connected to the input of the first FF 617, and the first FF 61
The output of 7 is input to the second FF 619 and the second FF 61
The output of 9 is input to the third FF 621 and the third FF 62
The output of 1 is input to the input of the fourth FF 623, and the output of the fourth FF 62
The output of 3 is connected to the input of the fifth FF 625.
The output of the reset pulse generation circuit 615 is the first to fifth outputs.
Connected to the reset inputs of FFs 617-625. Further, the clock signal CLK is the first to fifth FFs.
It is input to timing inputs 617 to 625. The third, fourth, and fifth FFs 62 of the shift register unit 609
The outputs of 1, 623 and 625 are supplied to the logic circuit unit 611.

The logic circuit section 611 is a shift register section 6
This is a circuit that selects the falling timing of the output control signal φa by the combination of the output of 09 and the external input signals SEL0 and SEL1. The logic circuit unit 611 uses the external input signal S
First and second input terminals 603 and 605 for receiving EL0 and SEL1, respectively, and inverters 627 and 62
9, first, second and third NAND gates 631, 633 and 635 for signal selection, and these NAND gates 6
And a fourth NAND gate 637 which generates an output control signal φa from the outputs of 31, 633 and 635. The first external terminal 603 is connected to the first inputs of the first and second NAND gates 631 and 633, and is also connected to the first input of the third NAND gate 635 via the inverter 629. The second external terminal 605 is the first N
It is connected to the second input of the AND gate 631 and also connected to the second inputs of the second and third NAND gates 633 and 635 via the inverter 627. Third FF6
21 outputs to the third input of the third NAND gate 635, and the output of the fourth FF 623 outputs to the second NAND gate 6.
33 has a third input connected to the first N-th output of the fifth FF 625.
Each is connected to the third input of the AND gate 631.
First, second and third NAND gates 631, 633,
The output of 635 is connected to the first, second and third inputs of the fourth NAND gate 637.

FIG. 3 is an operation timing chart of the synchronous DRAM of FIG. 1. The operation of the synchronous DRAM of FIG. 1 will be described with reference to this figure. Around time t22,
The address input circuit 101 receives the X address 801 in the addresses A0 to An and the Y address 803 near time t23. After that, the clock signal C
The address buffer 10 is analogized independently of LK.
The X address and the Y address output from 5 are transferred to the X address decoder 107 and the Y decoder 109, respectively. The memory cell array 1 is output by the outputs of the X address decoder 107 and the Y address decoder 109.
The memory cell in 15 is selected. The stored data 805 of the selected memory cell is transferred to the data latch circuit 601 via the data bus 119 at time t25. On the other hand, the row address strobe signal / input to the shift register unit 609 of the output clock control circuit 607
RAS falls at time t21, and in response to this fall, reset pulse generation circuit 615 outputs reset signal S8 having a one-shot pulse. The reset signal S8 resets the first to fifth FFs 617 to 625 slightly later than the time t21 (in FIG. 3, the case where the outputs of all the FFs are at the "L" level is shown, so that the reset operation is a signal. Not shown above). Thereafter, drive signal S4 falls, and in response to this fall, output signal S4A of inverter 613 rises to "H" level. At a time t22 when the output signal S4A becomes "H" level and the first clock signal CLK rises, the output signal A of the first FF 617 changes from "L" level to "H" level in response to this rising. After that, at times t23, t24, t26 and t27, the output signals B to E of the second to fifth FFs 619 to 625 are output.
Each of them changes from "L" level to "H" level. After that, the row address strobe signal / RAS changes to time t28.
At the rising edge of the reset signal S, the reset pulse generation circuit 615 responds to the reset signal S having a one-shot pulse.
8 is output and the drive signal S4 also rises. Therefore, the output signal A of the inverter 613 changes from "H" level to "L" level. First to fifth FFs 61 to 625
The output signals A to E of the above are changed from "H" level to "L" level in response to the pulse of the reset signal S8.

Next, the operation of the logic circuit section 611 of the output clock delay control circuit 607 will be described. Note that this operation is explained in the case where the external input signal SEL0 is "H" level, SEL
1 is "L" level (see FIG. 3A), both external input signals SEL0 and SEL1 are "L" level (see FIG. 3B), and external input signals SEL0 and SEL1.
In both cases, the case of "H" level (see FIG. 3C) will be described separately.

In the case of FIG. 3A, when the external input signal SEL0 is at "H" level and SEL1 is at "L" level, the outputs of the first NAND gate 631 and the third NAND gate 635 are shift register units. It is at "L" level regardless of the output of 609. on the other hand,
The output of the second NAND gate 633 is the output of the fourth FF 62.
The output signal D of 3 is output as it is. Therefore, the fourth N
Output control signal φa which is the output signal of AND gate 637
Becomes the output signal D of the fourth FF 623, and becomes the time t26.
Rises, and falls at time t28. This is explained by Table 1 below, which shows the signal levels of the inputs and outputs of the first to fourth NAND gates 631 to 637.

【table 1】

Output circuit 123 outputs read data D0 (805) in response to output control signal φa with a delay of a predetermined delay time Ta from time t26.

In the case of FIG. 3B, when the external input signal SEL0 is at "L" level and SEL1 is at "L" level, the outputs of the first NAND gate 631 and the second NAND gate 633 are shift register units. It is at "L" level regardless of the output of 609. on the other hand,
The output of the third NAND gate 635 is the output of the third FF 62.
The output signal C of 1 is output as it is. Therefore, the fourth N
Output control signal φa which is the output signal of AND gate 637
Becomes the output signal C of the third FF 621, and the output control signal φa rises at time t24 and falls at time t28. This is illustrated by Table 2 below.

[Table 2]

The output circuit 123 tries to output the read data D0 (805) in response to the output control signal φa, but at time t24, the output circuit 123 reads the read output D0.
(805) is not yet latched. Therefore, the read data D is delayed by a time Tb longer than the predetermined delay time Ta.
Outputs 0.

In the case of FIG. 3C, when the external input signal SEL0 is at "H" level and SEL1 is at "H" level, the outputs of the second NAND gate 633 and the third NAND gate 635 are shift register units. It is at "L" level regardless of the output of 609. on the other hand,
The output of the first NAND gate 631 is the fifth FF 62
The output signal E of 5 is output as it is. Therefore, the fourth N
Output control signal φa which is the output signal of AND gate 637
Becomes the output signal E of the fifth FF 625, and the output control signal φa rises at time t27 and falls at time t28. This is illustrated by Table 3 below.

[Table 3]

The output circuit 123 responds to the output control signal φa and delays the read data D0 by a predetermined delay time Ta.
(805) is output.

In the case of FIG. 3B, since the read data D0 has not yet been sent to the data latch circuit 601 when the output control signal φa rises, the data output of the output circuit 123 from the rising time t24 of the clock signal CLK. It will take time Tb by the time. On the other hand, in the cases of (a) and (c) of FIG. 3, since the read data D0 has already been latched in the data latch circuit 601 when the output control signal φa rises, the rising time t26 of the clock signal CLK.
Alternatively, the output circuit 123 can output the read data D0 after a delay of a predetermined delay time Ta from t27.

Comparing the three cases described above, in the case of FIG. 3B, the row address strobe signal / RAS is generated.
Although the time from the fall time t21 to the start of access is fast, the access start from the rise of the clock signal CLK is slow. In the case of FIG. 3C, the time from the rise time t21 of the row address strobe signal / RAS to the start of access is delayed. Therefore, it can be said that the case of FIG. 3A is the case where the optimum output control signal φa is generated. Therefore, if the external input signal SEL0 is set to "H" level and SEL1 is set to "L" level, the output control signal φa output from the output clock delay control circuit 607 causes the output circuit 123 to output the read data D0, and Synchronization operation is obtained. The DRA having the same configuration as that of this embodiment
Even in M, if the transfer rate of read data from the memory cell array 115 to the data latch circuit 601 is high due to manufacturing variations, the case of FIG. 3B may be the optimum synchronous operation.

[0023]

As described above in detail, in the DRAM of the present invention, the output control signal can be arbitrarily set by a predetermined input signal or the like. Also, the read data from the memory can be output in synchronization with the optimum clock pulse.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a synchronous DRAM showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of an output clock delay control circuit shown in FIG.

3 is an operation timing chart of the synchronous DRAM of FIG.

[Explanation of symbols]

 101 ... Address input circuit 107 ... X address decoder 109 ... Y address decoder 111 ... Word line 113 ... Bit line 115 ... Memory cell array 117 ... Input / output circuit 123 ... Output circuit 125 ... Memory control signal generation circuit 601 ... Data latch circuit 603, 605 ... External input terminal

Claims (5)

[Claims] 1. A memory cell array having a plurality of memory cells, a circuit connected to the memory cell array for selecting a specific memory cell from the plurality of memory cells, and a memory cell connected to the memory cell array. And a data output circuit connected to the transfer means for receiving the data from the transfer means and outputting the received data in response to a control signal, and a clock signal and an input signal. A data output circuit that generates a plurality of control signals having different timings in synchronization with the received clock signal and selects one of the plurality of control signals in response to the state of the received input signal. A synchronous semiconductor memory having a control signal generating circuit for outputting to. 2. The control signal generation circuit receives the clock signal, the first and second address strobe signals, and generates a plurality of internal control signals, the input signal, the clock signal, and the memory control signal generation circuit. 2. The synchronous semiconductor memory according to claim 1, further comprising an output clock delay control circuit which receives one of the plurality of internal control signals and outputs the control signal to the data output circuit. 3. The output clock delay control circuit receives a control signal from the clock signal and one of the plurality of internal control signals, and generates a plurality of the control signals, and a plurality of control signals. 3. The synchronous semiconductor memory according to claim 2, further comprising: an output selection unit that receives and selects one of the plurality of control signals in response to a state of an input signal and outputs the selected control signal to a data output circuit. 4. The synchronous semiconductor memory according to claim 3, wherein the control signal generator includes a flip-flop. 5. The synchronous semiconductor memory according to claim 3, wherein the output selection unit has a plurality of gate circuits.