JPH09297966A - Digital signal reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the degradation of an error rate caused by a phase locked loop. SOLUTION: A S/N calculating circuit 21 calculates S/N of a reproduced signal b1 from a pre-amplifier 13, and supplies a data signal e1 of this calculated result to a control circuit 22. When S/N indicated by the data signal e1 is improved, the control circuit 22 supplies a control signal f1 indicating that DC gain is switched to the higher according to the above to a DC gain switching circuit 23, When S/N indicated by the data signal e1 is lowered, the control circuit 22 supplies a control signal f1 indicating that DC gain is switched to the lower according to the above to a DC gain switching circuit 23. The DC gain switching circuit 23 switches DC gain of a PLL 117 based on the control signal f1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing apparatus for reproducing a digital signal from a recording medium, and more particularly to a digital signal reproducing apparatus capable of improving an error rate.

[0002]

2. Description of the Related Art In recent years, a digital signal reproducing apparatus for reproducing a digital signal from a recording medium has been widely used for a data recording apparatus such as a computer and a digital video tape recorder.

FIG. 14 is a block diagram showing an example of such a conventional digital signal reproducing apparatus.

In FIG. 14, reference numeral 301 is a magnetic tape on which a digital code is recorded.
Is reproduced by the head 302. A reproduction signal a21 reproduced from the magnetic tape 301 by the head 302 is amplified by a preamplifier 303 and supplied to an automatic gain control circuit (hereinafter referred to as AGC) 304 as a reproduction signal b21. The AGC 304 absorbs the amplitude fluctuation of the reproduction signal b21 and supplies it as the reproduction signal c21 to the waveform equalization circuit 305. The waveform equalization circuit 305 equalizes the waveform of the reproduction signal c21 and supplies it as a reproduction signal d21 to the identification circuit 306 and a phase locked loop (hereinafter referred to as PLL) 307. The PLL 307 extracts a clock signal e1 which is a reference for signal processing from the supplied reproduction signal d21 and supplies it to the identification circuit 306 and the output terminal 308.
The discrimination circuit 306 outputs the reproduction signal d from the waveform equalization circuit 305.
21 is identified by using the clock signal e1 from the PLL 307 to obtain the reproduced digital signal f21 and output terminal 3
Lead to 09.

In recent years, various methods have been used to improve the reproduction error rate in response to a demand for higher recording density on the recording medium. Viterbi decoding is one of the methods.

FIG. 15 is a block diagram showing a digital signal reproducing apparatus using such Viterbi decoding.

In FIG. 15, interleaved NRZI is used as the digital code stored in the magnetic tape 321. The magnetic tape 321 is reproduced by the head 322. The reproduction signal a22 reproduced from the magnetic tape 321 by the head 322 is the preamplifier 323 and AGC3.
24, an analog / digital conversion circuit (hereinafter referred to as an A / D conversion circuit) as d22 via the waveform equalization circuit 325.
326 and PLL327. PLL327
Extracts a clock signal e2, which is a reference for signal processing, from the supplied reproduction signal d22 and supplies the clock signal e2 to the A / D conversion circuit 326 and the Viterbi decoding circuit 328 and an output terminal 329.
Lead to. The A / D conversion circuit 326 samples the reproduction signal d22 from the waveform equalization circuit 325 using the clock signal e2 from the PLL 327, converts it into an 8-bit digital signal f22, and supplies it to the Viterbi decoding circuit 328.
The Viterbi decoding circuit 328 performs Viterbi decoding of the interleaved NRZI on the digital signal f22 to obtain a reproduced digital signal g22 and guides it to the output terminal 330.

By using such a Viterbi decoding circuit 328, the reproduction error rate can be improved.

Here, generally, the error rate of the digital signal reproducing apparatus is almost determined by the error generated by the noise contained in the reproduced signal when the reproduced S / N (signal to noise ratio) is bad. However, when the reproduction S / N is improved to some extent, errors due to noise are reduced, so that the PLL
Of the identification timing due to the residual phase error of the
The influence of the error that occurs due to the variation of the identification timing due to the clock jitter of cannot be ignored. Play S
When / N is further improved, errors caused by these PLLs become a dominant factor.

The residual phase error and clock jitter of the PLL have a great influence on the effect of improving the error rate of Viterbi decoding. In Viterbi decoding, the system is configured assuming that the noise included in the reproduced signal is Gaussian noise as described above. However, if the timing of the A / D conversion deviates from the optimum phase due to the PLL, the data after the A / D conversion has a variation with a special habit.
This is equivalent to the fact that a noise component other than Gaussian noise is multiplexed in the reproduced signal, and breaks the preconditions for Viterbi decoding. The influence of such a timing shift of the A / D conversion will be described with reference to FIGS.

FIG. 16 shows a reproduction signal d22 immediately before A / D conversion.
17 shows the eye pattern, FIG. 17 shows the data variation when there is no A / D conversion timing deviation, and FIG. 18 shows the data variation when there is no A / D conversion timing deviation.

In FIG. 16, the eye pattern of the reproduced signal d22 is an eye pattern when the signal recorded by the interleaved NRZI is reproduced by the partial response (Class 4).

A / D at timing T21 shown in FIG.
When conversion is performed, there is no deviation from the optimum phase, and the variation in data due to sampling becomes a variation close to a normal distribution, as shown in FIG.

A / D at timing T22 shown in FIG.
When converting, there is a deviation from the optimum phase,
The variation in data due to sampling is completely different from the normal distribution as shown in FIG. 18, and in addition, the variation is much larger than that in FIG. With such variations, the original error correction capability of Viterbi decoding cannot be exhibited.

In order to reduce the residual phase error of the PLL, the DC gain of the PLL may be set large. However, if a large DC gain is set in an actual digital signal reproducing device, the stability of the PLL at low S / N is impaired, and the DC gain cannot be set too high unnecessarily.

Further, in order to reduce the clock jitter of the PLL, the purity of the oscillation frequency of the voltage control oscillator in the PLL may be set high. However, also in the actual digital signal reproducing apparatus, the tracking performance of the PLL at the time of low S / N is impaired, so that it cannot be set unnecessarily high.

In the above digital signal reproducing apparatus, high S /
The PLL must be designed in consideration of the balance between the performance at N time and the performance at low S / N, and the error rate deterioration caused by the PLL cannot be avoided. Further, even when the Viterbi decoding is adopted, there is a problem that the error rate improving performance cannot be exhibited due to the PLL.

[0018]

In such a conventional digital signal reproducing apparatus, the phase locked loop must be designed in consideration of the performance balance at the time of high signal noise ratio and at the time of low signal noise ratio. The deterioration of the error rate caused by droop was unavoidable. Further, even when the Viterbi decoding is adopted, there is a problem that the error rate improving performance cannot be exhibited due to the phase locked loop.

Therefore, an object of the present invention is to provide a digital signal reproducing apparatus which can eliminate the above-mentioned drawbacks and reduce the deterioration of the error rate caused by the phase locked loop.

[0020]

According to a first aspect of the present invention, there is provided a digital signal reproducing apparatus for reproducing a recording medium on which a digital code is recorded to obtain a reproduced signal, and a signal noise ratio of the reproduced signal from the reproducing means. And a phase-locked loop for extracting a clock signal serving as a reference for signal processing from the reproduction signal from the reproduction means, and a reproduction signal from the reproduction means to the clock signal from the phase-locked loop. If the calculation result of the signal noise ratio of the discrimination circuit for obtaining a reproduced digital signal by discriminating using, and the signal noise ratio calculation means becomes high, the DC gain of the phase locked loop is switched to a higher one accordingly, And a control circuit for switching the DC gain of the phase-locked loop to a lower one when the calculation result of the signal noise ratio becomes lower. To.

According to a second aspect of the digital signal reproducing apparatus of the present invention,
Reproducing means for reproducing a recording medium on which a digital code is recorded to obtain a reproduced signal, signal noise ratio calculating means for calculating a signal noise ratio of the reproduced signal from the reproducing means, and signal processing from the reproduced signal from the reproducing means. A phase locked loop for extracting a clock signal serving as a reference, a discrimination circuit for obtaining a reproduced digital signal by discriminating the reproduced signal from the reproducing means using the clock signal from the phase locked loop, and the signal noise ratio. If the calculation result of the signal-noise ratio of the calculation means becomes high, the purity of the oscillation frequency of the voltage-controlled oscillator of the phase locked loop is switched to a higher one accordingly, and if the calculation result of the signal-noise ratio becomes low, accordingly And a control circuit for switching the purity of the oscillation frequency of the voltage-controlled oscillator of the phase locked loop to a lower one.

According to a third aspect of the digital signal reproducing apparatus of the present invention,
Reproducing means for reproducing a recording medium on which a digital code is recorded to obtain a reproduced signal, signal noise ratio calculating means for calculating a signal noise ratio of the reproduced signal from the reproducing means, and signal processing from the reproduced signal from the reproducing means. A phase locked loop for extracting a clock signal serving as a reference, a discrimination circuit for obtaining a reproduced digital signal by discriminating the reproduced signal from the reproducing means using the clock signal from the phase locked loop, and the signal noise ratio. If the calculation result of the signal-to-noise ratio of the calculation means becomes high, the DC gain of the phase-locked loop and the purity of the oscillation frequency of the voltage-controlled oscillator of the phase-locked loop are switched to the higher one accordingly, and If the calculation result becomes low, the DC gain of the phase-locked loop and the oscillation frequency of the voltage-controlled oscillator of the phase-locked loop will be changed accordingly. And a control circuit for switching the degree to lower,
Is provided.

According to a fourth aspect of the digital signal reproducing apparatus,
The digital signal reproducing apparatus according to any one of claims 1 to 3, wherein the discriminating circuit performs an analog / digital converting circuit for converting the reproduced signal into an analog / digital signal, and a digital signal from the analog / digital converting circuit. And a Viterbi decoding circuit for performing Viterbi decoding by using.

According to a fifth aspect of the digital signal reproducing apparatus,
The digital signal reproducing apparatus according to any one of claims 1 to 4, wherein the signal-noise-ratio calculating means reproduces an envelope of a reproduced signal reproduced from the recording medium and not subjected to automatic gain control. It is characterized by comprising an envelope detection circuit that outputs amplitude information and a signal-noise ratio conversion circuit that converts the signal-noise ratio by multiplying the amplitude information from the envelope detection circuit by a predetermined constant.

According to a sixth aspect of the digital signal reproducing apparatus,
The digital signal reproducing apparatus according to claim 4, wherein an error between a reproduction signal amplitude value and a standard value indicated by a digital signal from the analog / digital conversion circuit, which is a constituent element of the signal noise ratio calculating means, is a predetermined value. And a condition judging circuit for comparing the signal and noise ratio calculating means, which is a constituent element of the signal noise ratio calculating means, and accumulates the error only when the comparison result of the condition judging circuit satisfies a predetermined condition, and the signal noise ratio calculation And a signal-to-noise ratio conversion circuit for converting the signal-to-noise ratio by multiplying the integration result of the integration circuit by a predetermined constant.

According to a seventh aspect of the digital signal reproducing apparatus,
5. The digital signal reproducing apparatus according to claim 4, which is a constituent element of the signal noise ratio calculating means, wherein a difference between a reproduction signal amplitude value and a standard value indicated by a digital signal from the analog / digital converting circuit is predetermined. A condition judging circuit for comparing with a value, a component of the signal-noise ratio calculating means, and an integrating circuit for accumulating the reproduction signal amplitude value only when the comparison result of the condition judging circuit satisfies a predetermined condition, A signal-to-noise ratio conversion circuit, which is a component of the signal-to-noise ratio calculation means, converts the signal-to-noise ratio by multiplying the integration result of the integration circuit by a predetermined constant.

According to the constitutions of claims 1, 3 to 7,
The control circuit, if the calculation result of the signal noise ratio of the signal noise ratio calculating means becomes high, the DC gain of the phase locked loop is switched to a higher one accordingly, and if the calculation result of the signal noise ratio becomes low, Since the DC gain of the phase locked loop is switched to the lower one, it is possible to reduce the error rate deterioration caused by the phase locked loop.

According to the present invention, when the control circuit raises the calculation result of the signal noise ratio of the signal noise ratio calculating means, the oscillation of the voltage controlled oscillator of the phase locked loop is accordingly generated. Switch to higher frequency purity,
If the calculation result of the signal-to-noise ratio becomes low, the purity of the oscillation frequency of the voltage-controlled oscillator of the phase locked loop is switched to the lower one, so that the deterioration of the error rate caused by the phase locked loop can be reduced.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a digital signal reproducing apparatus according to the present invention.

In FIG. 1, reference numeral 11 is a magnetic tape on which a digital code is recorded, and this magnetic tape 11 is reproduced by a head 12. A reproduction signal a1 reproduced from the magnetic tape 11 by the head 12 is amplified by a preamplifier 13 and is reproduced as a reproduction signal b1 by an automatic gain control circuit (hereinafter, referred to as AGC) 14 and a signal-to-noise ratio calculation circuit (hereinafter, S / N). (Referred to as a calculation circuit) 21. AGC
Reference numeral 14 absorbs the amplitude fluctuation of the reproduction signal b1 and reproduces the reproduction signal c1.
Is supplied to the waveform equalization circuit 15. Waveform equalization circuit 15
Is equalized to the waveform of the reproduction signal c1 and supplied to the identification circuit 16 and the phase locked loop (hereinafter referred to as PLL) 17 as the reproduction signal d1. The S / N calculation circuit 21 calculates the S / N of the reproduction signal b1 from the preamplifier 13 and supplies the data signal e1 of this calculation result to the control circuit 22. When the S / N indicated by the data signal e1 becomes high, the control circuit 22 supplies the control signal f1 indicating that the DC gain is switched to the higher one accordingly, to the DC gain switching circuit 23, and the S / N indicated by the data signal e1 is supplied. When N decreases, the control signal f1 indicating that the DC gain is switched to the lower one is supplied to the DC gain switching circuit 23 accordingly.

The DC gain switching circuit 23 switches the DC gain of the PLL 17 based on the control signal f1.

The PLL 17 extracts the clock signal g1 which is a reference for signal processing from the supplied reproduction signal d1 and supplies it to the discrimination circuit 16 while the DC gain is switched by the DC gain switching circuit 23, and supplies it to the discrimination circuit 16 and an output terminal. Lead to 18. The discrimination circuit 16 uses the reproduction signal d from the waveform equalization circuit 15.
1 is identified by using the clock signal g1 from the PLL 17 to obtain reproduced digital data h1 and output terminal 19
Lead to.

The operation of the embodiment of the invention will be described below.

When the S / N (signal-to-noise ratio) of the reproduced signal is good, the S / N indicated by the data signal e1 becomes high, and the S / N calculation circuit 21 switches the DC gain to the higher one. The control signal f1 shown is supplied to the DC gain switching circuit 23. As a result, the PLL 17 has a high DC gain, and the discrimination circuit 16 discriminates the reproduction signal d1 from the waveform equalization circuit 15 using the clock signal g1 having a small residual phase error to obtain the reproduction digital data h1 and outputs it. Lead to terminal 19.

When the S / N (signal-to-noise ratio) of the reproduced signal is bad, the S / N indicated by the data signal e1 becomes a low value, and the S / N calculation circuit 21 switches the DC gain to the lower one. The control signal f1 shown is supplied to the DC gain switching circuit 23. This causes the PLL 17 to have a low DC gain, and the discrimination circuit 16 discriminates the reproduction signal d1 by using the clock signal g1 having high stability to obtain the reproduction digital data h1 and guide it to the output terminal 19.

According to this embodiment of the invention, when the S / N of the reproduced signal is high (when it is good), the DC gain of the PLL is automatically increased and the residual phase error is reduced. Even if the frequency fluctuates, it becomes possible to keep the identification phase by the clock signal g1 from the PLL near the optimum value. Therefore, it is possible to improve the error rate when the reproduction frequency changes during special reproduction. When the S / N of the reproduced signal is low (bad), P
Since the DC gain of the LL becomes small, the stability of the PLL can be kept good and the error rate can be kept good. In this way, the PLL is adjusted according to the S / N of the reproduced signal.
Keeps the optimum characteristics of, and reproduce signal S / N in a wide range.
The error rate can be improved according to As a result, the deterioration of the error rate caused by the phase locked loop can be reduced, so that the digital signal reproducing apparatus can be used to improve the performance of the apparatus and increase the recording density of the magnetic tape (recording medium).

FIG. 2 is a block diagram showing a second embodiment of the digital signal reproducing apparatus according to the present invention. The same components as those in FIG. 1 are designated by the same reference numerals and their description is omitted. There is.

In FIG. 2, when the S / N indicated by the data signal e1 from the S / N calculation circuit 21 becomes high, the control circuit 32 follows the voltage control oscillator of the PLL 37 (hereinafter,
(Hereinafter referred to as VCO), the control signal f2 indicating that the purity Q of the oscillation frequency of the VCO) is switched to the higher one is supplied to the purity switching circuit 33, and if the S / N indicated by the data signal e1 becomes low, the purity Q becomes lower accordingly. Control signal f2 indicating switching to
Is supplied to the purity switching circuit 33.

The purity switching circuit 33 switches the purity Q of the VCO oscillation frequency of the PLL 37 based on the control signal f2.

The PLL 37 is set to V by the purity switching circuit 33.
With the purity Q of the oscillation frequency of CO being switched and selected, a clock signal g2 serving as a reference for signal processing is extracted from the supplied reproduction signal d1 and supplied to the discrimination circuit 16 and also led to the output terminal 18. The discrimination circuit 16 uses the reproduction signal d1 from the waveform equalization circuit 15 as the clock signal g2 from the PLL 37.
The reproduced digital data h2 is obtained by performing identification by using, and is guided to the output terminal 19.

According to this embodiment of the invention, when the S / N of the reproduced signal is good, the VC of the PLL is automatically
Since the purity Q of the O oscillation frequency is increased and the clock jitter is reduced, it is possible to keep the identification phase by the clock signal g1 from the PLL near the optimum value. Therefore, the error rate can be improved. Further, when the S / N of the reproduced signal is bad, the purity Q of the oscillation frequency of the VCO of the PLL is automatically reduced, so that the tracking of the PLL can be kept good and the error rate in this case is also good. Can be kept at As described above, the characteristics of the PLL can always be optimized according to the S / N of the reproduction signal, and the error rate can be improved according to the S / N of the reproduction signal in a wide range. It is possible to obtain the same effect as that of the above embodiment.

FIG. 3 is a block diagram showing a third embodiment of the digital signal reproducing apparatus according to the present invention. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. There is.

In FIG. 3, the S / N calculation circuit 41 calculates the S / N of the reproduction signal b1 from the preamplifier 13, and the data signal e3 of this calculation result is sent to the DC gain control circuit 42 and the purity switching circuit 43. Supply. When the S / N indicated by the data signal e3 becomes high, the DC gain control circuit 42 supplies the DC gain switching circuit 44 with the control signal i3 indicating that the DC gain is switched to the higher side accordingly, and the data signal e
When the S / N indicated by 3 becomes low, the control signal i3 indicating that the DC gain is switched to the lower one is supplied to the DC gain switching circuit 44 accordingly.

The DC gain switching circuit 44 switches the DC gain of the PLL 47 based on the control signal i3.

The purity control circuit 43 includes the S / N calculation circuit 4
If the S / N indicated by the data signal e3 from 1 becomes higher, the control signal j3 indicating that the purity Q of the oscillation frequency of the voltage control oscillator (hereinafter referred to as VCO) of the PLL 47 is switched to the higher one accordingly. If the S / N indicated by the data signal e3 supplied to the switching circuit 45 becomes low, the purity Q
Is supplied to the purity switching circuit 45, which indicates that the control signal j3 is switched to the lower one.

The purity switching circuit 45 switches the purity Q of the VCO oscillation frequency of the PLL 47 based on the control signal j3.

In the PLL 47, the DC gain switching circuit 23 selects and switches the DC gain and the purity switching circuit 45.
With the purity Q of the oscillation frequency of the VCO being switched and selected, the clock signal g3 serving as a signal processing reference is extracted from the supplied reproduction signal d1, supplied to the discrimination circuit 16 and guided to the output terminal 18. The discrimination circuit 16 discriminates the reproduction signal d1 from the waveform equalization circuit 15 using the clock signal g3 from the PLL 47 to obtain reproduction digital data h3 and leads it to the output terminal 19.

According to the embodiment of the invention as described above, the effects of both the embodiment of the invention of FIG. 1 and the embodiment of the invention of FIG. 2 can be obtained.

FIG. 4 is a block diagram showing a fourth embodiment of the digital signal reproducing apparatus according to the present invention.

In FIG. 4, interleaved NRZI is used as the digital code recorded on the magnetic tape 51. The magnetic tape 51 is reproduced by the head 52.
The reproduction signal a4 reproduced from the magnetic tape 51 by the head 52 is amplified by the preamplifier 53 and supplied to the AGC 54 and the S / N calculating circuit 61 as the reproduction signal b4.
The AGC 54 absorbs the amplitude fluctuation of the reproduction signal b4 and supplies it to the waveform equalizing circuit 55 as the reproduction signal c4. The waveform equalization circuit 55 equalizes the waveform of the reproduction signal c4 and reproduces the reproduction signal d4.
Is supplied to an analog / digital conversion circuit (hereinafter referred to as an A / D conversion circuit) 56 and a PLL 57. The S / N calculation circuit 61 calculates the S / N ratio of the reproduction signal b4 from the preamplifier 53.
N is calculated, and the data signal e4 of the calculation result is supplied to the control circuit 62. When the S / N indicated by the data signal e4 becomes high, the control circuit 62 supplies a control signal f4 indicating that the DC gain is switched to a higher one accordingly, and the S / N indicated by the data signal e4 is supplied. If the value becomes low, the control signal f4 indicating that the DC gain is switched to the lower one is supplied to the DC gain switching circuit 63 accordingly.

The DC gain switching circuit 63 switches the DC gain of the PLL 57 based on the control signal f4.

The PLL 57 extracts the clock signal g4, which is a reference for signal processing, from the supplied reproduction signal d4 while the DC gain is switched and selected by the DC gain switching circuit 63, and the A / D conversion circuit 56 and the Viterbi decoding are performed. The voltage is supplied to the circuit 58 and is also led to the output terminal 59. A / D conversion circuit 56
Performs sampling of the reproduction signal d4 from the waveform equalization circuit 55 using the clock signal g4 from the PLL 57 and 8b
Viterbi decoding circuit 58 by converting it into a digital signal h4
To supply. The Viterbi decoding circuit 58 uses the digital signal h4.
Is subjected to Viterbi decoding of interleaved NRZI to obtain reproduced digital data i4 and lead it to the output terminal 60.
The A / D conversion circuit 56 and the Viterbi decoding circuit 58 form an identification circuit that performs Viterbi decoding.

According to the embodiment of the invention as described above, when the S / N of the reproduced signal is good, the DC gain of the PLL automatically increases and the residual phase error decreases, so that the reproduced frequency fluctuates. Even if the clock signal g4 from the PLL causes A
It is possible to keep the A / D conversion timing (sampling timing) of the / D conversion circuit 56 near the optimum value. This means that the variation of the digital signal h4 input to the Viterbi decoding circuit 58 becomes small, and the variation distribution also approaches the normal distribution. Therefore, the error correction capability of Viterbi decoding can be maximized, and the error rate is further improved. Further, when the S / N ratio of the reproduction signal b4 deteriorates, the DC gain of the PLL automatically decreases, so that the stability of the PLL is kept good. In this way, the characteristics of the PLL are always kept optimum in accordance with the input signal S / N, and a greater performance improvement is possible in the S / N of all reproduced signals. Even when Viterbi decoding is performed, the invention of FIG. It is possible to obtain the same effect as that of the above embodiment.

FIG. 5 shows S / of the digital signal reproducing apparatus of FIG.
3 is a block diagram showing a configuration example of an N calculation circuit 21. FIG.

In FIG. 5, the S / N calculation circuit 21 is composed of an envelope detection circuit 24 and an S / N conversion circuit 25. The envelope detection circuit 24 is the preamplifier 1
3 performs envelope detection of the reproduction signal b1 from S.3 and outputs the data signal k1 indicating the amplitude information of the reproduction envelope to the S / N ratio.
It is supplied to the conversion circuit 25. The S / N conversion circuit 25 converts the S / N value by multiplying the amplitude information indicated by the data signal k1 by a predetermined constant, and supplies the resulting data signal e1 to the control circuit 22. Here, since the noise amount included in the reproduction signal b1 is substantially constant, the S / N value can be obtained by multiplying the amplitude information of the reproduction signal b1 by a predetermined constant.

According to such a configuration example, the control system related to the PLL does not have a loop configuration, so that high speed control is possible.

The configuration example shown in FIG. 5 can also be applied to the S / N calculation circuits shown in FIGS.

FIG. 6 is a block diagram showing a fifth embodiment of the digital signal reproducing apparatus according to the present invention. The same components as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 6, the Viterbi decoding circuit 71 is
The data signal m5 indicating the error between the reproduction signal amplitude value indicated by the digital signal h5 from the / D conversion circuit 70 and the standard value is S /
It is supplied to the N calculation circuit 72. The S / N calculation circuit 72 calculates and calculates the S / N of the reproduction signal d4 from the waveform equalization circuit 55 based on the data signal m5 from the Viterbi decoding circuit 71, and the data signal n5 of this calculation result is supplied to the control circuit 73. Supply to. The control circuit 73 controls the S / N indicated by the data signal n5.
Is higher, the control signal p5 indicating that the DC gain is switched to the higher one is supplied to the DC gain switching circuit 74, and if the S / N indicated by the data signal n5 is lower, the lower the DC gain is accordingly. Control signal p indicating switching to
5 is supplied to the DC gain switching circuit 74.

The DC gain switching circuit 74 switches the DC gain of the PLL 75 based on the control signal p5.

The PLL 75 extracts the clock signal g5, which is a reference for signal processing, from the supplied reproduction signal d4 in a state where the DC gain is switched and selected by the DC gain switching circuit 74, and the A / D conversion circuit 70 and the Viterbi decoding are performed. The voltage is supplied to the circuit 71 and is also led to the output terminal 59. A / D conversion circuit 70
Reproduces the reproduced signal d4 from the waveform equalizing circuit 55 using the clock signal g5 from the PLL 75 to convert it into a digital 8-bit digital signal h5 and supplies it to the Viterbi decoding circuit 71. The Viterbi decoding circuit 71 performs Viterbi decoding of the interleaved NRZI on the digital signal h5 to obtain reproduced digital data i5 and outputs it to the output terminal 6
Lead to 0.

According to such an embodiment of the invention, when the S / N of the reproduction signal d4 is good, the DC gain of the PLL automatically increases and the residual phase error decreases, so that the reproduction frequency fluctuates. Even in this case, however, it is possible to keep the A / D conversion timing of the A / D conversion circuit 70 by the clock signal g5 from the PLL near the optimum value. Also, the reproduction signal d4
If the S / N ratio is deteriorated, the DC gain of the PLL is automatically reduced, so that the stability of the PLL is kept good. As a result, the same effect as that of the embodiment of the invention shown in FIG. 4 can be obtained.

FIG. 7 is a block diagram showing the Viterbi decoding circuit 71 of FIG. 6 in more detail.

In FIG. 7, the input terminals 81 and 82 are connected to
The digital signal h5 from the A / D conversion circuit 70,
The clock signal g5 from the PLL 64 is guided.

The timing of the demultiplexer 83 is controlled by the clock signal g5 from the input terminal 82, the data of the digital signal h5 from the input terminal 81 is separated into an odd series and an even series, and the separated odd series digital signal r5. Is supplied to the first sub-Viterbi decoding circuit 85, and the separated even series digital signal s5 is supplied to the second sub-Viterbi decoding circuit 86.

The frequency divider 84 frequency-divides the clock signal g5 from the input terminal 82 by ½ to generate a clock signal t5 which rises to a high level at the input timing of the odd-numbered series of data of the clock signal g5. Then, the clock signal g5 is supplied to the first sub-Viterbi decoding circuit 85.
The clock signal u5 that rises to a high level at the input timing of the even-numbered series of data is generated and supplied to the second sub-Viterbi decoding circuit 86. In this way, the digital signal h5 from the input terminal 81 is separated into an odd series and an even series to convert the interleaved NRZI into a normal NRZI. First and second sub-Viterbi decoding circuit 8
Reference numerals 5 and 86 are Viterbi decoding circuits that perform NRZI Viterbi decoding. The first sub-Viterbi decoding circuit 85 outputs N signals based on the clock signal t5 with respect to the digital signal r5.
Viterbi decoding of RZI is performed to obtain a digital signal v5 and the digital signal v5 is supplied to the multiplexer 87, and the A / D conversion circuit 7
The S / N calculation circuit 72 calculates the data signal m5 indicating the error between the reproduction signal amplitude value indicated by the digital signal r5 from 0 and the standard value.
To supply. The second sub-Viterbi decoding circuit 86 performs NRZ on the basis of the clock signal u5 with respect to the digital signal s5.
Viterbi decoding of I is performed to obtain a digital signal w5, which is supplied to the multiplexer 87. The multiplexer 87 receives the clock signal g from the input terminal 82.
5, the timing is controlled, the digital signal v5 from the first sub-Viterbi decoding circuit 85 is set to an odd number sequence,
Of the reproduced digital signal i5 by synthesizing the digital signal w5 from the sub-Viterbi decoding circuit 86 of FIG.
Is generated and output from the output terminal 88.

FIG. 8 shows the first sub-Viterbi decoding circuit 8 of FIG.
FIG. 5 is a block diagram showing 5 in more detail.

In FIG. 8, the first sub-Viterbi decoding circuit 85 includes an error calculating circuit 91 and a path metric calculating circuit 9.
2, replacement circuit 93, first and second path memories 94, 9
5, output selection circuit 96, delay flip-flop (D
FF) 97 and adder 98.

Error calculation circuit 91, path metric calculation circuit 92, first and second path memories 94 and 95, DFF
The frequency-divided clock signal t5 from the frequency divider 84 is guided to 97.
It is designed to operate based on.

The demultiplexer 83 is connected to the input terminal 90.
Is derived from the odd-numbered series of digital signals r5.

The error calculation circuit 91 calculates the data value X of the digital signal r5 from the input terminal 90 and the standard value (+ A and −).
Find the difference α and β from A). The formula in this case is shown below.

Α = X + A (1) β = X−A (2) The error calculation circuit 91 outputs the data signal m5 indicating the value of α to S.
The data signal m5 indicating the value of α and the data signal a6 indicating the value of β are supplied to the path metric calculating circuit 92 while being supplied to the / N calculating circuit 72.

The path metric calculation circuit 92 calculates a path metric using α and β indicated by the data signals m5 and a6, supplies the control signal b6 indicating the calculated path metric to the replacement circuit 93, and also calculates the calculated path metric. An output selection control signal c6 is created based on the metric and supplied to the output selection circuit 96.

The first and second path memories 94 and 95 are
It is composed of a 1-bit shift register, and when a new data value X is inputted, data of "0" and "1" are inputted respectively, and accordingly, the oldest bit is the first and second of the output selection circuit 96. The replacement circuit 93, which is ejected to the input terminal, copies the data stored in the first path memory 94 to the second path memory 95, and
When the data stored in the path memory 95 of the first path memory 94 is copied to the first path memory 94 without doing anything.
In the case where the contents of the path memories 94 and 95 are held as they are, three kinds of control are performed according to the path metric calculation result indicated by the control signal b6 from the path metric calculation circuit 92.

The output selection circuit 96 selects one of the bits repelled from the first and second path memories 94 and 95 based on the output selection control signal c6 and outputs the digital signal d.
6 is supplied to one input terminal of the data signal adder 98 and is also supplied to the DFF 97. The DFF 97 delays the digital signal d6 by one cycle of the clock signal t5, that is, the bit cycle of the digital signal d6 and supplies the delayed digital signal e6 to the other input terminal of the adder 98.
The adder 98 outputs the digital signal d6 and the delayed digital signal e.
A digital signal v5 of the Viterbi decoded output is created by adding 6 and is guided to the output terminal 99.

9 and 10 are graphs showing the distribution of the input data values of the digital signal d5 input to the Viterbi decoding circuit 71, and FIG. 9 shows the case where the S / N of the reproduced signal d4 is high. Indicates the case where the reproduction signal d4 has a low S / N.

Here, the data value of the digital signal h5 input to the Viterbi decoding circuit 71 (in this case, the waveform equivalent circuit 1
5 shows the sampling value of the reproduction signal d4 of 5),
Disperses around + 2A, 0, -2A. That is, the data value X of the odd-numbered series digital signal r5 of the digital signal d5
Fluctuates with a leaf around + 2A, 0, -2A. This variation is caused by the reproduction signal d4 as shown in FIG.
When the S / N is high, the range is narrow, and as shown in FIG. 10, when the S / N of the reproduction signal d4 is low, the range is wide.

Here, the calculation result α of the error calculation circuit 91
However, when α <−A, the range in which the data value X exists is the shaded portion in FIGS. 9 and 10. Therefore,
A value proportional to the input signal amplitude is obtained by integrating a predetermined number of data values X existing in this portion, and the calculation result α
The same effect can be obtained by adding up.

The S / N calculation circuit 72 of FIG. 6 is constructed based on such a theory.

FIG. 11 is a block diagram showing in detail the S / N calculation circuit 72 of FIG.

A data signal m5 indicating the calculation result α is led to the input terminal 101 of the S / N calculation circuit 72. α <
The -A condition setting circuit uses the data signal m from the input terminal 101.
It is determined whether α indicated by 5 satisfies the condition of α <−A, only the data value of α that satisfies this condition is supplied to the integrating circuit 103, and the integrating circuit 103 receives the data value of α that satisfies the condition. When the condition is satisfied and α <−A is satisfied,
One pulse is supplied to the counter 104. As a result, the counter 104 grasps the number of times of addition of the integrating circuit 103, and when it reaches a predetermined number of times, resets its own count and causes the integrating circuit 103 to stop the calculation.
The S / N conversion circuit 105 outputs the calculation result to the integration circuit 103.
Then, the integrating circuit 103 is reset.

The S / N conversion circuit 105 is an integration circuit 103.
By multiplying the calculation result from
It is converted into an N value, and the data signal n5 indicating the S / N value is led to the output terminal 108.

The S / N calculation circuit 72 grasps the S / N value by such a configuration.

According to such an S / N calculation circuit 72,
It can be realized by adding some digital circuits to the Viterbi decoding circuit. Therefore, the Viterbi decoding circuit can be easily configured on the same integrated circuit and can be realized at low cost.

FIG. 12 is a block diagram of an S / N calculation circuit showing a sixth embodiment of the digital signal reproducing apparatus according to the present invention, and the other circuit uses the circuit of FIG. .

In FIG. 12, the S / N calculation circuit 172 is shown.
The data signal m5 indicating the calculation result α is input to the input terminal 111 of
Has been led. Input terminal 12 of S / N calculation circuit 172
1 is supplied with the odd-numbered series digital signal r5 (see FIGS. 7 and 8) of the digital signal h5 input to the Viterbi decoding circuit 71. The digital signal r5 from the input terminal 121 is supplied to the integrating circuit 113. The α <-A condition setting circuit 112 determines whether or not α indicated by the data signal m5 from the input terminal 111 satisfies the condition of α <-A, and only when this condition is satisfied, the integration circuit 113 is integrated. A control signal to be performed is supplied to the integration circuit 113 to generate a digital signal r.
In addition to causing the data value X of 5 to be added and satisfying the condition of α <−A, one pulse is supplied to the counter 114. As a result, the counter 114 causes the integration circuit 11 to
The number of additions of 3 is grasped, and when the number of additions reaches a predetermined number, the count of itself is reset and the addition circuit 113
To stop the calculation, and the calculation result is sent to the integrating circuit 113 by S
After being sent to the / N conversion circuit 115, the integration circuit 113 is reset.

The S / N conversion circuit 115 includes an integration circuit 113.
By multiplying the calculation result from
It is converted into an N value, and the data signal n5 indicating the S / N value is led to the output terminal 118.

The S / N calculating circuit 172 grasps the S / N value with such a configuration, and the same data signal n5 as that of the S / N calculating circuit 72 of FIG. 11 is output from the output terminal 118 thereof. To be done. As a result, also in the embodiment of the present invention, the same effect as that of the embodiment of the invention shown in FIGS. 6 to 10 can be obtained, and like the S / N calculation circuit 72 of FIG. It can be easily configured on the same integrated circuit as the above and can be realized at low cost.

FIG. 13 is a graph showing the performance improving effect according to the embodiment of the invention shown in FIGS. 1 to 12 as a form opponent, in which the vertical axis shows the error rate and the horizontal axis shows the S / N of the reproduced signal b1. Is shown.

In FIG. 13, the solid line shows the case of the embodiment of the invention shown in FIGS. 1 to 12, and the broken line shows the first fixed PLL, which has a large DC gain and a large VCO.
The transmission frequency purity Q is set high and fixed. The alternate long and two short dashes line shows the second fixed PLL, which is fixed by setting the DC gain to be small and the purity Q of the oscillation frequency of the VCO to be low. The alternate long and short dash line indicates the third fixed PL
L indicates that the DC gain and the purity Q of the VCO oscillation frequency are set to a medium level and fixed in consideration of the balance between high S / N and low S / N.

As shown in this figure, the error rate in the case of the embodiment of the invention is equal to or higher than that of the first to third fixed PLLs in all regions where the S / N of the reproduction signal b1 is, You can see that the error rate is being improved.

Although the magnetic tape is used as the recording medium in the embodiments of the invention shown in FIGS. 1 to 12, various kinds of applications such as a magnetic disk can be applied. The digital signal reproducing apparatus according to the embodiment of the invention shown in FIGS. 1 to 12 can be applied to various applications such as a digital video tape recorder and a hard disk device of a personal computer. In the embodiment of the invention shown in FIGS. 4 to 12, the magnetic tape 51 is used as the recording medium.
Interleaved NRZ as a digital code to be recorded in
Although I is used, it may be applied to another digital code for performing Viterbi decoding, for example, a normal NRZI. Further, in the embodiment of the invention shown in FIGS. 4 to 12, only the DC gain of the PLL is switched according to the calculation result of the S / N calculation circuit, but it corresponds to the calculation result of the S / N calculation circuit. Then P
It may be configured to switch only the purity of the oscillation frequency of the LL VCO, or to switch both the DC gain and the purity.

[0094]

As described above, according to the present invention, since the deterioration of the error rate caused by the phase locked loop can be reduced, the performance of the apparatus can be improved and the recording density of the recording medium can be increased. .

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a first invention of a digital signal reproducing apparatus according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a second invention of a digital signal reproducing apparatus according to the present invention.

FIG. 3 is a block diagram showing an embodiment of a third invention of a digital signal reproducing apparatus according to the present invention.

FIG. 4 is a block diagram showing an embodiment of a fourth invention of a digital signal reproducing apparatus according to the present invention.

5 is a block diagram showing a configuration example of an S / N calculation circuit of the digital signal reproducing device of FIG.

FIG. 6 is a block diagram showing a fifth embodiment of a digital signal reproducing apparatus according to the present invention.

7 is a block diagram showing the Viterbi decoding circuit of FIG. 6 in more detail.

FIG. 8 is a block diagram showing the first sub-Viterbi decoding circuit in FIG. 7 in more detail.

9 is a graph showing the distribution of input data values when the S / N of the digital signal input to the Viterbi decoding circuit in FIG. 7 is high.

10 is a graph showing the distribution of input data values when the S / N of the digital signal input to the Viterbi decoding circuit in FIG. 7 is low.

FIG. 11 is a block diagram showing the S / N calculation circuit of FIG. 6 in detail.

FIG. 12 is a block diagram of an S / N calculation circuit showing a sixth embodiment of the digital signal reproducing apparatus according to the present invention.

FIG. 13 is a graph stylistically showing the performance improving effect according to the embodiment of the invention shown in FIGS. 1 to 12;

FIG. 14 is a block diagram showing a conventional digital signal reproducing device.

FIG. 15 is a block diagram showing a digital signal reproducing device using conventional Viterbi decoding.

16 is an explanatory diagram showing an eye pattern of a reproduced signal immediately before A / D conversion in the digital signal reproducing device of FIG.

17 is an explanatory diagram showing a variation in data when there is no A / D conversion timing shift in the digital signal reproducing apparatus in FIG.

18 is an explanatory diagram showing a variation in data when there is no A / D conversion timing deviation in the digital signal reproducing apparatus in FIG.

[Explanation of symbols]

 11 magnetic tape 12 head 13 preamplifier 14 AGC 15 waveform equalization circuit 16 identification circuit 17 PLL 21 S / N calculation circuit 22 control circuit 23 DC gain switching circuit

Claims (7)

[Claims] 1. A reproducing means for reproducing a recording medium having a digital code recorded thereon to obtain a reproduced signal, a signal noise ratio calculating means for calculating a signal noise ratio of a reproduced signal from the reproducing means, and a reproducing means for reproducing the signal from the reproducing means. A phase-locked loop that extracts a clock signal that serves as a reference for signal processing from the reproduced signal; and an identification circuit that obtains a reproduced digital signal by identifying the reproduced signal from the reproducing unit using the clock signal from the phase-locked loop. If the signal-noise ratio calculation result of the signal-noise ratio calculation means becomes higher, the DC gain of the phase-locked loop is switched to a higher one accordingly, and if the signal-noise ratio calculation result becomes lower, the phase becomes A digital signal reproducing apparatus comprising: a control circuit for switching a DC gain of a locked loop to a lower one. 2. A reproducing means for reproducing a recording medium on which a digital code is recorded to obtain a reproduced signal, a signal noise ratio calculating means for calculating a signal noise ratio of a reproduced signal from the reproducing means, and a reproducing means from the reproducing means. A phase-locked loop that extracts a clock signal that serves as a reference for signal processing from the reproduced signal; and an identification circuit that obtains a reproduced digital signal by identifying the reproduced signal from the reproducing unit using the clock signal from the phase-locked loop. If the signal noise ratio calculation result of the signal noise ratio calculation means becomes high, the purity of the oscillation frequency of the voltage controlled oscillator of the phase locked loop is switched to a higher one accordingly, and the calculation result of the signal noise ratio becomes low. Then, according to this, a control circuit for switching the purity of the oscillation frequency of the voltage-controlled oscillator of the phase-locked loop to a lower one is provided. Digital signal reproducing apparatus for. 3. A reproducing means for reproducing a recording medium on which a digital code is recorded to obtain a reproduced signal, a signal noise ratio calculating means for calculating a signal noise ratio of the reproduced signal from the reproducing means, and a reproducing means for reproducing the signal from the reproducing means. A phase-locked loop that extracts a clock signal that serves as a reference for signal processing from the reproduced signal; and an identification circuit that obtains a reproduced digital signal by identifying the reproduced signal from the reproducing unit using the clock signal from the phase-locked loop. If the calculation result of the signal noise ratio of the signal noise ratio calculation means becomes high, the DC gain of the phase locked loop and the purity of the oscillation frequency of the voltage controlled oscillator of the phase locked loop are switched to a higher one accordingly. If the calculation result of the signal noise ratio becomes low, the DC gain of the phase locked loop and the voltage control transmission of the phase locked loop are accordingly Digital signal reproducing apparatus characterized by comprising a control circuit for switching the lower the purity of the oscillation frequency. 4. An analog / digital conversion circuit for converting the reproduction signal into analog / digital, the identification circuit comprising:
4. A digital signal reproducing apparatus according to claim 1, wherein the digital signal reproducing apparatus comprises a Viterbi decoding circuit that performs Viterbi decoding using the digital signal from the analog / digital conversion circuit. 5. An envelope detection circuit for outputting amplitude information of a reproduction envelope for performing envelope detection of a reproduction signal reproduced from the recording medium before automatic gain control by the signal noise ratio calculating means, and the envelope detection circuit. 5. The digital signal reproducing apparatus according to claim 1, further comprising a signal / noise ratio conversion circuit for converting the signal / noise ratio by multiplying the amplitude information from the signal by a predetermined constant. 6. A condition judging circuit which is a constituent element of the signal noise ratio calculating means, and which compares an error between a reproduced signal amplitude value and a standard value indicated by a digital signal from the analog / digital converting circuit with a predetermined value. A component of the signal-to-noise ratio calculating means, an integrating circuit that integrates the error only when the comparison result of the condition determining circuit satisfies a predetermined condition, and a component of the signal-to-noise ratio calculating means, The digital signal reproducing apparatus according to claim 4, further comprising: a signal-to-noise ratio conversion circuit that converts a signal-to-noise ratio by multiplying the integration result of the integration circuit by a predetermined constant. 7. A condition judging circuit which is a constituent element of the signal noise ratio calculating means, and which compares an error between a reproduction signal amplitude value and a standard value indicated by a digital signal from the analog / digital converting circuit with a predetermined value. A constituent element of the signal-to-noise ratio calculation means, a summing circuit that sums the reproduction signal amplitude value only when the comparison result of the condition determination circuit satisfies a predetermined condition, and a constituent element of the signal-noise ratio calculation means 5. The digital signal reproducing apparatus according to claim 4, further comprising: a signal-to-noise ratio conversion circuit that converts a signal-to-noise ratio by multiplying the integration result of the integration circuit by a predetermined constant.