JPH09297728A - Dma controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set the exact number of subscanning lines by providing a counter addition value setting means for setting an addition value to a transfer count value and a counter adding/subtracting means. SOLUTION: A subtraction transfer counter holding part 175 holds a counter value selected by a transfer counter selector 174, through a subtraction transfer counter value latch signal. A counter addition value setting part 176 outputs any arbitrary counter addition setting value, through a counter addition value latch signal. Based on an addition/subtraction switch signal and the counter addition value latch signal, a counter addition/subtraction part 117 subtracts a fixed subtraction value '1' from the count value outputted from the subtraction transfer counter holding part 175 or adds the arbitrary addition value set by the counter addition value setting part 176 to that count value, so that the added/subtracted count value are outputted to a count value selector 170.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA for transferring data between a peripheral device and a storage device without going through a central processing unit.
(Direct memory access) DM for controlling transfer
The present invention relates to an A controller, and particularly to a DMA controller suitable for use in a facsimile machine.

[0002]

2. Description of the Related Art DMA transfer is performed by a central processing unit (hereinafter referred to as C
The data transfer of one block is performed at high speed without the intervention of (PU). In the case of a facsimile machine, this one block may be one line of image information in the main scanning direction as disclosed in JP-A-2-270077 or a block of 1 Kbyte or the like. Further, recently, high-speed operation has been required, and it has become necessary to transfer one page in order to reduce the load on the CPU.

That is, since recent facsimile apparatuses require high-speed operations such as high-speed reading and high-speed writing, DMA transfer is generally used for transferring data such as image data without CPU intervention. ing. Also,
Since the process of restarting the DMA transfer puts a load on the CPU, the process has been performed from the line unit to the page unit.

Further, although storage devices such as DRAMs have become low in price, it is necessary to efficiently use the minimum necessary amount, and therefore, it is necessary only to process the maximum fixed size of reading and writing. Often there is only a storage device.

However, there has been a demand for transmitting a long original document which is overwhelmingly longer than the maximum standard size, and for recording the long original by roll paper instead of standard cut paper. For this reason, there are cases where the number of sub-scanning lines is unknown, or where the number is greater than or equal to the maximum count value.

[0006]

That is, since the DMA transfer is to count the number of transfers set by the CPU, and transfer the set number of transfers to finish, the number of main scanning words (bytes) and the sub-scanning are performed. The transfer of one page when the number of lines is also known can be set. However, when reading a long original, long printing on roll paper, etc., there are cases where the number of sub-scanning lines cannot be known, or there is a case where the number of sub-scanning lines is greater than or equal to the maximum count value, due to capacity limitations of the printing device, At the start of the DMA transfer, there is a disadvantage that the transfer number cannot be set accurately.

Therefore, the present invention has been made in order to solve such a problem, and DMA is performed even when the number of sub-scanning lines is unknown or when the number of sub-scanning lines is greater than the maximum count value.
An object of the present invention is to provide a DMA controller capable of starting transfer.

[0008]

In order to achieve the above object, the invention according to claim 1 of the present application controls a DMA transfer for directly performing data transfer between a peripheral device and a storage device without passing through a CPU. , In the DMA controller that subtracts the transfer count value set from the CPU by a predetermined fixed value for each transfer and transfers the set value, an arbitrary addition value to be added to the transfer count value during the DMA transfer is set. And a counter addition / subtraction means for subtracting a predetermined fixed value for each transfer from the transfer count value and for adding the counter addition value set in the counter addition value setting means. is there.

Further, in the invention described in claim 2, in the DMA controller according to claim 1, an arbitrary added value set in the counter added value setting means and a fixed added value fixedly set in advance. It is provided with an addition value switching means for switching to the counter addition value.

According to a third aspect of the present invention, in the DMA controller according to the first aspect, a plurality of the counter addition value setting means are provided and the addition value set in each counter addition value setting means is switched. An addition value switching means for setting the counter addition value is provided.

On the other hand, the invention according to claim 4 is the DMA controller according to claim 2 or 3,
The addition value switching means switches the counter addition value according to the operating DMA channel.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a facsimile apparatus to which a DMA controller according to each invention of the present application is applied.

In the figure, reference numeral 1 is a CPU for performing control processing of each part of the apparatus and processing of a facsimile transmission control procedure, and 2 is a control processing program executed by the CPU 1 and various data necessary for executing the control processing program. A system memory that stores the work area of the CPU 1 and 3 is a parameter memory for storing various kinds of information unique to the G3 facsimile apparatus and the like. 4 is a document scanned at a predetermined resolution to read an image. A scanner 5 as an image reading device for performing various kinds of predetermined image processing on a read image, a plotter 5 as an image recording device for recording the image-processed image data or image data received from another facsimile device at a predetermined resolution, Reference numeral 6 denotes an operation panel for operating this device, which is composed of various operation keys and various display devices.

Reference numeral 7 is an encoding / decoding unit that encodes and compresses the image data to be transmitted, and also decodes the image data that has been encoded and compressed and received to the original image data, and 8 indicates the image read by the scanner 4. An image storage device for storing data, image data in a coded and compressed state and image data to be output to the plotter 5, and 9 is a device for realizing a modem function of the G3 facsimile device, and exchanges transmission procedure signals. Low-speed modem function (V.21
Modem) and a modem equipped with a high-speed modem function (V.29 modem, V.27ter modem) for mainly exchanging image data, 10 is for connecting the facsimile apparatus to a public line, and is automatically generated. A network control unit (NCU) having an incoming call function, 11 is a peripheral device such as the scanner 4 or the plotter 5 and the image storage device 8 without going through the CPU 1.
It is a DMA controller for exchanging data at high speed.

The CPU 1, system memory 2, parameter memory 3, scanner 4, plotter 5, operation panel 6, encoding / decoding unit 7, image storage device 8, modem 9,
The network control device 10 and the DMA controller 11 are connected to the system bus 12, and data exchange between these elements is mainly performed via the system bus 12, but the modem 9 and the network control device 10 are connected. Data is exchanged directly with.

FIG. 2 is a block diagram showing the internal structure of the DMA controller 11. In the figure, 13 is a request sampling unit that receives a request signal of each channel indicating a DMA transfer request from a peripheral device such as a scanner 4 or a plotter 5, and 14 is based on the received request signal and in accordance with a predetermined priority order or the like. DM
The operation channel determining unit determines the operation channel for A transfer, and the address generating unit 15, the control signal generating unit 16, and the transfer counting unit 17 correspond to the DMA channel determined by the operation channel determining unit 14. Is activated.

The address generation unit 15 determines D based on the operation channel information determined by the operation channel determination unit 14.
An address is generated for MA transfer and output to the image storage device 8 or the like. The control signal generator 16 receives the request signal and outputs the DMA transfer permission signal DACK to the peripheral device whose operation channel is determined, the memory read / write (R / W) signal, and the I / O read / write (R / W) signal.
W) A control signal necessary for DMA transfer of a signal or the like is generated. The transfer counting unit 17 counts the number of transfers of the DMA transfer in block units, and outputs a transfer end signal as C.
It is output to PU1 and is a characteristic part of the present invention.
Details will be described below.

FIG. 3 is a block diagram showing an embodiment of the transfer counting section 17. The transfer counting unit 17 according to the present embodiment includes a count value selector 170 and CH1 transfer counter holding units 171 to CHN transfer counter holding unit 17.
3, a transfer counter selector 174, a subtraction transfer counter holding unit 175, a counter addition value setting unit 176, and a counter addition / subtraction unit 177.

The count value selector 170 is a DMA.
Either the transfer count set value set by the CPU 1 at the start of transfer or the count value subtracted by 1 by DMA transfer and output from the counter addition / subtraction unit 177 is selected based on the input count value switching signal. Output. CH1 transfer counter holding units 171 to CHN
The transfer counter holding unit 173 has DMA channels CH1 to CH1.
The count value output from the count value selector 170 for each CHN is held by the corresponding CH1 to CHN transfer count value latch signals. The transfer counter selector 174 selects and outputs the count value of the operating DMA channel from each output of the CH1 to CHN transfer counter holding units 171 to 173 based on the subtraction transfer counter switching signal. The subtraction transfer counter holding unit 175 holds the count value selected and output by the transfer counter selector 174 by a subtraction transfer count value latch signal. The counter addition value setting unit 176 sets and outputs an arbitrary counter addition setting value by a counter addition value latch signal.
The counter addition / subtraction unit 177 subtracts 1 which is a fixed subtraction value or sets the counter addition value from the count value output from the subtraction transfer counter holding unit 18 based on the addition / subtraction value switching signal and the counter addition value latch signal. Part 17
The addition value set to 6 is added, and the count value after addition and subtraction is output to the count value selector 170.

FIG. 4 shows a first embodiment (corresponding to claim 1) of the counter addition / subtraction unit 177. The counter adder / subtractor 177 includes an adder / subtractor 177a and a selector 177b.
The selector 177b selects whether to add the counter addition value setting unit output to the subtraction transfer counter holding unit output or to subtract -1, that is, 1
Addition / subtraction is performed by the adder / subtractor 177a.

Examples of operation timings in the above configuration are shown in FIGS. 5, 6 and 7. FIG. 5 shows the operation timing when the transfer count value is initially set, FIG. 6 shows the timing when the normal DMA operation is performed, and FIG. 7 is the DMA characteristic of the present invention.
The timing at the time of operation is shown.

First, as for the initial setting of the normal transfer count value, as shown in FIG. 5, the CPU 1 gives the transfer count setting value (initial setting value) for each operating DMA channel to the count value selector 170 and inputs it. It is selected by setting the count value switching signal to the “L” level and given to each of the transfer counter holding units 171 to 173. These transfer count set values correspond to the corresponding CH1 to CHN corresponding to the rising edge of the transfer count value latch signal.
1 to CHN transfer counter holding units 171 to 173.

Thereafter, each DMA channel CH1 to CHN
6, the transfer count value of each channel CH1 to CHN is decremented by 1 every time the DMA transfer of each channel CH1 to CHN is performed.
For example, when the DMA transfer of the channel CH1 operates, the output of the CH1 transfer counter holding unit 171 (denoted as A) is selected by the transfer counter selector 174 by the subtraction transfer counter switching signal, and the rising edge of the subtraction transfer count value latch signal is generated. Subtraction transfer counter holding unit 175
Latched on. The output (A) of the subtraction transfer counter holding unit 175 is input to the counter addition / subtraction unit 177, and when the addition / subtraction value switching signal is at the “H” level, the counter addition / subtraction unit 177 selects −1 by the selector 177b to perform subtraction. Subtract 1 from the output (A) of the transfer counter holding unit. The counter addition / subtraction unit output (A-1) obtained by subtracting 1 is input to the count value selector 170, and the count value selector 170 selects the counter addition / subtraction unit output when the input count value switching signal is at the “H” level. The subtracted count value (A-1) is held in the CH1 transfer counter holding unit 171 again at the rising edge of the CH1 transfer count value latch signal. Similarly, in the channel CH2, the count value (B) output from the CH2 transfer counter holding unit 172 is set to 1 by the counter addition / subtraction unit 177 via the transfer counter selector 174 and the subtraction transfer counter 175.
The subtraction is performed (B-1), and the operation is performed such that the value is again held in the CH2 transfer counter holding unit 13 via the count value selector 170.

However, when the transfer count setting value (A) is set to D
When it is found that the transfer of + D must be performed after the MA operation is started and the end of the reception or the detection of the end of the original at the time of reading the original is performed, as shown in FIG.
The CPU is set in the counter addition value setting unit 176 during the transfer A times.
The counter addition setting value (D) is written from 1. This counter addition set value (D) is set in the counter addition value setting unit 176 at the rising edge of the counter addition value latch signal. The counter addition / subtraction unit 177, which has recognized that the counter addition value setting unit 176 has been written by the counter addition value latch signal, adds and subtracts the output (D) of the counter addition value setting unit 176 during the DMA transfer of the next channel CH1. If it is added by 177a, the count value of A + D is set as the total number of transfers, and it is possible to perform the DMA transfer of the number of transfers (A + D) as shown in FIG.

Therefore, according to the present embodiment, the facsimile apparatus can start the DMA transfer even when the number of sub-scanning lines is unknown or when the long original is read or written when the number of sub-scanning lines is greater than the maximum count value. It is possible to set the correct number of sub-scanning lines when the correct number of sub-scanning lines is known by the end of reception or the detection of the document end at the time of reading.

FIG. 9 is a block diagram showing a second embodiment (corresponding to claim 2) of the counter addition / subtraction unit 177.
In the present embodiment, in addition to the above-described embodiment, the selector 17
The fixed addition value is input to 7c. The timing is the same as that shown in the above embodiment. Here, as the fixed addition value, a value such as 1 Kbyte, the number of sub-scanning lines in the horizontal direction of B5 size, or 16 lines if one block is controlled by 16 lines is used for each bit line of a plurality of bits. It can be realized in the form of a fixed value set by grounding or non-grounding.

According to the present embodiment, in addition to the effects of the above-described embodiment, even when the size is set to a multiple of the standard size, for example, B5 size is set horizontally, even if it is twice the B4 size length, it can be easily re-set. Can be set.

FIG. 10 shows a second addition / subtraction unit 177 of the counter addition / subtraction unit 177.
4 is a block diagram showing an embodiment (corresponding to claim 3) of FIG. In the present embodiment, a plurality (here, two) of the counter addition value setting units 176 shown in FIG. 3 are provided, and as shown in FIG. 10, a plurality of counter addition / subtraction units 177d (here, first, The second) counter addition value setting section output is input. Regarding the timing, similar to the above, it is the same as that shown in the first embodiment. As a method of using the plurality of counter addition value setting units 176, A4 width, B4 width, and A3 width are prepared depending on the main scanning width, and a plurality of counter addition value setting sections 176 are used depending on the difference in linear density.

According to this embodiment, in addition to the effects of the first embodiment, a multiple of a plurality of standard sizes, for example, A
Although it was set to 4 size horizontal or B5 size horizontal, it can be easily reset even if it is twice the A3 size vertical or B4 size vertical.

By the way, as a fourth embodiment (corresponding to claim 4), by adding the difference of the DMA transfer operation channel to the selector switching condition of FIG. 9 or 10, it becomes possible to perform channel-specific addition. .

Thus, in addition to the effect of the second or third embodiment, another addition value can be set in the read channel, the write channel, and other channels.

Although the counter addition / subtraction unit 177 is provided in each of the above embodiments, the subtraction unit and the addition unit may be provided separately.

Further, in each of the above embodiments, the case where the DMA controller according to the present invention is applied to the facsimile apparatus has been described, but it is also applicable to an image processing apparatus which handles general image data, a digital copying machine and the like. .

[0035]

As described above, according to the invention of claim 1 of the present application, the data transfer between the peripheral device and the storage device is performed by the CP.
In a DMA controller that controls DMA transfer performed directly without U, subtracts a transfer count value set by the CPU by a predetermined fixed value for each transfer, and transfers the set value during DMA transfer. Counter addition value setting means capable of setting an arbitrary addition value to be added to the transfer count value,
Since a predetermined fixed value is subtracted from the transfer count value for each transfer and a counter addition / subtraction unit for adding the counter addition value set in the counter addition value setting unit is provided, for example, in a facsimile device or the like, sub-scanning is performed. When the number of lines is unknown, or when reading or writing a long original when the count value is greater than or equal to the maximum count value, DMA transfer can be started. There is an effect that it is possible to set the correct number of sub-scanning lines at the time when it is found.

Further, according to the invention of claim 2, in the DMA controller according to claim 1, an arbitrary addition value set in the counter addition value setting means and a fixed addition set in advance in a fixed manner. Since the addition value switching means for switching the value and the counter addition value is provided, the same effect as that of claim 1 can be obtained, and it is set to a multiple of the standard size, for example, B5 size, but twice that. Even in the case of B4 size portrait, there is an effect that it can be easily reset.

According to a third aspect of the invention, in the DMA controller according to the first aspect, a plurality of the counter addition value setting means are provided and the addition values set in the respective counter addition value setting means are provided. Since the addition value switching means for switching to the counter addition value is provided, the same effect as in claim 1 can be obtained, and a plurality of standard sizes, for example, A4 size horizontal and B5 size horizontal are set. Even in the case of a double A3 size portrait or B4 size portrait, there is an effect that it can be easily reset.

On the other hand, according to the invention of claim 4, in the DMA controller of claim 2 or 3, the addition value switching means switches the counter addition value according to the operating DMA channel. Therefore, the same effects as those of claim 2 or claim 3 can be obtained, and another addition value can be set in the read channel, the write channel, and other channels.

[Brief description of drawings]

FIG. 1 is a block diagram of a facsimile apparatus to which a DMA controller according to each embodiment of the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of a DMA controller in the facsimile device.

FIG. 3 is a block diagram showing an embodiment of a transfer counting unit in the DMA controller.

FIG. 4 is a block diagram showing a first embodiment of a counter addition / subtraction unit in the transfer counting unit.

FIG. 5 is a diagram showing an initial setting timing of a transfer count value.

FIG. 6 is a diagram showing the timing of subtracting the transfer count value by one.

FIG. 7 is a diagram showing a timing at which a transfer count value is added.

FIG. 8 is a DM that changes depending on the addition of the transfer count values.
Explanatory drawing of A transfer number.

FIG. 9 is a block diagram showing a second embodiment of a counter addition / subtraction unit in the transfer counting unit.

FIG. 10 is a block diagram showing a third embodiment of a counter addition / subtraction unit in the transfer count unit.

[Explanation of symbols]

 1 CPU 2 system memory 3 parameter memory 4 scanner 5 plotter 6 operation panel 7 encoding / decoding unit 8 image storage device 9 modem 10 network control device 11 DMA controller 12 system bus 13 request sampling unit 14 operation channel determination unit 15 address generation unit 16 Control Signal Generation Unit 17 Transfer Count Unit 170 Count Value Selector 171 to 173 CH1 to CHN Transfer Counter Holding Unit 174 Transfer Counter Selector 175 Subtraction Transfer Counter Holding Unit 176 Counter Addition Value Setting Unit 177 Counter Addition / Subtraction Unit 177a Adder / Subtractor 177b to 177d Selector

Claims (4)

[Claims] 1. A DMA transfer which directly transfers data between a peripheral device and a storage device without passing through a central processing unit is controlled, and a transfer count value set by the central processing unit is subtracted by a predetermined fixed value for each transfer. Then, DMA for transferring the set value
In the controller, counter addition value setting means capable of setting an arbitrary addition value to be added to the transfer count value during the DMA transfer, and subtracting a predetermined fixed value for each transfer from the transfer count value and setting the counter addition value. And a counter addition / subtraction means for adding the counter addition value set in the means. 2. An addition value switching means for switching between an arbitrary addition value set in the counter addition value setting means and a fixed addition value fixedly set in advance to be a counter addition value. The DMA controller according to claim 1, wherein 3. A plurality of counter addition value setting means, and addition value switching means for switching the addition value set in each counter addition value setting means to be a counter addition value. 1. The DMA controller according to 1. 4. The DMA controller according to claim 2, wherein the addition value switching means switches the counter addition value according to the operating DMA channel.