JPH09294216A - Amplifier circuit for deflection circuit - Google Patents

Amplifier circuit for deflection circuit

Info

Publication number
JPH09294216A
JPH09294216A JP10781196A JP10781196A JPH09294216A JP H09294216 A JPH09294216 A JP H09294216A JP 10781196 A JP10781196 A JP 10781196A JP 10781196 A JP10781196 A JP 10781196A JP H09294216 A JPH09294216 A JP H09294216A
Authority
JP
Japan
Prior art keywords
power supply
circuit
resistor
supply voltage
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10781196A
Other languages
Japanese (ja)
Other versions
JP3342290B2 (en
Inventor
Shigeaki Mashita
茂明 真下
Kazumasa Arai
一正 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP10781196A priority Critical patent/JP3342290B2/en
Publication of JPH09294216A publication Critical patent/JPH09294216A/en
Application granted granted Critical
Publication of JP3342290B2 publication Critical patent/JP3342290B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce power consumption more than that of a conventional circuit by providing a transistor(TR), a 2nd diode, and a 2nd resistor whose resistance is higher than that of a 1st resistor, in addition to a pumpup circuit, to the amplifier circuit. SOLUTION: A charge time is determined by the time constant of a pumpup capacitor PC11 and a 1st resistor R11. Since the resistance of the 1st resistor R11 is small, the time constant is not increased, and, hence, it is possible to avoid the situation in which the time required for charge/discharge is extended and the increase/decrease in a power supply voltage cannot follow the increase/ decrease in an output voltage is taking place. Furthermore, discharged through a discharging route during a blanking period, and in this case, a 2nd resistor R12 directly connected to a positive power supply +Vcc has a higher resistance than that of the 1st resistor R11, so that the current flowing therein is small. Moreover, a TR11 is nonconductive and no current flows in the 1st resistor R11, and hence the power consumption due to the current flowing in both resistors 11, 12 can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はCRTディスプレ
イ、プロジェクションテレビなどに用いられるコンバー
ジェンス補正回路などの偏向回路に用いられる増幅回路
の改善に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of an amplifier circuit used in a deflection circuit such as a convergence correction circuit used in a CRT display, a projection television and the like.

【0002】[0002]

【従来の技術】以下で従来例に係る偏向回路用の増幅回
路について説明する。この回路は、CRTディスプレイ
やプロジェクションテレビなどのコンバージェンス補正
回路の出力部に用いられる回路であって図3に示すよう
に、不図示の偏向信号生成回路によって生成された偏向
信号(IS)をアンプ(1)で増幅し、この出力電圧
(Vout)をコンバージェンス補正用の偏向コイル
(L)に出力することで、ブラウン管に照射される電子
を偏向してコンバージェンス補正をする回路である。
2. Description of the Related Art A conventional amplification circuit for a deflection circuit will be described below. This circuit is a circuit used in the output section of a convergence correction circuit such as a CRT display or a projection television, and as shown in FIG. 3, the deflection signal (IS) generated by a deflection signal generation circuit (not shown) is amplified ( This is a circuit for amplifying the output voltage (Vout) in 1) and outputting the output voltage (Vout) to the deflection coil (L) for convergence correction, thereby deflecting the electrons radiated to the cathode ray tube to perform the convergence correction.

【0003】この回路は図3に示すように、アンプ
(1)と、アンプの正側の電源電圧(+Vc)を生成す
る第1の電源回路(2)と、アンプの負側の電源電圧
(−Vc)を生成する第2の電源回路(3)とを有す
る。これら第1,第2の電源回路(2,3)はいずれも
いわゆるポンプアップ回路なる昇圧回路であって、それ
ぞれに備えられた昇圧用のポンプアップコンデンサ(P
C1,PC2)に充放電する事で、走査期間には電源電
圧(±Vcc)を、帰線期間にはこれを昇圧した2倍の
電源電圧(±Vcc×2)をそれぞれ生成して供給する
ことで、消費電力を低減して高効率化を図る回路であ
る。
As shown in FIG. 3, this circuit includes an amplifier (1), a first power supply circuit (2) for generating a positive power supply voltage (+ Vc) of the amplifier, and a negative power supply voltage (+ Vc) of the amplifier. A second power supply circuit (3) for generating -Vc). Each of the first and second power supply circuits (2, 3) is a step-up circuit which is a so-called pump-up circuit, and each has a step-up pump-up capacitor (P
By charging / discharging C1 and PC2), a power supply voltage (± Vcc) is generated during the scanning period, and a doubled power supply voltage (± Vcc × 2) that is boosted during the blanking period is generated and supplied. This is a circuit for reducing power consumption and improving efficiency.

【0004】このアンプの出力電圧(Vout),電源
電圧(±Vc)などの関係を図5に示す。アンプの出力
電圧(Vout)は、図5に示すように帰線期間には高
電圧のフライバックパルスが生じるので、正側ではこれ
よりも高電圧の電源電圧が必要になるが、走査期間では
出力電圧(Vout)はさほど上昇しないので、帰線期
間ほど高電圧の電源電圧は必要ない。
FIG. 5 shows the relationship between the output voltage (Vout) and the power supply voltage (± Vc) of this amplifier. As for the output voltage (Vout) of the amplifier, a flyback pulse having a high voltage is generated in the blanking period as shown in FIG. 5, so a power supply voltage higher than this is required on the positive side, but in the scanning period. Since the output voltage (Vout) does not rise so much, the power supply voltage as high as the blanking period is not required.

【0005】よって、単に高電圧の一定電圧を電源電圧
としたのでは、走査期間における電力のロスが大きく、
その効率が低下するので、図5に示すように、それほど
高電圧が要求されない走査期間では正電源(+Vc
c),負電源(−Vcc)をアンプ(1)に電源電圧
(±Vc)として供給し、高電圧が要求される帰線期間
では、正電源(+Vcc),負電源(−Vcc)を2倍
に昇圧した電圧(+Vcc×2,−Vcc×2)をアン
プ(1)に電源電圧(±Vc)として供給し、電力のロ
スを低減して高効率化を図っている。
Therefore, if a constant high voltage is used as the power supply voltage, the power loss during the scanning period is large,
Since the efficiency is lowered, as shown in FIG. 5, the positive power supply (+ Vc
c), the negative power supply (-Vcc) is supplied to the amplifier (1) as the power supply voltage (± Vc), and the positive power supply (+ Vcc) and the negative power supply (-Vcc) are set to 2 during the blanking period when a high voltage is required. The voltage (+ Vcc × 2, −Vcc × 2) that is doubled is supplied to the amplifier (1) as a power supply voltage (± Vc) to reduce power loss and improve efficiency.

【0006】上記の回路の動作について以下で図4を参
照しながら説明する。第2の電源回路(2)の動作は第
1の電源回路(1)の動作と同様なので説明を省略す
る。走査期間ではスイッチング回路(SW1)がOFF
し、正電源(+Vcc)がダイオード(D1)を介して
アンプの正側に供給される。この間ポンプアップコンデ
ンサ(PC1)は図4に示すようにダイオード(D1)
→ポンプアップコンデンサ(PC1)→抵抗(R1)→
接地電位(GND)なる充電経路で充電されており、こ
の際のポンプアップコンデンサ(PC1)の電極間の電
位差は+Vccとなる。
The operation of the above circuit will be described below with reference to FIG. The operation of the second power supply circuit (2) is the same as the operation of the first power supply circuit (1), and the description thereof will be omitted. The switching circuit (SW1) is OFF during the scanning period.
Then, the positive power supply (+ Vcc) is supplied to the positive side of the amplifier via the diode (D1). During this period, the pump-up capacitor (PC1) is a diode (D1) as shown in FIG.
→ Pump-up capacitor (PC1) → Resistor (R1) →
It is charged through the charging path of the ground potential (GND), and the potential difference between the electrodes of the pump-up capacitor (PC1) at this time is + Vcc.

【0007】その後帰線期間になるとスイッチング回路
(SW1)がONする。するとアンプ(1)の正側の電
源電圧(+Vc)は、ポンプアップコンデンサ(PC
1)に充電されていた電荷が図4に示すような放電経路
で放電されることで、正電源(+Vcc)に加えて、コ
ンデンサの電極間の電位差すなわち+Vccだけ昇圧さ
れるので、+Vcc×2となる。
Then, in the blanking period, the switching circuit (SW1) is turned on. Then, the power supply voltage (+ Vc) on the positive side of the amplifier (1) becomes the pump-up capacitor (PC
Since the electric charge charged in 1) is discharged in the discharge path as shown in FIG. 4, in addition to the positive power supply (+ Vcc), the potential difference between the electrodes of the capacitor, that is, + Vcc is boosted, and therefore + Vcc × 2 Becomes

【0008】このように生成された電源電圧(+Vc,
−Vc)を用いて、アンプ(1)は偏向信号(IS)を
アンプ(1)で増幅し、増幅された結果である出力電圧
(Vout)をコンバージェンス補正用の偏向コイル
(L)に出力することで、ブラウン管に照射される電子
を偏向してコンバージェンス補正をしている。以上のよ
うにして、走査期間では+Vccを、帰線期間では+V
cc×2をというように、期間に応じて電源電圧を切替
えているので、フライバックパルスに対応できる高電圧
の一定電圧を電源電圧とする回路に比して、走査期間で
の消費電力のロスを低減し、効率を向上させている。
The power supply voltage (+ Vc,
-Vc), the amplifier (1) amplifies the deflection signal (IS) by the amplifier (1), and outputs the amplified output voltage (Vout) to the deflection coil (L) for convergence correction. As a result, the electrons radiated to the cathode ray tube are deflected to correct the convergence. As described above, + Vcc is applied during the scanning period and + Vcc is applied during the blanking period.
Since the power supply voltage is switched according to the period, such as cc × 2, the loss of power consumption during the scanning period is higher than that of a circuit that uses a constant high voltage that can handle flyback pulses as the power supply voltage. To improve efficiency.

【0009】[0009]

【発明が解決しようとする課題】上記の図3に示す回路
においては、充電経路に設けられた抵抗(R1)とし
て、抵抗値の小さいものを用いている。これはポンプア
ップコンデンサ(PC1)の充放電の際の時定数を規定
するため、抵抗値が大きいものを用いると、充放電に要
する時間が長くなってしまい、とくに高電圧が要求され
る帰線期間において電源電圧の上昇が出力電圧の上昇に
追従できずに出力が歪んでしまうためである。
In the circuit shown in FIG. 3, the resistor (R1) provided in the charging path has a small resistance value. This defines the time constant for charging / discharging the pump-up capacitor (PC1), so if a capacitor with a large resistance value is used, the time required for charging / discharging will become longer, and a particularly high voltage retrace line is required. This is because the rise of the power supply voltage cannot follow the rise of the output voltage during the period and the output is distorted.

【0010】上記回路では放電時に、比較的高電圧の電
源電圧(+Vcc)が上述のように抵抗値の小さい抵抗
(R1)に直接印加され、この抵抗(R1)に比較的大
きな電流が流れるので、消費電力が大きくなってしまう
という問題が生じる。殊に、帰線期間のデューティ比が
大きくなるような場合には、1周期において抵抗(R
1)に電源電圧(+Vcc)が印加される時間が長くな
るので、この消費電力のロスは一層大きくなってしま
う。
In the above circuit, when discharging, a relatively high power supply voltage (+ Vcc) is directly applied to the resistor (R1) having a small resistance value as described above, and a relatively large current flows through this resistor (R1). However, there arises a problem that power consumption increases. Especially when the duty ratio during the blanking period becomes large, the resistance (R
Since the time period during which the power supply voltage (+ Vcc) is applied to 1) becomes long, this power consumption loss becomes even larger.

【0011】[0011]

【課題を解決するための手段】本発明は上記従来の欠点
に鑑み成されたもので、図1に示すように、前記偏向信
号を増幅して偏向コイルに出力する信号増幅部と、一定
電圧にその一端が接続され、走査期間ではオフして帰線
期間ではオンするスイッチ回路と、前記一定電圧にアノ
ードが接続され、カソードが前記信号増幅部の電源電圧
の出力となる第1のダイオードと、前記第1のダイオー
ドのカソードに一端が接続された充放電用のコンデンサ
と、前記充放電用のコンデンサの他端にエミッタが接続
されたトランジスタと、前記トランジスタのコレクタと
接地電位との間に接続された第1の抵抗と、前記トラン
ジスタのベースと接地電位との間に接続され、前記第1
の抵抗よりも抵抗値が高い第2の抵抗と、前記充放電用
のコンデンサの他端及び前記トランジスタのエミッタに
カソード/アノードが接続され、アノード/カソードが
前記スイッチ回路の他端と前記トランジスタのベースと
の間に接続された第2のダイオードとを具備し、走査期
間では前記充放電用のコンデンサに充電しつつ前記一定
電圧を前記信号増幅部の電源電圧とし、帰線期間で前記
コンデンサから放電させることで前記一定電圧を昇圧さ
せて前記信号増幅部の電源電圧とする電源回路とを備え
たことを特徴とする偏向回路用の増幅回路により、さら
なる電力のロスの低減、効率の向上を目的とする。
The present invention has been made in view of the above-mentioned drawbacks of the prior art. As shown in FIG. 1, a signal amplifier for amplifying the deflection signal and outputting it to a deflection coil, and a constant voltage. A switch circuit that has one end connected to it, is turned off during a scanning period and is turned on during a blanking period, and has a first diode whose anode is connected to the constant voltage and whose cathode serves as an output of the power supply voltage of the signal amplification section. Between a charge / discharge capacitor having one end connected to the cathode of the first diode, a transistor having an emitter connected to the other end of the charge / discharge capacitor, and between the collector of the transistor and the ground potential. A first resistor connected between the first resistor and a base of the transistor and the ground potential;
A second resistor having a resistance value higher than that of the resistor, a cathode / anode is connected to the other end of the charging / discharging capacitor and the emitter of the transistor, and the anode / cathode is connected to the other end of the switch circuit and the transistor. A second diode connected between the base and the base, wherein the constant voltage is used as the power supply voltage of the signal amplifying unit while charging the charging / discharging capacitor during the scanning period, and the capacitor is removed from the capacitor during the blanking period. An amplification circuit for a deflection circuit, further comprising a power supply circuit for boosting the constant voltage by discharging to use as a power supply voltage of the signal amplification section, further reducing power loss and improving efficiency. To aim.

【0012】[0012]

【発明の実施の形態】以下で、本発明の実施形態に係る
偏向回路用の増幅回路について図面を参照しながら説明
する。この回路は、CRTディスプレイやプロジェクシ
ョンテレビなどのコンバージェンス補正回路の出力部に
用いられる回路であって図1に示すように、不図示の偏
向信号生成回路によって生成された偏向信号(IS)を
アンプ(11)で増幅し、この出力電圧(Vout)を
コンバージェンス補正用の偏向コイル(L)に出力する
ことで、ブラウン管に照射される電子を偏向してコンバ
ージェンス補正をする回路である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an amplifier circuit for a deflection circuit according to an embodiment of the present invention will be described with reference to the drawings. This circuit is a circuit used in the output part of a convergence correction circuit such as a CRT display or a projection television, and as shown in FIG. 1, a deflection signal (IS) generated by a deflection signal generation circuit (not shown) is amplified ( 11) Amplification is performed and the output voltage (Vout) is output to the deflection coil (L) for convergence correction, thereby deflecting the electrons radiated to the cathode ray tube to perform the convergence correction.

【0013】この増幅回路は図1に示すように、アンプ
(11),第1の電源回路(12)及び第2の電源回路
(13)を有する。この回路の各部の構成について以下
で説明する。アンプ(11)は信号増幅部の一例であっ
て、後述の電源電圧(+Vc,−Vc)を用いて、偏向
信号(IS)を増幅し、出力電圧(Vout)を偏向コ
イル(L)に出力する回路である。
As shown in FIG. 1, this amplifier circuit has an amplifier (11), a first power supply circuit (12) and a second power supply circuit (13). The configuration of each part of this circuit will be described below. The amplifier (11) is an example of a signal amplifying unit, amplifies the deflection signal (IS) using a power supply voltage (+ Vc, −Vc) described later, and outputs the output voltage (Vout) to the deflection coil (L). It is a circuit to do.

【0014】第1の電源回路(12)は、図1に示すよ
うに走査期間ではポンプアップコンデンサ(PC11)
に充電しつつ正電源(+Vcc)をアンプ(11)の電
源電圧(+Vc)とし、帰線期間でポンプアップコンデ
ンサ(PC11)から放電させることで正電源(+Vc
c)を2倍に昇圧させてアンプ(11)の電源電圧とす
る回路である。
The first power supply circuit (12) has a pump-up capacitor (PC11) in the scanning period as shown in FIG.
The positive power supply (+ Vcc) is set to the power supply voltage (+ Vc) of the amplifier (11) while being charged, and the positive power supply (+ Vc) is discharged by discharging the pump-up capacitor (PC11) during the blanking period.
It is a circuit that doubles c) to be the power supply voltage of the amplifier (11).

【0015】この回路は、一定の正電源(+Vcc)に
その一端が接続され、走査期間ではOFFして帰線期間
ではONするスイッチ回路(SW11)と、正電源(+
Vcc)にアノードが接続され、カソードがアンプ(1
1)の電源電圧(+Vc)の出力となる第1のダイオー
ド(D11)と、第1のダイオード(D11)のカソー
ドに一端が接続されたポンプアップコンデンサ(PC1
1)と、ポンプアップコンデンサ(PC11)の他端に
エミッタが接続されたPNP型のトランジスタ(TR1
1)と、トランジスタ(TR11)のコレクタと接地電
位(GND)との間に接続され、充放電に係る時定数を
ポンプアップコンデンサ(PC11)とともに規定する
第1の抵抗(R11)と、トランジスタ(TR11)の
ベースと接地電位(GND)との間に接続され、第1の
抵抗(R11)よりも抵抗値が高い第2の抵抗(R1
2)と、ポンプアップコンデンサの他端及びトランジス
タ(TR11)のエミッタにカソードが接続され、アノ
ードがスイッチ回路(SW11)の他端とトランジスタ
(TR11)のベースとの間に接続された第2のダイオ
ード(D12)とを有する。
One end of this circuit is connected to a constant positive power source (+ Vcc), which is turned off during the scanning period and turned on during the retrace line period, and a positive power source (+).
The anode is connected to Vcc) and the cathode is connected to the amplifier (1
1) A first diode (D11) that outputs the power supply voltage (+ Vc) and a pump-up capacitor (PC1) having one end connected to the cathode of the first diode (D11).
1) and a PNP transistor (TR1) whose emitter is connected to the other end of the pump-up capacitor (PC11).
1) is connected between the collector of the transistor (TR11) and the ground potential (GND), and defines a time constant for charging / discharging together with the pump-up capacitor (PC11), and a transistor (R11). A second resistor (R1) connected between the base of TR11) and the ground potential (GND) and having a resistance value higher than that of the first resistor (R11).
2), a cathode is connected to the other end of the pump-up capacitor and the emitter of the transistor (TR11), and an anode is connected between the other end of the switch circuit (SW11) and the base of the transistor (TR11). And a diode (D12).

【0016】この回路は図3に示す従来のポンプアップ
回路に、トランジスタ(TR11),第2のダイオード
(D12)及び第2の抵抗(R12)が追加された点が
従来と異なる点である。第2の電源回路(13)は、第
1の電源回路(12)と同様に、走査期間ではポンプア
ップコンデンサ(PC12)に充電しつつ一定の負電源
(−Vcc)をアンプ(11)の電源電圧(−Vc)と
し、帰線期間でポンプアップコンデンサ(PC12)か
ら放電させることで負電源(−Vcc)を2倍に昇圧さ
せてアンプ(11)の電源電圧とする回路である。その
構成は図1に示すように、第1の電源回路(12)と対
称なので説明を省略する。
This circuit is different from the conventional pump-up circuit shown in FIG. 3 in that a transistor (TR11), a second diode (D12) and a second resistor (R12) are added. Similarly to the first power supply circuit (12), the second power supply circuit (13) charges the pump-up capacitor (PC12) during the scanning period and supplies a constant negative power supply (-Vcc) to the power supply of the amplifier (11). It is a circuit that doubles the negative power supply (-Vcc) by using the voltage (-Vc) and discharging the pump-up capacitor (PC12) in the blanking period to use the power supply voltage of the amplifier (11). The configuration thereof is symmetrical to that of the first power supply circuit (12) as shown in FIG.

【0017】引き続いて上記の増幅回路の動作について
以下で説明する。最初に電源が投入されると第1,第2
の電源回路(12,13)にそれぞれ正電源(+Vc
c),負電源(−Vcc)が印加される。次いで偏向信
号(IS)がアンプ(11)によって増幅されて出力電
圧(Vout)が生成され、偏向コイル(L)に出力さ
れ、同時に第1,第2の電源回路(12,13)にも出
力される。
Next, the operation of the above amplifier circuit will be described below. When the power is first turned on, the first and second
Power supply circuit (12, 13) of the positive power supply (+ Vc
c), a negative power supply (-Vcc) is applied. Next, the deflection signal (IS) is amplified by the amplifier (11) to generate an output voltage (Vout), which is output to the deflection coil (L) and simultaneously output to the first and second power supply circuits (12, 13). To be done.

【0018】その後の動作については、(1)走査期
間,(2)帰線期間で動作が異なるので、この2つの場
合について図2を参照しながら説明する。なお、以下で
は第1の電源回路(12)の動作について主に説明し、
第2の電源回路(13)の動作については第1の電源回
路(11)の動作と同様なので、説明を省略する。 (1)走査期間 この期間ではまずスイッチ回路(SW11)がOFFす
る。
Regarding the subsequent operation, the operation is different in (1) scanning period and (2) retrace line period, so these two cases will be described with reference to FIG. In the following, the operation of the first power supply circuit (12) will be mainly described,
The operation of the second power supply circuit (13) is the same as the operation of the first power supply circuit (11), and therefore its description is omitted. (1) Scanning period In this period, the switch circuit (SW11) is turned off first.

【0019】このとき第2のダイオード(D12)によ
る逆バイアスによってトランジスタ(TR11)のベー
ス電位は上昇せず、GND電位であり一方エミッタの電
位が上昇するので、第2の抵抗(R12)にベース電流
が流れてトランジスタ(TR11)がONする。このた
め、図2に示すように正電源(+Vcc)→第1のダイ
オード(D11)→ポンプアップコンデンサ(PC1
1)→トランジスタ(TR11)→第1の抵抗(R1
1)→接地電位(GND)という充電経路でポンプアッ
プコンデンサ(PC11)に充電され、ポンプアップコ
ンデンサ(PC)の電極間の電位差は正電源(+Vc
c)まで上昇する。
At this time, the base potential of the transistor (TR11) does not rise due to the reverse bias of the second diode (D12), but it is the GND potential, while the potential of the emitter rises, so that the base of the second resistor (R12) is increased. A current flows and the transistor (TR11) is turned on. Therefore, as shown in FIG. 2, positive power supply (+ Vcc) → first diode (D11) → pump-up capacitor (PC1)
1) → transistor (TR11) → first resistor (R1)
1) → The pump-up capacitor (PC11) is charged through the charging path of ground potential (GND), and the potential difference between the electrodes of the pump-up capacitor (PC) is the positive power supply (+ Vc).
rise to c).

【0020】この期間中、アンプ(11)の正側では第
1のダイオード(D11)を介して正電源(+Vcc)
がアンプ(11)に印加され、アンプ(11)の電源電
圧(+Vc)となる。アンプ(11)の負側でも同様に
して、負電源(−Vcc)が直接印加され、これがアン
プ(11)の電源電圧(−Vc)として供給されること
になる。
During this period, on the positive side of the amplifier (11), the positive power source (+ Vcc) is supplied via the first diode (D11).
Is applied to the amplifier (11) and becomes the power supply voltage (+ Vc) of the amplifier (11). Similarly, the negative power source (-Vcc) is directly applied to the negative side of the amplifier (11), and this is supplied as the power source voltage (-Vc) of the amplifier (11).

【0021】このように、正/負電源(+Vcc,−V
cc)を第1,第2の電源電圧(+Vc,−Vc)とし
て用いたアンプ(11)によって偏向信号(Vin)が
増幅されて出力電圧(Vout)が偏向コイル(L)に
出力され、ブラウン管に照射される電子が偏向されるこ
とにより、コンバージェンス補正がなされる。 (2)帰線期間 この期間ではスイッチ回路(SW11)がONする。
In this way, the positive / negative power supply (+ Vcc, -V
The deflection signal (Vin) is amplified by the amplifier (11) using cc) as the first and second power supply voltages (+ Vc, -Vc), and the output voltage (Vout) is output to the deflection coil (L). Convergence correction is performed by deflecting the electrons irradiated on the. (2) Return line period During this period, the switch circuit (SW11) is turned on.

【0022】このとき第2の抵抗(R12)に正電源
(+Vcc)が印加されてこれに電流が流れ、トランジ
スタ(TR11)のベース電位が上昇してトランジスタ
(TR11)がOFFする。従来と異なり第2の抵抗
(R12)の抵抗値は従来の図3に示す抵抗(R1)の
抵抗値に比して大きいので、この第2の抵抗(R12)
に正電源(+Vcc)が直接印加されても、このとき流
れる電流は従来に比して小さく、この際の消費電力は従
来に比して小さくて済む。
At this time, a positive power supply (+ Vcc) is applied to the second resistor (R12) and a current flows through it, the base potential of the transistor (TR11) rises and the transistor (TR11) turns off. Unlike the prior art, the resistance value of the second resistor (R12) is larger than the resistance value of the conventional resistor (R1) shown in FIG. 3, so that the second resistance (R12) is
Even if a positive power supply (+ Vcc) is directly applied to the device, the current flowing at this time is smaller than in the conventional case, and the power consumption at this time is smaller than in the conventional case.

【0023】こうしてトランジスタ(TR11)がOF
Fすることにより、図2に示すように正電源(+Vc
c)→スイッチ回路(SW11)→第2のダイオード
(D12)→ポンプアップコンデンサ(PC11)→ア
ンプ(11)という経路でポンプアップコンデンサ(P
C11)から放電される。この期間中、アンプの正側で
は第1のダイオード(D11)から供給される正電源
(+Vcc)に、ポンプアップコンデンサ(PC11)
の電極間の電位差(+Vcc)が上乗される事になるの
で、正電源の2倍の電圧(+Vcc×2)がアンプ(1
1)の電源電圧(+Vc)として供給されることにな
る。アンプの負側でも同様にして、負電源の2倍の電圧
(−Vcc×2)が印加され、これがアンプ(11)の
電源電圧(−Vc)として供給される。
Thus, the transistor (TR11) is OF
As shown in FIG. 2, the positive power supply (+ Vc
c) → switch circuit (SW11) → second diode (D12) → pump up capacitor (PC11) → amplifier (11)
It is discharged from C11). During this period, on the positive side of the amplifier, the pump-up capacitor (PC11) is connected to the positive power supply (+ Vcc) supplied from the first diode (D11).
Since the potential difference (+ Vcc) between the electrodes of the amplifier is added, the voltage (+ Vcc × 2) that is twice the voltage of the positive power source is applied to the amplifier (1
It is supplied as the power supply voltage (+ Vc) of 1). Similarly, on the negative side of the amplifier, a voltage (-Vcc x 2) that is twice the voltage of the negative power source is applied, and this is supplied as the power source voltage (-Vc) of the amplifier (11).

【0024】このように、正/負電源の2倍の電圧(+
Vcc×2,−Vcc×2)である第1,第2の電源電
圧(+Vc,−Vc)を用いて、アンプ(11)によっ
て偏向信号(Vin)が増幅されて出力電圧(Vou
t)が偏向コイル(L)に出力され、ブラウン管に照射
される電子の偏向がなされ、コンバージェンス補正が行
われる。
In this way, the voltage (+
The deflection signal (Vin) is amplified by the amplifier (11) using the first and second power supply voltages (+ Vc, -Vc) which are Vcc * 2, -Vcc * 2) and the output voltage (Vou).
t) is output to the deflection coil (L), the electrons radiated to the cathode ray tube are deflected, and the convergence correction is performed.

【0025】以上説明したように、本実施形態に係る偏
向回路用の増幅回路によれば、効率が高い従来の図3に
示すようなポンプアップ回路に加えて、トランジスタ
(TR11)と第2のダイオード(D12)と、第1の
抵抗(R11)よりも抵抗値が大きい第2の抵抗(R1
2)を設けた回路を第1,第2の電源回路(12,1
3)として用い、走査期間では図2に示すような充電経
路で充電している。
As described above, according to the amplifier circuit for the deflection circuit of this embodiment, in addition to the conventional pump-up circuit as shown in FIG. 3 which has high efficiency, the transistor (TR11) and the second transistor are provided. A diode (D12) and a second resistor (R1) having a resistance value larger than that of the first resistor (R11).
2) is provided to the first and second power supply circuits (12, 1)
3), and is charged through the charging path as shown in FIG. 2 during the scanning period.

【0026】このため、充電時間はポンプアップコンデ
ンサ(PC11)と第1の抵抗(R11)との時定数で
決まるが第1の抵抗(R11)の抵抗値は小さいので上
記の時定数は大きくならず、充放電に要する時間が長く
なってしまい、電源電圧の増減が出力電圧の増減に追従
できなくなるという事態を回避できる。また、帰線期間
では図2に示すような放電経路で放電しており、このと
き、正電源(+Vcc)に直接接続される第2の抵抗
(R12)は第1の抵抗(R11)よりも高抵抗である
のでこれに流れる電流も少なく、また、トランジスタ
(TR11)がOFFしていることで、抵抗値が小さい
第1の抵抗(R11)には高電圧の正電源(+Vcc)
は直接印加されず、第1の抵抗(R11)には電流が流
れないので、抵抗(R11,R12)に電流が流れる事
で生じる消費電力を、従来に比して低減する事が可能に
なる。
Therefore, the charging time is determined by the time constant of the pump-up capacitor (PC11) and the first resistor (R11), but since the resistance value of the first resistor (R11) is small, the above time constant will not be large. Therefore, it is possible to avoid a situation in which the time required for charging / discharging becomes long and the increase / decrease in power supply voltage cannot follow the increase / decrease in output voltage. Further, during the blanking period, discharge is performed through the discharge path as shown in FIG. 2, and at this time, the second resistor (R12) directly connected to the positive power source (+ Vcc) is more than the first resistor (R11). Since it is a high resistance, a current flowing through it is small, and since the transistor (TR11) is off, a high voltage positive power supply (+ Vcc) is applied to the first resistor (R11) having a small resistance value.
Is not directly applied, and no current flows through the first resistor (R11). Therefore, it is possible to reduce the power consumption caused by the current flowing through the resistors (R11, R12) compared to the conventional case. .

【0027】なお、本実施形態では偏向回路用の増幅回
路としてコンバージェンス補正用の増幅回路について説
明しているが、本発明はこれに限らず、例えば垂直偏向
回路などのような他の偏向回路に適用しても、同様の効
果を奏する。
In the present embodiment, the amplification circuit for convergence correction is described as the amplification circuit for the deflection circuit. However, the present invention is not limited to this, and another deflection circuit such as a vertical deflection circuit may be used. Even if it applies, the same effect is produced.

【0028】[0028]

【発明の効果】以上説明したように、本発明に係る偏向
回路用の増幅回路によれば、従来用いていたポンプアッ
プ回路に加えて、トランジスタと第2のダイオードと、
第1の抵抗よりも抵抗値が大きい第2の抵抗を設けてい
る。このため、帰線期間では一定の電源電圧に直接接続
される第2の抵抗は第1の抵抗よりも高抵抗であるので
これに流れる電流も少なく、また、トランジスタがOF
Fしていることにより、比較的高い一定の電源電圧が抵
抗値が小さい第1の抵抗には直接印加されず、第1の抵
抗には電流が流れないので、この抵抗に電流が流れる事
で生じる消費電力を、従来に比して低減する事が可能に
なる。
As described above, according to the amplifier circuit for the deflection circuit of the present invention, in addition to the conventionally used pump-up circuit, the transistor and the second diode are provided.
A second resistor having a larger resistance value than the first resistor is provided. Therefore, during the blanking period, the second resistance directly connected to the constant power supply voltage has a higher resistance than the first resistance, so that a current flowing through the second resistance is small and the transistor is OF
Due to F, a relatively high constant power supply voltage is not directly applied to the first resistor having a small resistance value, and no current flows through the first resistor. Therefore, current flows through this resistor. The generated power consumption can be reduced as compared with the conventional one.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施形態に係る偏向回路用の増幅回路
の回路図である。
FIG. 1 is a circuit diagram of an amplifier circuit for a deflection circuit according to an embodiment of the present invention.

【図2】本発明の実施形態に係る偏向回路用の増幅回路
の動作を説明する図である。
FIG. 2 is a diagram illustrating an operation of the amplifier circuit for the deflection circuit according to the embodiment of the present invention.

【図3】従来例に係る偏向回路用の増幅回路の回路図で
ある。
FIG. 3 is a circuit diagram of an amplifier circuit for a deflection circuit according to a conventional example.

【図4】従来例に係る偏向回路用の増幅回路の動作を説
明する図である。
FIG. 4 is a diagram illustrating an operation of an amplifier circuit for a deflection circuit according to a conventional example.

【図5】ポンプアップ回路を用いたコンバージェンス補
正回路の出力電圧と電源電圧との関係を説明する図であ
る。
FIG. 5 is a diagram illustrating a relationship between an output voltage and a power supply voltage of a convergence correction circuit using a pump-up circuit.

【符号の説明】[Explanation of symbols]

(11) アンプ(信号増幅部) (12) 第1の電源回路 (13) 第2の電源回路 (PC11) ポンプアップコンデンサ(充放
電用のコンデンサ) (SW11,SW12)スイッチ回路 (TR11) トランジスタ (D11) 第1のダイオード (D12) 第2のダイオード (R11) 第1の抵抗 (R12) 第2の抵抗 (IS) 偏向信号 (Vout) 出力電圧 (+Vcc) 正電源 (−Vcc) 負電源 (+Vc) 第1の電源電圧 (+Vc) 第2の電源電圧 (L) 偏向コイル
(11) Amplifier (Signal Amplifying Unit) (12) First Power Supply Circuit (13) Second Power Supply Circuit (PC11) Pump-up Capacitor (Charging / Discharging Capacitor) (SW11, SW12) Switch Circuit (TR11) Transistor ( D11) First diode (D12) Second diode (R11) First resistance (R12) Second resistance (IS) Deflection signal (Vout) Output voltage (+ Vcc) Positive power supply (-Vcc) Negative power supply (+ Vc) ) First power supply voltage (+ Vc) Second power supply voltage (L) Deflection coil

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 偏向信号を増幅して偏向コイルに出力す
る信号増幅部と、 一定の電源電圧にその一端が接続され、走査期間ではオ
フして帰線期間ではオンするスイッチ回路と、 前記一定の電源電圧にアノードが接続され、カソードが
前記信号増幅部の電源電圧の出力となる第1のダイオー
ドと、 前記第1のダイオードのカソードに一端が接続された充
放電用のコンデンサと、 前記充放電用のコンデンサの他端にエミッタが接続され
たトランジスタと、 前記トランジスタのコレクタと接地電位との間に接続さ
れた第1の抵抗と、 前記トランジスタのベースと接地電位との間に接続さ
れ、前記第1の抵抗よりも抵抗値が高い第2の抵抗と、 前記充放電用のコンデンサの他端及び前記トランジスタ
のエミッタにカソード/アノードが接続され、アノード
/カソードが前記スイッチ回路の他端と前記トランジス
タのベースとの間に接続された第2のダイオードとを具
備し、走査期間では前記充放電用のコンデンサに充電し
つつ前記一定の電源電圧を前記信号増幅部の電源電圧と
し、帰線期間で前記コンデンサから放電させることで前
記一定の電源電圧を昇圧させて前記信号増幅部の電源電
圧とする電源回路とを備えた事を特徴とする偏向回路用
の増幅回路。
1. A signal amplification unit for amplifying a deflection signal and outputting it to a deflection coil, a switch circuit having one end connected to a constant power supply voltage, which is turned off during a scanning period and turned on during a retrace line period, A first diode whose anode is connected to the power supply voltage of the first diode and whose cathode is the output of the power supply voltage of the signal amplification section; a charging / discharging capacitor whose one end is connected to the cathode of the first diode; A transistor whose emitter is connected to the other end of the discharging capacitor, a first resistor connected between the collector of the transistor and ground potential, and a transistor connected between the base of the transistor and ground potential, A second resistor having a resistance value higher than that of the first resistor, and a cathode / anode connected to the other end of the charging / discharging capacitor and the emitter of the transistor, A node / cathode is provided with a second diode connected between the other end of the switch circuit and the base of the transistor, and the constant power supply voltage is maintained while charging the charging / discharging capacitor during a scanning period. A deflection circuit, comprising: a power supply voltage of the signal amplification unit; and a power supply circuit that boosts the constant power supply voltage by discharging the capacitor in a blanking period to use as the power supply voltage of the signal amplification unit. Amplification circuit for the circuit.
JP10781196A 1996-04-26 1996-04-26 Amplifier circuit for deflection circuit Expired - Fee Related JP3342290B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10781196A JP3342290B2 (en) 1996-04-26 1996-04-26 Amplifier circuit for deflection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10781196A JP3342290B2 (en) 1996-04-26 1996-04-26 Amplifier circuit for deflection circuit

Publications (2)

Publication Number Publication Date
JPH09294216A true JPH09294216A (en) 1997-11-11
JP3342290B2 JP3342290B2 (en) 2002-11-05

Family

ID=14468643

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10781196A Expired - Fee Related JP3342290B2 (en) 1996-04-26 1996-04-26 Amplifier circuit for deflection circuit

Country Status (1)

Country Link
JP (1) JP3342290B2 (en)

Also Published As

Publication number Publication date
JP3342290B2 (en) 2002-11-05

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