JPH09293841A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve the problem of the coupling noise in a hierarchical bit line configuration, by lessening the influence of an upper interconnection on the chip yield. SOLUTION: Left odd-numbered sense amplifiers S/A0... are connected not only to left bit line pairs BL0, L, BL0, L- ... of corresponding rows through first transfer gate pairs TG0, a, TG0, a- ... but to upper interconnection pairs ML0, ML0- of corresponding rows through second transfer gate pairs TG0, b, TG0, b- ... and these are terminated at mid points of an array SM1 and connected to right bit line pairs BL0, R, BL0, R- ... of corresponding rows through through-hole pairs HU0, HU0- . Similarly right odd-numbered sense amplifiers S/Al... are also connected to right bit line pairs BL1, R, BL1, R- ... and left bit line pairs BL1, L, BL1, L- ... of corresponding rows with the reversed traverse relation.

Description

Detailed Description of the Invention

[0010]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a layout structure of sense amplifiers and bit lines in the memory device.

[0020]

2. Description of the Related Art Generally, a dynamic RAM (DRA)
In the memory array M), as shown in FIG. 9, a differential type sense amplifier S / A provided for each row or each column.
A pair of bit line pairs (bit line / complementary line) BLi, BLi _- is connected to i (i = 0,1,2 ...). Then, for example, the bit line BLi and the odd-numbered word lines WL1 and WL3
, WL5 ... At the intersections with memory cells MCi, 1, MC
i, 3, MCi, 5 ... Are arranged (connected), and the bit complementary line BL is
i _- and the even-numbered word lines WL0, WL2, the memory cell MCi at intersections WL4 ... and _{-, 0, MCi -, 2} , MCi -, 4,
... are arranged (connected).

Each memory cell MCi, j (j = 0,1,2...) Is 1
Transistors Qi, j and one capacitor Ci, j. For example, when writing data to memory cell MC1,1, a word line driving circuit (not shown) is connected to word line WL.
1 is driven or activated to an H level potential to turn on transistor Q1,1 and at the same time sense amplifier S /
A1 changes the potential of the bit line BL1 to H level (VDD) or L level (Vss) according to the write information ("1" or "0"). As a result, VDD is applied to the capacitor C1,1.
Alternatively, a charging voltage of Vss is obtained. Thereafter, the word line driving circuit lowers the word line WL1 to L level (Vss) to turn off the transistor Q1,1. As a result, the charge voltage or charge of "1" (VDD) or "0" (Vss) is held in the capacitor C1,1 as stored information.

When reading the stored information from the memory cell MC1,1, the sense amplifier S / A1 sets the bit line B in advance.
L1 and auxiliary bit line BL1 _- and a constant potential (generally VDD
/ 2), the word line drive circuit drives or activates the word line WL1 to H level to turn on the transistor Q1,1. Then, the bit line BL1 and the capacitor C1,1 are short-circuited and the bit line BL1 is shorted.
The potential on 1 slightly changes from the precharge level according to the charge stored in the capacitor C1,1. This bit line B
By detecting and amplifying a slight potential change on L1 by the sense amplifier S / A1, information stored in the memory cell MC1,1 is determined.

By the way, in a large-scale DRAM, as shown in FIG.
As shown in FIG. 11 and FIG. 11, the memory array is composed of a plurality of sub memory arrays ... MAK-1, MAK, MAK + 1 ... And a considerable number of sense amplifiers S / A are arranged beside each sub memory array MA. It adopts the layout of the shape.

In the structure shown in FIG. 10, the same number of sense amplifiers S / A0, S / A1, ... S as the bit line pairs in the array MA are provided on one side (left side or right side) of each sub memory array MA.
In this method, / An is concentrated. As shown in FIG. 11, the array MA is provided outside the left and right sides of each sub memory array MA
Number of sense amplifiers S / A0, S / A as many as the number of bit line pairs in
1, ... S / An is a staggered arrangement. In addition,
Each sense amplifier S / A is commonly used by sub memory arrays (eg, MAK-1, MAK) on the left and right sides.

In any of the sense amplifier arrangement methods shown in FIGS. 10 and 11, in order to reduce the chip size of the memory device, the bit line BL is extended and the sub memory array M is used.
It is effective to increase A, reduce the number of sense amplifiers S / A, and reduce the ratio of the sense amplifier bank area to the entire chip. However, in order to extend the bit line, the deterioration of the characteristics due to the increase of the resistance and the capacitance becomes a problem. Therefore, a hierarchical bit line configuration as shown in FIG. 12 has been proposed.

In FIG. 12, each sense amplifier S /
Ai is a pair of main bit line pairs (MBi, MBi _-) is connected to each main bit line pair (MBi, MBi _-) to the transfer gate pairs _{(TRi, 0, TRi, 0} -), (TRi, 1
, TRi, 1 _-) ... a plurality of sets of sub-bit line pair via the (S
_{Bi, 0, SBi, 0 -} ), (SBi, 1, SBi, 1 -) ... are connected in parallel. Each sub bit line SB corresponds to a normal bit line BL, and is directly connected to a memory cell (not shown) for one row or one column in a normal sub memory array MA. The main bit line MB is composed of a wiring (usually a metal wiring) in a layer above the sub bit line SB, has a lower resistance and a smaller load capacitance than the sub bit line SB.

Transfer gate pair (TRi, 0, TRi,
_{0 -), (TRi, 1} , TRi, 1 -) ... sub-bit line selection signal SS0, SS1 ... is given to the. For example, when a certain memory cell connected to the sub bit line SBi, 0 is read, the sub bit line selection signal SS
Only 0 is at "H" level, and all other sub-bit line selection signals SS1, SS2 ... Are at "L" level. Thus, the sub-bit line pair (SBi, 0, SBi, 0 _-) read data (potential change) on the transfer gate pairs (TR1,0, TR1,0 _-) main bit line pair through the ( M
Bi, MBi _-) to be transmitted and amplified by the sense amplifier S / Ai.

As described above, according to the hierarchical bit line structure, the number of sense amplifiers or the number of sense amplifiers is increased by expanding the sub memory array by a multiple corresponding to the number of sub bit lines SB connected in parallel to each main bit line MB. The area occupied by the sense amplifier bank can be reduced, and the size of the memory chip can be reduced.

[0110]

However, in the conventional hierarchical bit line structure as described above, the main bit line MB which is the upper layer wiring is required to have a minimum wiring pitch equivalent to that of the sub bit line SB which is the lower layer wiring. It In a semiconductor device, the upper layer wiring has a larger step than the lower layer wiring, and the processing accuracy is usually severe. By applying the rule of the minimum wiring pitch there, there is a problem that the processing condition of the upper layer wiring (main bit line) regulates the chip yield. Most of the recent DRAMs have a stack type memory cell structure, and the level difference in the upper layer wiring is quite large, so it is difficult to adopt the conventional hierarchical bit line configuration as described above.

Further, in the conventional hierarchical bit line structure, there is also a problem that coupling noise from the upper layer wiring (main bit line) in the vicinity of the selected sub bit line SB enters and the sensing margin is reduced.

The present invention has been made in view of the problems of the prior art, and provides a semiconductor memory device having a novel hierarchical bit line structure which reduces the possibility that the upper layer wiring will regulate the yield of chips. The purpose is to do.

A further object of the present invention is to provide a semiconductor memory device having a novel hierarchical bit line structure in which there is no need to worry about coupling noise between upper layer wirings and lower layer wirings (bit lines).

[0150]

To achieve the above object, the first semiconductor memory device of the present invention has sense amplifiers arranged in a zigzag pattern on the outside of each unit memory array in a zigzag pattern. , The left bit line and the right bit line, which are separated from each other, are respectively connected to the left side memory cells and the left side memory cells of each row or each column, and each of the left side sense amplifiers corresponds thereto. Each of the right side is connected to the left side bit line of the row or column and connected to the right side bit line of the corresponding row or column through the upper left side wiring provided in a layer above the bit line. Of the sense amplifier are connected to the right bit line of the corresponding row or column, and via the right upper layer wiring provided in a layer above the right bit line. It characterized it that it is connected to the left bit line of the corresponding row or column configuration Te.

The second semiconductor memory device of the present invention is the same as the first semiconductor memory device, wherein the left sense amplifier is connected to the left bit line of the corresponding row or column via the first transfer gate. And a right-side bit line of the corresponding row or column connected through a third transfer gate to the left upper wiring of the corresponding row or column via a second transfer gate. And a connection to the right upper layer wiring of the corresponding row or column through a fourth transfer gate.

In the third semiconductor memory device of the present invention, the sense amplifiers are arranged in a zigzag pattern on the left and right outside of each unit memory array, and a plurality of memory cells on the left side and right side of each row or each column in the memory array are arranged. The left bit line and the right bit line, which are separated from each other, are respectively connected to the plurality of memory cells, and each of the left sense amplifiers is connected to the left upper line via a left upper layer wiring provided in a layer higher than the bit line. A row or column connected to the left-side bit line and the right-side bit line of the corresponding row or column, and each of the right-side sense amplifiers through the right-side upper layer wiring provided in a layer higher than the bit line. Of the left side bit line and the right side bit line.

The fourth semiconductor memory device of the present invention is the same as the third semiconductor memory device, wherein each of the upper layer wirings is on the left side of the corresponding row or column via the first and second transfer gates. It is characterized in that it is connected to the bit line and the right bit line.

[0190]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a DRAM according to an embodiment of the present invention.
The structure of the main part of is shown. FIG. 2 shows an enlarged part of this DRAM.

This DRAM has, for example, four 256K.
Bit capacity sub-memory array (unit memory array) S
Built-in M0 to SM3, 1M for the entire memory array
Has a bit storage capacity.

Each sub memory array SMK (K = 0, 1, 2,
3) Inside, 512 bit line pairs (BL0, BL0 _-)
~ (BL511, BL511 _-) and 512 word lines WL0
One memory cell (only MC0, j, MC2, j, MC4, j are shown in FIG. 1 as an example) is connected to each intersection with WL511. Each line of the bit line BLi (or _{BLi -) (i = 0,1,2 ...} 255) is the left bit line BLi in the midpoint in the array SM, L (or BLi, L _-) and right bit lines BLi, R (or BLi, R _-) is divided into a.

In each row, each left bit line BLi, L
(Or BLi, L _-) memory cell of the left half MCi, 0 (M
_{Ci -, 0) ~MCi, 255} (MCi -, connected to 255), each of right bit lines BLi, R (or BLi, R _-) is the right half memory cell _{MCi, 256 (MCi -, 256} ) ~MCi , 511 (MC
i _-, it is connected to the 511).

[0240] In relation to the word line WL and bit line BL, the word line WL0 ～WL255 the left half left bit line pair _{(BL0, L, BL0, L} -) ~ (BL511, L, BL511,
L _-) and intersecting, the right half the word lines WL256 ～WL511
There right bit line pair _{(BL0, R, BL0, R} -) ~ (BL511,
R, B511, R _-) and intersect.

Sense amplifier banks SBKL, SBKR are provided on the left and right outer sides of each sub memory array SMK, and these banks SBKL, SBKR have the same number of bit line pairs (512).
Individual) sense amplifiers S / A0, S / A1, S / A2, ...
S / A511 are arranged in a staggered pattern. 1 and 2, only the uppermost three sense amplifiers S / A0, S / A1 and S / A2 are shown for convenience of illustration.

As shown in FIG. 2, for example, regarding the sub memory array SM1, in the left sense amplifier bank SBKL, even-numbered sense amplifiers S / A0 and S / A are provided.
2, ... S / A510 are arranged in every other row in one column, and in the right sense amplifier bank SBKR, odd-numbered sense amplifiers S / A1, S / A3, ... S / A511 are offset by one row from the left side. They are arranged every other row and in one column.

In FIG. 2, the head (hereinafter referred to as the 0th for convenience) belonging to the left sense amplifier bank SBKL.
Sense amplifiers S / A0, the first transfer gate pairs (TG0, a, TG0, a -) left bit line pair of row 0 through (BL0, L, BL0, L -) is connected to the , the second transfer gate pairs (TG0, b, TG0, b -) - it is connected to the upper wiring pair of row 0 through (ML0, ML0). These upper layer wiring pair of 0th row (ML0, ML0 _-)
The left side pair of bit lines (BL0, L, BL0, L -) than extend parallel with the upper layer also terminates at the midpoint of the sub memory array SM1, where a pair of through holes (HU0, HU
0 _-) 0th row right bit line pair via a (BL0, R, BL
0, R _-) to which it is connected.

Next, the right side sense amplifier bank SBKR
The first sense amplifier S / A1 belonging to the third transfer gate pairs (TG1, c, TG1, c -) first through the
Right bit line pairs of lines (BL1, R, BL1, R -) is connected to the fourth transfer gate pairs (TG1, d,
TG1, d _-) first row of the upper wire pair through (ML1, ML
1 _-) to which is connected. The upper layer wiring pair (M
L1, ML1 _-) is right bit line pair (BL1, R, BL1,
R _-) the sub-memory arrays S extend in parallel in an upper layer than
M1 terminates at an intermediate point, where a pair of through holes are connected to the (HU1, HU1 _{- -)} first row left bit line pair via a (BL1, L, BL1, L ).

Next, the left sense amplifier bank SBKL
The second sense amplifier S / A2 belonging to the first transfer gate pairs (TG2, a, TG2, a -) through a second
Left bit line pair lines (, BL2 L, BL2, L -) is connected to the second transfer gate pairs (TG2, b,
TG2, b _-) the second row of the upper wire pair through (ML2, ML
2 _-) to which is connected. The upper layer wiring pair (M
L2, ML2 _-) is the left bit line pair (BL2, L, BL2,
L _-) the sub-memory arrays S extend in parallel in an upper layer than
M1 terminates at an intermediate point, where a pair of through holes are connected to the (HU2, HU2 _{- -)} right bit line pair of the second row through the (BL2, R, BL2, R ).

Subsequent sense amplifiers S / A3, S / A4 ...
Also, the same wiring structure as described above, each left bit line pair of the corresponding row (BL3, L, BL3, L -), (BL4, L
, BL4, L _-) ... and right bit line pair (BL3, R, B
_L3, R - are connected) ... to _{-), (BL4, R,} BL4, R.

[0310] The first to fourth each transfer gate pair for sub memory array _{SM1 (TGa, TGa -),} (T
_{Gb, TGb -), (TGc} , TGc -), (TGd, TG
d _- The), X address decoder 10 (FIG. 1) from the first
~ Fourth gate control signal or bit line selection signal T5,
T4, T6 and T7 are given respectively.

In FIG. 1, the X address decoder 10
Inputs the upper 3 bits (A8, A9, A10) of the 11-bit X address signal A0-A10, and outputs the bit line selection signals (T0-T3) to the sub-memory arrays SM0, SM1, SM2, SM3. ), (T4 to T7),
(T8 to T11) and (T12 to T15) are given respectively, and sub memory arrays SM0, SM1, SM2 and SM are provided.
The word line drive circuits WD0, which are respectively assigned to 3,
Driver selection signal ES for WD1, WD2, and WD3
0, ES1, ES2, ES3 are given respectively.

Each word line drive circuit WDK inputs the lower 9 bits A0 to A8 of the X address signals A0 to A10, and when selected by the corresponding driver selection signal ESK, the lower 9 bits A0 to A8 are internally supplied. 5 in the sub memory array SMK
Any one of the 12 word lines WL0 to WL511 is selected and activated. In this case, address bit A8
Is a logical value "0", the left half word lines WL0 to WL
Any one of 255 is selected and address bit A
When 8 is a logical value "1", the right half word line WL256 ~
Any one of WL511 is selected.

Only one of the driver selection signals ES0 to ES3 becomes active (logical value "1") in accordance with the logical value of the upper 2 bits (A9, A10).
All others are inactive (logical value "0").

For example, (A9, A10) is ("1",
When it is "0", only ES1 is in the active state (logical value "1"), and the other ES0, ES2, ES3 are all inactive state (logical value "0"). In this case, only the word line drive circuit WD1 is activated, and the other word line drive circuits WD0, WD2, WD3 do not operate. As a result, in the sub memory array SM1, X
The word line WLj in the column designated by the lower 9 bits A0 to A8 of the address signal is driven.

Each sub memory array SM0, SM1, SM
2, 1 to 4 bit line selection signals (T
0 to T3), (T4 to T7), (T8 to T11), (T12
To T15) are the corresponding driver selection signals ES0, ES.
1, ES2, ES3 are active (“H” level)
, That is, each corresponding sub memory array S
It is valid when M0, SM1, SM2, SM3 is selected.

For example, in the above example, the driver selection signal E
When S1 becomes active (logical value "1"),
At the input side of the inverting circuit 12, a signal ES1 ₋ having a logic value (“0”) opposite to ES1 is obtained. This allows
NOR circuits 14a, 14b on both sides of the inverting circuit 12
14c and 14d are enabled. Further, since the driver selection signals ES0 and ES2 on both sides are inactive (logical value "0"), the NOR circuit 16 in the subsequent stage is
a, 16b, 16c and 16d are also enabled.
Thereby, the NOR circuits 16a, 16b, 16c, 16
Bit line selection signals T5, T4, T6, T7 on the output side of d
Becomes an active state (logical value "1") or an inactive state (logical value "0") depending on the logical value of the address bit A8.

For example, address bit A8 is "1".
When the, NOR circuit 20 (8) of the input stage, 20 (8 _-) of the output signal (BX8, BX8 _-) is ( "1", "0") in which from NOR circuit 16a, 16b, 16c, 16d The second and third bit line selection signals T4 and T6 are active (logical value "1") and the first and fourth bit line selection signals T5 and T7 are inactive (logical value " 0 "). At this time, the bit line selection signals T2, T3, T8 and T9 are inactive.

When the address bit A8 is "0", the first and fourth bit line selection signals T5 and T7 are in the active state (logical value "1"), and the second and third bit lines are in the active state. The selection signals T4 and T6 are in an inactive state (logical value "0"). At this time, the bit line selection signals T2, T3, T8 and T9 are inactive.

In the above example, the X address decoder 10 selects the sub memory array SM1. However, the mechanism for selecting the other sub memory arrays SM0, SM2, SM3 is the same as above.

As described above, in this embodiment, the four sub memory arrays SM0 to SM0 are arranged according to the logical values of the upper 2 bits (A9, A10) of the X address signals A0 to A10.
Any one of 3 is selected. Then, according to the logical value of the X address signal A8, the left half area or the right half area is selected in the selected sub memory array SMK.

FIG. 3 shows a wiring layout in the vicinity of an intermediate point in each sub memory array SMK in the hierarchical bit line structure of this embodiment.

In FIG. 3, the left upper layer wiring and the right upper layer wiring of two adjacent rows (for example, ML2 and ML).
1 _-) are formed on the same line so that the butt each other at the midpoint, each slightly offset at right angles in opposite directions to each other at an intermediate point corresponding opposite bit line of lines (BL2, R, BL1, L _-) is in the connection.

In this way, the left upper layer wiring and the right upper layer wiring of two adjacent rows are formed on the same line,
Left upper wiring _{ML0, ML0 -, ML2, ML2} - ... left bit lines BL0, L, BL0, L _- is arranged in a ... 2 times the wiring pitch of the right upper wiring ML1, ML1 _-, ML3, M
L3 _- ... right bit lines BL0, R, BL0, R _- are arranged at ... 2 times the wiring pitch of the.

As described above, since the upper layer wirings ML in the hierarchical bit line structure of the present embodiment are arranged at a wiring pitch twice that of the bit lines BL of the lower layer wiring, the line width is large and the step is large. However, there is a sufficient margin in the layout rule. Therefore, the upper layer wiring ML is unlikely to regulate the yield of chips.

Insulating films of one layer or two layers or more are provided between the bit line BL and the upper layer wiring ML, and each through hole HU vertically penetrates these insulating films. Bit line BL is made of, for example, polysilicon or tungsten, and upper layer interconnection ML is made of, for example, aluminum or tungsten.

FIG. 4 shows a transfer gate (eg, TG0, b in FIG. 2) in the hierarchical bit line structure of this embodiment.
_{TG0, b -, TG0, a} , TG0, a - ...) showing a wiring layout in the vicinity.

In FIG. 4, the transfer gate TG is composed of an N-type MOS transistor formed in the main surface region of the semiconductor substrate. One terminal (drain terminal) of each of the first and second transfer gates (TG0, a and TG0, b) corresponding to the bit line and the upper layer wiring (for example, BL0, L and ML0) in the same row is shared. Has been done.

For example, one terminal of the sense amplifier S / A0 is connected to the first and second transfer gates (TG0, a, TG) via the upper layer wiring ML'0 and the contact hole D.
0, b) connected to the common drain terminal (N type diffusion layer). The source terminal (N type diffusion layer) of the first transfer gate TG0, a is connected to the bit line B through the contact hole SB.
It is connected to L0, L. Second transfer gate T
The source terminal (N type diffusion layer) of G0, b is a contact hole SM.
Is connected to the upper layer wiring ML0 via.

First transfer gates TG0, a, TG
_{0, a -, TG2, a} , TG2, a - ... common gate line FG gate terminal, which is provided in a lower layer than the bit line BL of
It consists of a. The second transfer gates _{TG0, b, TG0, b -} , TG2, b, TG2, b - also ... gate terminal, and it is configured with a common gate line FGb provided in a lower layer than the bit lines BL .

Next, referring to the timing chart of FIG. 5, the operation when the sub memory array SM1 is accessed for data reading in the DRAM of this embodiment will be described.

Before the read operation is performed, all bit lines BL in the memory array are precharged,
The enable signal ENB applied to the input stage of the X address decoder 10 (FIG. 1) is in the inactive state (logical value "1"), and the first to fourth bit line selection signals T5, T4
, T6, T7 are all in the active state (logical value "1"), and all transfer gates TG
_{0, a, TG0, a -} , TG0, b, TG0, b - ... are in the ON state.

In the precharge state, the left side (even number)
Each sense amplifier S / A0, S / A2 ... is, first each transfer gate pair of _{(TG0, a, TG0, a} -), (TG2,
a, TG2, a _-) ... each corresponding even left bit line pair line through the _{(BL0, L, BL0, L} -), (BL2, L, T
G2, L _-) ... feeds power to the precharge level (VDD / 2) a, second each transfer gate pair (TG0,
_{b, TG0, b -),} (TG2, b, TG2, b -) ... and the left upper wiring pair _{(ML0, ML0 -), (} ML2, ML2 -)
... each corresponding even right bit line pair line through the (BL0, R, BL0, R -), (BL2, R, TG2, R -) power supply ... to pre-charge level (VDD / 2) are doing.

[0540] Also, the right side (odd) the sense amplifiers S / A1, S / A3 ... of a third each transfer gate pair _{(TG1, c, TG1ca -)} , (TG3, c, TG3, c -) …
Via the right bit line pair (B
_{L1, R, BL1, R -} ), (BL3, R, TG3, R -) ... feeds power to the precharge level (VDD / 2) a, fourth each transfer gate pair (TG1, d, TG1, d _-),
(TG3, d, TG3, d -) ... and the right upper metal wire pair _{(ML1, ML1 -), (} ML3, ML3 -) ... each corresponding odd numbered left bit line pair line through the (BL1, L, B
_{L1, L -), (BL3} , L, TG3, L -) ... pre-charge the
Power is supplied to the level (VDD / 2).

[0550] row address strobe signal for data reading (RAS _-) When the active state ( "L" level), X address signal is latched, as described above upper 3 bits of the X address signal ( A8, A9
, A10) is decoded by the X address decoder 10 (FIG. 1).

It is now assumed that any one (WLj) of the right half word lines WL256 to WL511 is selected in sub memory array SM1. In this case, of the first to fourth bit line selection signals T5, T4, T6 and T7 for the sub memory array SM1, the second and third bit line selection signals T4 and T6 are in the active state ("H").
(Level), the first and fourth bit line selection signals T5 and T7 transit to the inactive state ("L" level). As a result, each second transfer gate pair (T
_{G0, b, TG0, b -} ), (TG2, b, TG2, b -) ... and third each transfer gate pair (TG1, c, TG1c
_{a -), (TG3, c} , TG3, c -) ... will remain in the ON state,
Each first transfer gate pair (TG0, a, TG0,
a ₋ ), (TG2, a, TG2, a ₋ ), and the fourth transfer gate pairs (TG1, d, TG1, d ₋ ), (TG3, d,
TG3, d _-) ... is in the OFF state.

In this case, the sub memory array SM1
When the driver selection signal ES1 for the sub-memory array S on the left side becomes active (logical value "1").
Third and fourth bit line selection signals T2 for M0,
First for T3 and sub memory array SM2 on the right
Also, the second bit line selection signals T9 and T8 are both forced into the inactive state (logical value "0"). As a result, the left side sense amplifier of the sub memory array SM1
Each sense amplifier S / A0 in the bank SB1L (SB0R),
S / A2 ... Is cut off from the sub memory array SM0 on the left side, and each sense amplifier S / A1, S / A3 ... In the right sense amplifier bank SB1R (SB2L) is cut off from the sub memory array SM2 on the right side. .

Therefore, in the sub memory array SM1, the left (even number) sense amplifiers S / A0, S
/ A2 ... are second each transfer gate pair in the ON state _{(TG0, b, TG0, b} -), (TG2, b, TG2, b -) ... and the left upper wire pair (ML0, ML0 _-), (ML2, ML
2 _-) ... and right bit line pairs each corresponding row through (BL
_{0, R, BL0, R -} ), (BL2, R, BL2, R -) ... are short-circuited coupled to. However, each sense amplifier S / A0, S / A
2 ... is the left bit line pair (BL0, L, B
_{L0, L -), (BL2} , L, BL2, L -) ... and the first respective transfer gate pair in the OFF state (TG0, a, TG0,
_{a -), (TG2, a} , TG2, a -) ... is blocked by.

Right (odd number) sense amplifier S / A
1, S / A3 ... is a third each transfer gate pair in the ON state _{(TG1, c, TG1, c} -), (TG3, c, TG3,
c _-) ... right bit line pairs each corresponding row through (BL1,
_{R, BL1, R -),} (BL3, R, BL3, R -) ... are short-circuited coupled to. However, each sense amplifier S / A1, S / A
3 ... is the right upper layer wiring pair (ML1, ML) of each corresponding row.
_{1 -), (ML3, ML3} -) ... to the left side pair of bit lines (B
_{L1, L, BL1, L -} ), (BL3, L, BL3, L -) ... and is,
Each of the fourth transfer gate pairs (TG1, d,
_{TG1, d -), (TG3} , d, TG3, d -) ... is blocked by.

When the selected word line WLj in the sub memory array SM1 is activated to the "H" level, each memory cell MC0, j on the word line WLj,
MC1, j ... Each bit line BL0 on the right side in accordance with the stored information
The potentials on R, BL1, R ... Change slightly. At the same time, the sense amplifiers S / A0, S / A1, S / A2 ...
Is activated and each bit line pair on the right side (BL0, R, BL0,
_{R -), (BL1, R} , BL1, R -), (BL2, R, BL2,
R _-) ... sense amplifier potential change of the above S / A0, S / A1
, S / A2 ... Is detected and amplified.

On the other hand, the Y address signal latched subsequent to the X address signal is the Y address decoder (not shown).
, And one of the sense amplifiers S / Ai is selected by the Y select signal YS. As a result, only the output signal of the selected sense amplifier S / Ai is transmitted to the main amplifier (not shown) through the data input / output line I / O (not shown). DQ is output on the data bus.

In the DRAM of this embodiment, any upper layer wiring (for example, ML) is provided during the data read operation as described above.
Even if the potential of 0) changes, bit lines (BL0,
Since L) is cut off from the corresponding sense amplifier (S / A0) by the transfer gate (TG0, a) in the off state, the problem of coupling noise does not occur. When a signal is transmitted on an arbitrary bit line (BL0, R), the upper layer wiring (ML1) in the vicinity of the bit line is transferred from the corresponding sense amplifier (S / A0) to the transfer gate (TG1, d) in the off state. ), The problem of coupling noise does not occur. Therefore, the sensing in each sense amplifier S / A is not likely to deteriorate due to the coupling noise, and highly reliable reading can be performed.

Further, in the DRAM of this embodiment, since the bit line of each row in the sub memory array SMK is divided into two at the intermediate point, the resistance and capacitance of each bit line BL are smaller than those in the case where it is not divided. Each is halved to half. In addition, each upper layer wiring ML connected to the bit line
However, the resistance and capacitance are much smaller than the bit line BL on the left side or the right side, and the resistance and capacitance are much smaller than those on the bit line BL. Therefore, even in the data path in which the upper layer wiring ML is connected in series to the bit line BL, the resistance and capacitance are considerably smaller than those of the conventional bit line that is not divided. Therefore, it is also advantageous in terms of power consumption and signal propagation speed.

FIG. 6 shows a wiring layout in the vicinity of an intermediate point in each sub memory array SMK according to a modification of this embodiment. Further, FIG. 7 shows the upper layer wiring M in this modification.
The three-dimensional structure of the connection part between L and a bit line is shown typically.

In FIG. 6, left upper layer wirings ML0, ML
0 _-, ML2, ML2 _- ... and the right upper wiring ML1, ML1 _-,
ML3, ML3 _- ... and is not on the same straight line, they are arranged offset by half a pitch from each other. In the vicinity of the connection portion, a wiring M1 in the same layer as the upper wiring ML, a wiring M2 in a layer higher than the upper wiring ML, and a gate wiring FG in a layer lower than the bit line BL are used. Due to the three-dimensional wiring structure, the planar wiring interval is narrowed.

FIG. 8 shows a partial structure of a DRAM according to another embodiment. This embodiment is largely different from the first embodiment described above in that the left bit lines BLi, L (BL of each row divided in the middle point in the sub memory array SMK are divided.
i, L _-) and right bit lines _{BLi, R (BLi, R -} ) of both the upper layer wiring MLi (MLi _-) is the corresponding structure connected to the sense amplifier S / Ai through.

In FIG. 8, each even-numbered sense amplifier S / A0, S / in the left-side sense amplifier bank SBKL is shown.
A2 ... is a transfer gate pair TG0, p for array selection.
, TG2, p ... through the upper layer wiring pairs (M
_{L0, ML0 -), (ML2} , ML2 - connected) ... to. Each upper wiring pair _{(ML0, ML0 -), (} ML
2, ML2 _-) ... is, left the transfer gate-to-TG0, L
, TG2, L ... through corresponding left bit line pairs (B
_{L0, L, BL0, L -} ), (BL2, L, BL2, L -) is connected to ..., right transfer gate pair TG0, R,
Via TG2, R ... Each corresponding right bit line pair (BL0,
_R, BL0, R - are connected) ... to _{-), (BL2, R,} BL2, R.

[0680] Also, the right side sense amplifier bank SBKL
Each of the odd-numbered sense amplifiers S / A1, S / A3,.
Is an array selection transfer gate pair TG1, p, TG
3, p ... through upper layer wiring pairs (ML1, M
_{L1 -), (ML3, ML3} - connected) ... to. Each upper wiring pair _{(ML1, ML1 -), (} ML3, ML
3 _-) ... is left transfer gate pair TG1, L, TG3,
Each corresponding left bit line pair (BL1, L, B
_{L1, L -), (BL3} , L, BL3, L -) is connected to ..., right transfer gate pair TG1, R, TG3, R ...
Through each corresponding right bit line pair (BL1, R, BL1,
R _- is connected) ... to _{-), (BL3, R,} BL3, R.

Left transfer gate pair TG0, L, TG
1, L, TG2, L ... and right side transfer gate pair TG
The gate terminals of 1, L, TG3, L, ... Have a common left bit line selection signal HC from the X address decoder 10 (FIG. 1).
L and right bit line select signal HCR are applied.

The left bit line selection signal HCL and the right bit line selection signal HCR are the upper 3 bits (A8) of the X address signal input to the X address decoder 10.
, A9, A10) are selectively activated according to the logical values. That is, when the sub-memory array SM1 is selected, the left half word line W in the array SM1 is selected.
When any one of L0 to WL255 is selected, the left bit line select signal HCL becomes active (logical value "1") and the left bit line pair (BL0, L, BL)
_{0, L -), (BL1} , L, BL1, L -), (BL2, L, BL2,
L _-) sense amplifier ... each S / A0, S / A1, S
/ A2... When any one of the right half word lines WL256 to WL511 in the array SM1 is selected, the right bit line selection signal HCR becomes active (logical value "1") and the right bit line pair ( B
_{L0, R, BL0, R -} ), (BL1, R, BL1, R -), (BL
_{2, R, BL2, R -} ) ... each sense amplifier S / A0,
Connected to S / A1, S / A2 ...

Array selection transfer gate pair TG1,
A common array selection signal F1 is given to p, TG2, p, TG3, p ... From the X address decoder 10 (FIG. 1). The array selection signal F1 is the drive selection signal ES.
1 corresponds to the sub memory array SM1
Becomes active (logical value "1") when each of the transfer gate pairs TG1, p, TG2, p,
Turn on TG3, p ...

[0720] According to this embodiment, each row of left bit lines _{BLi, L (BLi, L -} ) and right bit lines BLi, R (BLi,
Since each of R ₋ ) is connected to the corresponding sense amplifier S / Ai via the common upper layer wiring MLi (MLi ₋ ), the imbalance in the sensing speed between the left and right bit lines can be eliminated. However, as compared with the above-described first embodiment, the power consumption increases as the number of upper layer wirings ML increases. In addition, when data is read, the upper layer wiring ML and the bit line simultaneously have the same potential amplitude on the same left side or right side of the same row, so that noise due to coupling may occur and the sensing may be affected. Therefore, the upper layer wiring ML
It is necessary to devise a layout to cancel the coupling noise.

In the above embodiment, the transfer gate pair (TGi, a) in the sense amplifier banks SBKL and SBKR is used.
, TGi, b, TGi, c, TGi, d, TGi, p) were provided outside the sense amplifier S / A, but may be incorporated in the sense amplifier S / A.

Further, in the above embodiment, the bit line B of each row is
L was split left and right at the middle point, and the left and right bit lines were connected to the left and right half memory cells of each row, respectively. However, it doesn't have to be divided exactly into left and right. In short, when the word line crossing the left bit line is activated, the left bit line is connected to each corresponding sense amplifier S / A, and when the word line crossing the right bit line is activated, the right bit line is connected to the right side. It suffices to control the bit line selection so that the bit line is connected to each corresponding sense amplifier S / A.

The material, structure, layout and the like of the bit line and the upper layer wiring are not limited to those in the above embodiment, but various selections,
Deformation is possible.

[0760]

As described above, according to the semiconductor memory device of the present invention, the sense amplifiers are arranged in a zigzag pattern on the left and right outer sides of the unit memory array, and the bit line is left on each row or each column in the array. Since the bit line and the right bit line are divided into two, upper layer wiring is provided on the left side or the right side, and both or one of the left bit line and the right bit line is connected to the corresponding sense amplifier via the upper layer wiring. In the hierarchical bit line structure, the wiring pitch margin of the upper wiring can be increased. This allows
It is possible to reduce the possibility that the upper layer wiring will regulate the chip yield.

Also, according to the semiconductor memory device of the present invention, it is possible to prevent coupling noise from the upper layer wiring to the nearby bit lines, and it is possible to guarantee a stable and reliable sensing operation in the sense amplifier. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a DRAM according to an embodiment of the present invention.

FIG. 2 is an enlarged block diagram showing a part of the configuration of the DRAM of FIG.

FIG. 3 is a diagram showing a wiring layout in the vicinity of an intermediate point in the sub memory array in the hierarchical bit line configuration of the embodiment.

FIG. 4 is a diagram showing a wiring layout in the vicinity of a transfer gate in a sense amplifier bank in the hierarchical bit line configuration of the embodiment.

FIG. 5 is a diagram showing timings of signals at various parts during data reading in the DRAM of the embodiment.

FIG. 6 is a diagram showing a wiring layout in the vicinity of an intermediate point in a sub memory array according to a modification of the embodiment.

7 is a diagram schematically showing a three-dimensional structure of a connection portion between an upper layer wiring and a bit line in the modification example of FIG.

FIG. 8 is a block diagram showing a partial configuration of a DRAM according to a second embodiment.

FIG. 9 is a circuit diagram showing a configuration of a typical memory array of a DRAM.

FIG. 10 is a diagram showing a layout and a wiring layout of sense amplifiers and bit lines in a conventional technique.

FIG. 11 is a diagram showing a layout and wiring layout of sense amplifiers and bit lines in another conventional technique.

FIG. 12 is a circuit diagram showing a conventional hierarchical bit line configuration.

[Explanation of symbols]

10 X address decoder SM0, SM1, ... SM3 sub memory array WD0, WD1, ... WD3 word line drive circuit S / A0, S / A1, S / A2 ... sense amplifier _{BL0, L, BL0, L -} , BL2, L , BL2, L _- ... right bit lines _{BL1, L, BL1, L -} , BL3, L, BL3, L - ... left bit lines _{ML0, ML0 -, ML2, ML2} - ... right upper wiring ML1, ML1 _-, ML3, ML3 _- ... left upper wiring _{TG0, a, TG0, a -} ... first transfer gate _{TG0, b, TG0, b -} ... second transfer gates _{TG1, c, TG1, c -} ... third transfer gates TG1, d, TG1, d _- ... fourth transfer gates TG0, L, TG1, L ... left transfer gate TG0, R, TG1, R ... right transfer gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kentaka Saito 2355, Kihara, Miura-mura, Inashiki-gun, Ibaraki Japan Texas Instruments Co., Ltd. (72) Tadashi Tachibana 2355, Kihara, Miura-mura, Inashiki-gun, Ibaraki Within KISSA Instruments Co., Ltd.

Claims (4)

[Claims] 1. Sense amplifiers are arranged in a zigzag pattern on the left and right outer sides of each unit memory array and are separated into a plurality of memory cells on the left side and a plurality of memory cells on the right side of each row or each column in the memory array. The left-side bit line and the right-side bit line are connected to each other, and each of the left-side sense amplifiers is connected to the corresponding left-side bit line of the row or column and is provided in a layer above the bit line. The right-side bit line is connected to the right-side bit line of the corresponding row or column through the left-side upper layer wiring, and each of the right-side sense amplifiers is connected to the right-side bit line of the corresponding row or column and the right-side bit A semiconductor memory device connected to the left bit line of the corresponding row or column through the upper layer wiring on the right side provided in a layer above the line. Place. 2. The left-side sense amplifier is connected to a left-side bit line of the corresponding row or column via a first transfer gate, and left-side of the corresponding row or column via a second transfer gate. The right-side sense amplifier is connected to an upper layer wiring, the right-side sense amplifier is connected to the right-side bit line of the corresponding row or column through a third transfer gate, and the right-side sense amplifier of the corresponding row or column is connected through a fourth transfer gate. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to a right upper wiring. 3. Sense amplifiers are arranged in a zigzag pattern on the left and right outer sides of each unit memory array and are separated into a plurality of memory cells on the left side and a plurality of memory cells on the right side of each row or column in the memory array. The left-side bit line and the right-side bit line are connected to each other, and the left-side bit lines in the row or column corresponding to the left-side bit lines are connected via the left-side upper layer wiring provided in a layer higher than the bit line. Line and the right-side bit line, and the right-side bit line and the right-side bit of the row or column corresponding to the right-side upper layer wiring in which each of the right-side sense amplifiers is provided in a layer higher than the bit line A semiconductor memory device connected to a line. 4. The semiconductor memory device according to claim 3, wherein each of the upper layer wirings is connected to the left bit line and the right bit line of the corresponding row or column through first and second transfer gates. .