JPH09293745A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH09293745A
JPH09293745A JP8102596A JP10259696A JPH09293745A JP H09293745 A JPH09293745 A JP H09293745A JP 8102596 A JP8102596 A JP 8102596A JP 10259696 A JP10259696 A JP 10259696A JP H09293745 A JPH09293745 A JP H09293745A
Authority
JP
Japan
Prior art keywords
wire
tip
bonding
header
lead pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8102596A
Other languages
Japanese (ja)
Inventor
Reiji Ono
玲司 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Development and Engineering Corp
Original Assignee
Toshiba Corp
Toshiba Electronic Engineering Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Electronic Engineering Co Ltd filed Critical Toshiba Corp
Priority to JP8102596A priority Critical patent/JPH09293745A/en
Publication of JPH09293745A publication Critical patent/JPH09293745A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be wire-bonded well through a simpler wire bonding process. SOLUTION: A semiconductor element 15 is mounted with its primary surface having a certain angle to the primary surface 11a of a header 11, and the tip of a lead pin 12-1 provided vertical to the primary surface of the header 11 and the pad of the semiconductor element 15 are electrically connected together for the formation of a semiconductor device, wherein the bonding area of the tip of the lead pin 12-1 is made to have a curved surface. Therefore, a metal wire is fixed to the semiconductor element 15 by pressure, and when the other end of the metal wire is bonded to the tip of the lead pin 12-1 by pressure, the header 11 is not required to be rotated to make the tip of the lead pin 12-1 horizontal, so that a wire bonding process can be simplified. The header 11 is not required to be rotated, so that a metal wire is hardly twisted, a normal wire loop can be obtained, and a metal wire can be restrained from deteriorating in tensile strength and touching an unnecessary object.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】この発明は、ワイヤ・ボンデ
ィングで電気的な接続が行われる半導体装置に関し、特
に、接続される２つのボンディング領域が互いに傾斜し
て配置される光通信用半導体素子に好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is electrically connected by wire bonding, and is particularly suitable for a semiconductor element for optical communication in which two bonding regions to be connected are arranged to be inclined to each other. It is something.

【０００２】[0002]

【従来の技術】半導体装置の実装工程では、半導体素子
を他の部品や回路と電気的に接続するためにワイヤ・ボ
ンディングが広く用いられている。ワイヤ・ボンディン
グでは、キャピラリの先端で金属製ワイヤをボンディン
グ領域に圧着することによって電気的な接続を行う。こ
の際、キャピラリの先端とボンディング領域との間で金
属製ワイヤを押し潰すため、キャピラリの先端とボンデ
ィング領域が平行でないと均等にワイヤを押し潰すこと
ができない。よって、良好なボンダビリティを得るため
には、ボンディング領域とキャピラリの先端が平行にな
っていることが望ましい。また、正常なワイヤ・ループ
を得るためには、接続される２つのボンディング領域が
平行でなければならない。2. Description of the Related Art In the process of mounting a semiconductor device, wire bonding is widely used to electrically connect a semiconductor element to other parts and circuits. In wire bonding, a metal wire is pressure-bonded to the bonding region at the tip of the capillary to make an electrical connection. At this time, since the metal wire is crushed between the tip of the capillary and the bonding area, the wire cannot be crushed evenly unless the tip of the capillary and the bonding area are parallel to each other. Therefore, in order to obtain good bondability, it is desirable that the bonding region and the tip of the capillary are parallel to each other. Also, in order to obtain a normal wire loop, the two bonding areas to be connected must be parallel.

【０００３】しかしながら、一般に、光通信用半導体素
子、特に受光素子は戻り光低減のためにヘッダーの主面
に対して傾斜して搭載されている。図４は、上記受光素
子の一例としてフォトダイオードをヘッダーに搭載した
状態の概略的な部分拡大図である。図４において、１１
はヘッダー本体で、この本体１１の主面１１ａには、底
部が主面１１ａに対して１５度の傾斜を有する溝１１
ｂ、及び貫通孔１１ｃが形成されている。１２はリード
ピンで、このリードピン１２は上記貫通孔１１ｃにガラ
ス１３でハーメチックシールされ、リードピン１２の先
端部は主面１１ａより上に突出している。１４は上記ヘ
ッダー本体１１の溝１１ｂ上に固着されたセラミック・
サブマウントで、このセラミック・サブマウント１４上
にフォトダイオード１５のチップが搭載されている。１
６はボンディング・ワイヤ（Ａｕワイヤ）で、このボン
ディング・ワイヤ１６によって、上記フォトダイオード
１５のボンディング・パッドとリードピン１２の先端部
とが電気的に接続されている。However, in general, semiconductor devices for optical communication, particularly light receiving devices, are mounted with an inclination with respect to the main surface of the header in order to reduce return light. FIG. 4 is a schematic partially enlarged view showing a state in which a photodiode is mounted on the header as an example of the light receiving element. In FIG. 4, 11
Is a header main body, and the main surface 11a of the main body 11 has a groove 11 whose bottom has an inclination of 15 degrees with respect to the main surface 11a.
b and a through hole 11c are formed. Reference numeral 12 is a lead pin. The lead pin 12 is hermetically sealed in the through hole 11c with glass 13. The tip of the lead pin 12 projects above the main surface 11a. 14 is a ceramic fixed on the groove 11b of the header body 11;
In the submount, the chip of the photodiode 15 is mounted on the ceramic submount 14. 1
Reference numeral 6 denotes a bonding wire (Au wire). The bonding wire 16 electrically connects the bonding pad of the photodiode 15 and the tip of the lead pin 12.

【０００４】次に、上記フォトダイオード１５の実装工
程を説明する。まず、ヘッダー本体１１の溝１１ｂに、
セラミック・サブマウント１４がＡｕＧｅ半田で固着さ
れる。上記セラミック・サブマウント１４を固着する際
には、ヘッダー本体１１は溝１１ｂの傾斜面が水平にな
るようにマウント治具に設置されている。その後、セラ
ミック・サブマウント１４上にフォトダイオード１５が
ＡｕＳｎ半田で固着される。このフォトダイオード１５
もセラミック・サブマウント１４のマウントと同様に、
ヘッダー本体１１をセラミック・サブマウント１１の表
面が水平になるようにマウント治具に設置した状態でマ
ウントされる。Next, a mounting process of the photodiode 15 will be described. First, in the groove 11b of the header body 11,
The ceramic submount 14 is fixed with AuGe solder. When fixing the ceramic submount 14, the header body 11 is installed on the mount jig so that the inclined surface of the groove 11b becomes horizontal. Then, the photodiode 15 is fixed onto the ceramic submount 14 with AuSn solder. This photodiode 15
Like the mount of the ceramic submount 14,
The header body 11 is mounted in a state where it is installed on a mounting jig so that the surface of the ceramic submount 11 is horizontal.

【０００５】次に、ワイヤ・ボンディングを行い、フォ
トダイオード１５のボンディング・パッドとリードピン
１２の先端部をボンディング・ワイヤ１６で接続する。
このワイヤ・ボンディングに際しては、最初にフォトダ
イオード１５の主面が水平になるようにヘッダー本体１
１を設置し、ボンディング・ワイヤ１６を圧着する。こ
の状態でリードピン１２の先端部のボンディング領域が
水平になるようにヘッダー本体１１を回転させ、今度は
ボンディング・ワイヤ１６をリードピン１２の先端部に
圧着する。Next, wire bonding is performed to connect the bonding pad of the photodiode 15 and the tip of the lead pin 12 with the bonding wire 16.
At the time of this wire bonding, first, the header body 1 is arranged so that the main surface of the photodiode 15 becomes horizontal.
1 is set and the bonding wire 16 is crimped. In this state, the header body 11 is rotated so that the bonding region at the tip of the lead pin 12 becomes horizontal, and the bonding wire 16 is crimped to the tip of the lead pin 12 this time.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、上述し
たような従来の技術では、半導体素子の主面が水平にな
るようにヘッダーを設置して半導体素子にボンディング
・ワイヤを圧着した後、半導体素子の主面に対して傾斜
しているリードピンの先端部にボンディング・ワイヤを
圧着するため、リードピンの先端部が水平になるように
再度ヘッダーを回転させる必要がある。このため、ワイ
ヤ・ボンディング工程が繁雑になると共に、ボンディン
グ・ワイヤに捩じれが生じるため、正常なワイヤ・ルー
プが得られず、ワイヤ引っ張り強度の低下やワイヤタッ
チ（他の電気的部位への接触）の原因となる。However, in the prior art as described above, the header is installed so that the main surface of the semiconductor element is horizontal and the bonding wire is crimped to the semiconductor element, and then the semiconductor element Since the bonding wire is crimped onto the tip of the lead pin that is inclined with respect to the main surface, it is necessary to rotate the header again so that the tip of the lead pin becomes horizontal. For this reason, the wire bonding process becomes complicated, and since the bonding wire is twisted, a normal wire loop cannot be obtained, and the wire tensile strength is reduced and the wire touch (contact with other electrical parts). Cause of.

【０００７】この発明は上記のような事情に鑑みてなさ
れたもので、その目的とするところは、互いに傾斜して
いるボンディング領域間でも簡単なワイヤ・ボンディン
グ工程で接続でき、ワイヤ・ループ形状を損なうことな
く良好なワイヤ・ボンディングが可能な半導体装置を提
供することにある。The present invention has been made in view of the above circumstances. The object of the present invention is to enable connection between bonding regions that are inclined to each other by a simple wire bonding process and to form a wire loop shape. An object of the present invention is to provide a semiconductor device capable of performing good wire bonding without damage.

【０００８】[0008]

【課題を解決するための手段】この発明の請求項１に記
載した半導体装置は、ヘッダーの主面に対して半導体素
子の主面が傾斜して搭載され、上記ヘッダーの主面に垂
直に設置されたリードピンの先端部と上記半導体素子の
主面とが金属製ワイヤで電気的に接続される半導体装置
において、上記リードピンの先端部における上記金属製
ワイヤとの接続領域が曲面であることを特徴としてい
る。According to a first aspect of the present invention, a semiconductor device is mounted in such a manner that a main surface of a semiconductor element is inclined with respect to a main surface of a header and is installed perpendicularly to the main surface of the header. In a semiconductor device in which the tip end of the lead pin and the main surface of the semiconductor element are electrically connected by a metal wire, the connection region between the tip end of the lead pin and the metal wire is a curved surface. I am trying.

【０００９】また、請求項２に示すように、前記リード
ピンの先端部における曲面の曲率半径は、前記金属製ワ
イヤの直径よりも大きいことを特徴とする。請求項３に
示すように、前記半導体素子は、前記ヘッダーの主面に
形成された傾斜部上に直接搭載されることを特徴とす
る。Further, as described in claim 2, the radius of curvature of the curved surface at the tip of the lead pin is larger than the diameter of the metal wire. According to a third aspect of the present invention, the semiconductor element is directly mounted on an inclined portion formed on the main surface of the header.

【００１０】請求項４に示すように、前記半導体素子
は、前記ヘッダーの主面に形成された傾斜部上にサブマ
ウントを介して搭載されることを特徴とする。更に、請
求項５に示すように、前記半導体素子は、受光素子であ
ることを特徴とする。According to a fourth aspect of the present invention, the semiconductor element is mounted on the inclined portion formed on the main surface of the header via a submount. Further, as described in claim 5, the semiconductor element is a light receiving element.

【００１１】請求項１のような構成によれば、リードピ
ンの先端部における金属製ワイヤとの接続領域が曲面で
あるので、半導体素子に金属製ワイヤを圧着した後、リ
ードピンの先端部に金属製ワイヤを圧着する際に、リー
ドピンの先端部が水平になるようにヘッダーを回転させ
る必要がなく、ワイヤ・ボンディング工程を簡単化でき
る。しかも、ヘッダーを回転させないので金属製ワイヤ
に捩じれが発生し難くなり、正常なワイヤ・ループが得
られるので、ワイヤ引っ張り強度の低下やワイヤタッチ
を抑制できる。According to the first aspect of the invention, since the connecting region of the lead pin with the metal wire is a curved surface, the metal wire is pressure-bonded to the semiconductor element and then the metal is attached to the tip of the lead pin. When crimping the wire, it is not necessary to rotate the header so that the tip of the lead pin becomes horizontal, which simplifies the wire bonding process. Moreover, since the header is not rotated, the metal wire is less likely to be twisted, and a normal wire loop can be obtained, so that reduction in wire tensile strength and wire touch can be suppressed.

【００１２】請求項２に記載したように、リードピンの
先端部における曲面の曲率半径を金属製ワイヤの直径よ
りも大きくすれば、ボンディング領域が曲面であっても
実質的に平面と見做してワイヤ・ボンディングを行うこ
とができる。As described in claim 2, if the radius of curvature of the curved surface at the tip of the lead pin is made larger than the diameter of the metal wire, even if the bonding region is curved, it is regarded as substantially flat. Wire bonding can be performed.

【００１３】請求項３に記載したように、半導体素子は
ヘッダーの主面に形成された傾斜部上に直接搭載しても
良く、請求項４に記載したように、傾斜部上にサブマウ
ントを介して搭載しても良い。請求項５に記載したよう
に、半導体素子が受光素子の場合には、受光素子の主面
がヘッダーの主面に対して傾斜して搭載されるので、戻
り光を低減できる。As described in claim 3, the semiconductor element may be directly mounted on the slanted portion formed on the main surface of the header. As described in claim 4, the submount is mounted on the slanted portion. You may install through. As described in claim 5, when the semiconductor element is a light-receiving element, the main surface of the light-receiving element is mounted so as to be inclined with respect to the main surface of the header, so that the returning light can be reduced.

【００１４】[0014]

【発明の実施の形態】以下、この発明の実施の形態につ
いて図面を参照して説明する。図１（ａ），（ｂ）はそ
れぞれ、この発明の第１の実施の形態に係る半導体装置
について説明するためのもので、モニター用フォトダイ
オードをヘッダーに搭載した状態の概略的な部分拡大図
であり、（ａ）図はワイヤ・ボンディング前の状態を示
す図、（ｂ）図はワイヤ・ボンディング後の状態を示す
図である。また、図２（ａ）〜（ｃ）はそれぞれ、上記
フォトダイオードの搭載前の状態を示しており、（ａ）
図は平面図、（ｂ）図は（ａ）図のＡ−Ａ´線に沿った
断面図、（ｃ）図は（ａ）図のＢ−Ｂ´線に沿った断面
図である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 (a) and 1 (b) are each for explaining a semiconductor device according to a first embodiment of the present invention, and are schematic partial enlarged views of a state in which a monitor photodiode is mounted on a header. FIG. 7A is a diagram showing a state before wire bonding, and FIG. 8B is a diagram showing a state after wire bonding. In addition, FIGS. 2A to 2C each show a state before mounting the photodiode, and FIG.
The figure is a plan view, the figure (b) is a sectional view taken along the line AA 'in the figure (a), and the figure (c) is a sectional view taken along the line BB' in the figure (a).

【００１５】図２（ａ）〜（ｃ）に示す如く、ＴＯ−４
６型ヘッダー本体１１の主面１１ａの中央部には底部が
主面１１ａに対して１５度の傾斜を有する溝１１ｂが設
けられ、周辺部には貫通孔１１ｃ−１，１１ｃ−２，１
１ｃ−３が設けられている。リードピン１２−１，１２
−２，１２−３はそれぞれ、上記貫通孔１１ｃ−１，１
１ｃ−２，１１ｃ−３にガラス１３−１，１３−２，１
３−３でハーメチックシールされ、各リードピン１２−
１，１２−２，１２−３の先端部は主面１１ａから上に
突出している。また、リードピン１２−１，１２−２の
先端部は、例えば放電加工により丸め処理が施され、こ
れらリードピンの直径５００μｍと同程度の直径を持つ
半球形となっている。一方、リードピン１２−３の先端
部は平らに潰されており、リードピン１２−４はヘッダ
ー本体１１の裏面に溶接されている。As shown in FIGS. 2 (a) to 2 (c), the TO-4
A groove 11b having a bottom portion inclined at an angle of 15 degrees with respect to the main surface 11a is provided at the center of the main surface 11a of the 6-type header body 11, and through holes 11c-1, 11c-2, 1 are provided in the peripheral portion.
1c-3 is provided. Lead pins 12-1, 12
-2 and 12-3 are the through holes 11c-1 and 1 respectively.
Glass 13-1, 13-2, 1 on 1c-2, 11c-3
Hermetically sealed with 3-3, each lead pin 12-
The tip portions of 1, 12-2 and 12-3 project upward from the main surface 11a. Further, the tip portions of the lead pins 12-1 and 12-2 are rounded by, for example, electric discharge machining, and have a hemispherical shape having a diameter of about 500 μm. On the other hand, the tip of the lead pin 12-3 is flattened, and the lead pin 12-4 is welded to the back surface of the header body 11.

【００１６】次に、上記図２（ａ）〜（ｃ）に示したヘ
ッダー本体１１へのフォトダイオードの実装工程につい
て図１（ａ），（ｂ）を参照して説明する。まず、ヘッ
ダー本体１１の主面１１ａを１５度傾け、溝１１ｂの底
部の傾斜面が水平になるようにしてマウント治具に保持
し、この溝１１ｂ上に両面が金属で覆われたセラミック
・サブマウント１４をＡｕＧｅ半田で固着する。その
後、上記セラミック・サブマウント１４上にフォトダイ
オード１５をＡｕＳｎ半田で固着する（図２（ａ）参
照）。Next, the process of mounting the photodiode on the header body 11 shown in FIGS. 2 (a) to 2 (c) will be described with reference to FIGS. 1 (a) and 1 (b). First, the main surface 11a of the header body 11 is tilted by 15 degrees, and the bottom surface of the groove 11b is held by a mounting jig so that the bottom inclined surface is horizontal, and a ceramic sub whose both surfaces are covered with metal on the groove 11b. The mount 14 is fixed with AuGe solder. After that, the photodiode 15 is fixed onto the ceramic submount 14 with AuSn solder (see FIG. 2A).

【００１７】次に、フォトダイオード１５のボンディン
グ・パッドが水平になるようにワイヤ治具に保持し、直
径２５μｍ程度のボンディング・ワイヤ（Ａｕワイヤ）
１６を用いてボンディング・パッドにファーストワイヤ
・ボンディングを行う。その後、ヘッダー本体１１を固
定したままでボンディング・ワイヤ１６を引き出しつつ
キャピラリの先端をリードピン１２−１の先端部に移動
させ、半球形の先端部上にセカンドワイヤ・ボンディン
グを行う（図２（ｂ）参照）。Next, a bonding wire (Au wire) having a diameter of about 25 μm is held by a wire jig so that the bonding pad of the photodiode 15 becomes horizontal.
First wire bonding is performed on the bonding pad using 16. After that, while the header body 11 is fixed, the tip of the capillary is moved to the tip of the lead pin 12-1 while pulling out the bonding wire 16 to perform the second wire bonding on the tip of the hemisphere (see FIG. 2B. )reference).

【００１８】上記ワイヤ・ボンディング工程において、
ボンディング領域は、一般にボールボンディング方式で
直径約１００μｍ、ウェッジボンディング方式で約５０
×１００μｍが必要となる。これに対し、リードピン１
２−１，１２−２の直径は５００μｍ程度、ボンディン
グ・ワイヤ１６の直径は２５μｍ程度であり、ボンディ
ング領域はリードピン１２−１，１２−２の先端部に比
べて十分狭く、且つボンディング・ワイヤ１６に比べて
十分に広い。従って、セカンドワイヤ・ボンディング時
に、半球形のリードピン１２−１，１２−２の先端部に
おいてフォトダイオード１５の主面の傾斜角に近似した
ボンディング領域を選択できる。しかも、リードピン１
２−１，１２−２の先端部の曲率半径はボンディング・
ワイヤ１６の直径よりも十分に大きいので、ボンディン
グ領域を実質的に平面と見做してワイヤ・ボンディング
が可能である。In the above wire bonding process,
Generally, the bonding area is about 100 μm in diameter by the ball bonding method and about 50 by the wedge bonding method.
× 100 μm is required. On the other hand, lead pin 1
The diameters of 2-1 and 12-2 are about 500 μm, and the diameter of the bonding wire 16 is about 25 μm. The bonding area is sufficiently narrower than the tips of the lead pins 12-1 and 12-2, and the bonding wire 16 is Wide enough compared to. Therefore, at the time of the second wire bonding, it is possible to select a bonding region close to the inclination angle of the main surface of the photodiode 15 at the tip of the hemispherical lead pins 12-1 and 12-2. Moreover, the lead pin 1
The radius of curvature of the tip of 2-1 and 12-2 is bonding.
It is sufficiently larger than the diameter of the wire 16 so that the bonding area can be regarded as a substantially flat surface for wire bonding.

【００１９】その後、上記フォトダイオード１５、上記
リードピン１２−１，１２−２，１２−３の先端部、上
記ボンディング・ワイヤ１６等をパッケージに封止して
半導体装置を完成する。After that, the photodiode 15, the tips of the lead pins 12-1, 12-2, 12-3, the bonding wire 16 and the like are sealed in a package to complete a semiconductor device.

【００２０】上記のような構成によれば、ワイヤ・ボン
ディングが行われるリードピン１２−１，１２−２の先
端部におけるボンディング領域が曲面であるので、フォ
トダイオード１５のボンディング・パッドにボンディン
グ・ワイヤ１６を圧着した後、リードピン１２−１，１
２−２の先端部にボンディング・ワイヤ１６を圧着する
際に、リードピン１２−１，１２−２の先端部が水平に
なるようにヘッダー本体１１を回転させる必要がなく、
ワイヤ・ボンディング工程を簡単化できる。また、ヘッ
ダー本体１１を回転させないのでボンディング・ワイヤ
１６に捩じれが発生し難くなり、正常なワイヤ・ループ
が得られるので、ワイヤ引っ張り強度の低下やワイヤタ
ッチを抑制できる。According to the above structure, since the bonding regions at the tips of the lead pins 12-1 and 12-2 where wire bonding is performed are curved surfaces, the bonding wire 16 is bonded to the bonding pad of the photodiode 15. After crimping, the lead pins 12-1, 1
When the bonding wire 16 is crimped to the tip of 2-2, it is not necessary to rotate the header body 11 so that the tips of the lead pins 12-1 and 12-2 are horizontal,
The wire bonding process can be simplified. Further, since the header body 11 is not rotated, the bonding wire 16 is less likely to be twisted, and a normal wire loop is obtained, so that reduction in wire tensile strength and wire touch can be suppressed.

【００２１】図３は、この発明の第２の実施の形態につ
いて説明するためのもので、リードピン１２−１（１２
−２も同様）の先端部近傍を抽出し、拡大して示してい
る。図示する如く、リードピン１２−１の先端部がこの
リードピンの直径よりも幅広く形成されている。FIG. 3 is for explaining a second embodiment of the present invention, in which the lead pin 12-1 (12
(--2 is also the same), the vicinity of the tip portion is extracted and enlarged. As shown, the tip of the lead pin 12-1 is formed wider than the diameter of the lead pin.

【００２２】このような構成によれば、リードピンの先
端部のボンディング領域を広くでき、且つリードピンの
先端部の曲率半径も大きくなるので、ワイヤ・ボンディ
ングが容易になる。According to this structure, the bonding area at the tip of the lead pin can be widened and the radius of curvature of the tip of the lead pin is also large, so that wire bonding becomes easy.

【００２３】なお、この発明は、上述した第１，第２の
実施の形態に限定されるものではなく、要旨を逸脱しな
い範囲で種々変形して実施可能である。例えば、半導体
素子がモニター用フォトダイオード１５の場合を例にと
って説明したが、他の半導体素子を搭載しても良いのは
勿論である。また、半導体素子が溝１１ｂの底部の傾斜
面上にセラミック・サブマウント１４を介して搭載され
る例を示したが、半導体素子を溝１１ｂの底部の傾斜面
上に直接搭載しても良い。更に、溝１１ｂの底部の傾斜
がヘッダー本体１１の主面１１ａに対して１５度の傾き
を有する場合について説明したが、必要に応じて適宜設
定すれば良く、この角度に限られないのはいうまでもな
い。The present invention is not limited to the above-described first and second embodiments, but can be variously modified and implemented without departing from the scope of the invention. For example, although the case where the semiconductor element is the monitor photodiode 15 has been described as an example, it goes without saying that another semiconductor element may be mounted. Further, although the example in which the semiconductor element is mounted on the inclined surface at the bottom of the groove 11b via the ceramic submount 14 is shown, the semiconductor element may be directly mounted on the inclined surface at the bottom of the groove 11b. Further, the case where the inclination of the bottom of the groove 11b has an inclination of 15 degrees with respect to the main surface 11a of the header body 11 has been described, but it may be appropriately set as necessary, and it is not limited to this angle. There is no end.

【００２４】[0024]

【発明の効果】以上説明したように、この発明によれ
ば、互いに傾斜しているボンディング領域間でも簡単な
ワイヤ・ボンディング工程で接続でき、ワイヤ・ループ
形状を損なうことなく良好なワイヤ・ボンディングが可
能な半導体装置が得られる。As described above, according to the present invention, it is possible to connect even the bonding regions that are inclined to each other by a simple wire bonding process, and good wire bonding can be performed without damaging the wire loop shape. A possible semiconductor device is obtained.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明の第１の実施の形態に係る半導体装置
について説明するためのもので、モニター用フォトダイ
オードをヘッダーに搭載した状態の概略的な部分拡大図
であり、（ａ）図はワイヤボンディング前の状態を示す
図、（ｂ）図はワイヤボンディング後の状態を示す図。FIG. 1 is a view for explaining a semiconductor device according to a first embodiment of the present invention, and is a schematic partial enlarged view of a state where a monitoring photodiode is mounted on a header, and FIG. The figure which shows the state before wire bonding, (b) figure is a figure which shows the state after wire bonding.

【図２】この発明の第１の実施の形態に係る半導体装置
について説明するためのもので、フォトダイオードの搭
載前の状態を示しており、（ａ）図は平面図、（ｂ）図
は（ａ）図のＡ−Ａ´線に沿った断面図、（ｃ）図は
（ａ）図のＢ−Ｂ´線に沿った断面図。2A and 2B are views for explaining a semiconductor device according to a first embodiment of the present invention, showing a state before mounting a photodiode, wherein FIG. 2A is a plan view and FIG. A sectional view taken along the line A-A 'of the figure (a), and a sectional view taken along the line BB' of the figure (a).

【図３】この発明の第２の実施の形態に係る半導体装置
について説明するためのもので、リードピンの先端部近
傍を抽出し、拡大して示す図。FIG. 3 is a view for explaining a semiconductor device according to a second embodiment of the present invention, in which the vicinity of the tip of the lead pin is extracted and enlarged.

【図４】従来の半導体装置について説明するためのもの
で、フォトダイオードをヘッダーに搭載した状態の概略
的な部分拡大図。FIG. 4 is a schematic partial enlarged view of a conventional semiconductor device, in which a photodiode is mounted on a header.

【符号の説明】[Explanation of symbols]

１１…ヘッダー本体、１１ａ…主面、１１ｂ…溝、１１
ｃ−１，１１ｃ−２，１１ｃ−３…貫通孔、１２−１，
１２−２，１２−３，１２−４…リードピン、１３…ガ
ラス、１４…セラミック・サブマウント、１５…フォト
ダイオード（半導体素子）、１６…ボンディング・ワイ
ヤ（金属製ワイヤ）。11 ... Header body, 11a ... Main surface, 11b ... Groove, 11
c-1, 11c-2, 11c-3 ... through-hole, 12-1,
12-2, 12-3, 12-4 ... Lead pin, 13 ... Glass, 14 ... Ceramic submount, 15 ... Photodiode (semiconductor element), 16 ... Bonding wire (metal wire).

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 ヘッダーの主面に対して半導体素子の主
面が傾斜して搭載され、上記ヘッダーの主面に垂直に設
置されたリードピンの先端部と上記半導体素子の主面と
が金属製ワイヤで電気的に接続される半導体装置におい
て、上記リードピンの先端部における上記金属製ワイヤ
との接続領域が曲面であることを特徴とする半導体装
置。1. A main surface of a semiconductor element is mounted so as to be inclined with respect to a main surface of a header, and a tip of a lead pin installed perpendicularly to the main surface of the header and a main surface of the semiconductor element are made of metal. A semiconductor device electrically connected by a wire, wherein a connection region of the tip of the lead pin with the metal wire is a curved surface. 【請求項２】 前記リードピンの先端部における曲面の
曲率半径は、前記金属製ワイヤの直径よりも大きいこと
を特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the radius of curvature of the curved surface at the tip of the lead pin is larger than the diameter of the metal wire. 【請求項３】 前記半導体素子は、前記ヘッダーの主面
に形成された傾斜部上に直接搭載されることを特徴とす
る請求項１または２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the semiconductor element is directly mounted on an inclined portion formed on the main surface of the header. 【請求項４】 前記半導体素子は、前記ヘッダーの主面
に形成された傾斜部上にサブマウントを介して搭載され
ることを特徴とする請求項１または２に記載の半導体装
置。4. The semiconductor device according to claim 1, wherein the semiconductor element is mounted on an inclined portion formed on the main surface of the header via a submount. 【請求項５】 前記半導体素子は、受光素子であること
を特徴とする請求項１ないし４いずれか１つの項に記載
の半導体装置。5. The semiconductor device according to claim 1, wherein the semiconductor element is a light receiving element.
JP8102596A 1996-04-24 1996-04-24 Semiconductor device Pending JPH09293745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8102596A JPH09293745A (en) 1996-04-24 1996-04-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8102596A JPH09293745A (en) 1996-04-24 1996-04-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH09293745A true JPH09293745A (en) 1997-11-11

Family

ID=14331628

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8102596A Pending JPH09293745A (en) 1996-04-24 1996-04-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH09293745A (en)

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