JPH09293003A - Computers and computer systems - Google Patents

Abstract

(57) [Abstract] [Problem] To improve the performance of a computer. As a branch instruction of a control program, a logical address of a branch destination is described in an instruction operand, and a head address (physical address) of each program is described in a page management table 5b. When a branch instruction is executed, the branch destination logical address of the instruction operand is read, the address at the program start time of the page management table 5b is read, and the read destination addresses are added to obtain the branch destination physical address of the control program. By executing the program of the physical address, the branch block referred to at the time of the conventional branch instruction is unnecessary, the memory size is reduced, and the execution performance of the program is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer that executes a control program to control a plant, and the like.
It relates to a computer system consisting of multiple computers,
In particular, it is intended to improve performance such as improvement of processing performance and maintainability.

[0002]

[Prior art]

Conventional Technology 1. FIG. 37 shows, for example, Japanese Patent Laid-Open No. 4-33200.
It is a block diagram which shows the conventional computer system shown by the 2nd publication. In the figure, reference numeral 1 is a maintenance tool for developing and maintaining a control program 5a necessary for executing the processor (computer) 10 and control information such as control data and a start management table, and a terminal such as a personal computer is usually used.

A hard disk device 1a stores control information such as a control program. 2 is the system bus, 3
Is an I connected to the processor 10 by the system bus 2.
O interfaces 4 are plant systems of controlled equipment.

Reference numeral 10 denotes a processor (computer) having the following structure. 5 is a memory of the processor 10, 5a is a control program, 5b is a control program 5a in the memory 5
The page management table 5c for holding the management information when stored above is a branch block for storing the branch destination logical address, and holds the branch block information specified by the control program 5a rewriting request from the maintenance tool 1.

The branch block information is information for holding one or a plurality of branch destination logical addresses with the number of instruction steps from the head of the control program as a branch destination logical address. 6 is a request processing unit for registering the control information sent from the maintenance tool 1 in the processor 10, and 6a is the maintenance tool 1
The receiving section 6b receives the control information from the control tool 6b, and the transmitting section 6b sends the result of processing the control information to the maintenance tool 1.

Reference numeral 6c is a program rewriting processing unit for performing processing for storing the control information from the maintenance tool 1 as the control program 5a, and 7 is a program execution unit for executing the control program 5a.

FIG. 40 shows an example of the configuration of the page management table 5 of the conventional computer system, in which the address (physical offset address from the beginning of the memory) where each module-divided control program is placed is a program number. Hold in correspondence with.

FIG. 41 shows the structure of a branch instruction of a conventional computer system, and its operand part holds a branch target block number which is an identifier for obtaining a branch target logical address from a branch block. .

FIG. 42 is a diagram for explaining the branch processing and shows a case where the branch processing is performed based on a branch instruction. The program 5 on the left side of the figure represents the control program to be processed in this case, and this program is stored in the control program 5a on the memory 5 shown in FIG.

Next, the operation will be described with reference to the flow charts of FIGS. 38 and 39. First, the flow of processing when the program rewriting in FIG. 38 is requested will be described. (1) The program rewriting processing request sent from the maintenance tool 1 is received by the receiving unit 6a of the request processing unit 6 and sent to the program rewriting processing unit 6c.

(2) The program rewrite processing section 6c
The control program of the designated module (in FIG. 42,
The program 5) is written in the control program 5a area of the memory unit 5 (ST000),

(3) The writing position to the control program 5a is expressed by a physical address which is an offset address from the head of the memory unit 5, and is registered in the page management table 5b in correspondence with the designated program number (ST00).
1). That is, as shown in FIG. 42, the page management table 5b
Is the physical address from the beginning of each program of the control program 5 in the order of "program 1, program 2, ...", "address 1, address 2, ... address 5, ...
・ ”Is stored.

(4) Next, the branch block information of the designated module is written in the branch block 5c area of the memory unit 5 (ST002). The branch block 5c stores the physical address as the address 4 at the third position of the branch block 5c when the "branch instruction 3" is present in the control program (program 5) as shown in FIG. Then, the address 4 and the start address 5 of the program 5 of the page management program 5b (a in FIG. 42) become the "branch destination physical address", which is the position of the branch program of the branch destination of the control program 5a. .

The flow of branch instruction processing when executing the branch instruction of FIG. 39 will be described. (1) The program execution unit 7 extracts an instruction from the control program 5a of the memory unit 5 (ST005). (2) If the instruction is a branch instruction, for example, the branch instruction 3 in FIG.
If so (ST006), (3) the branch target block number of the operand part shown in FIG. 41 is used as an identifier, and the branch target logical address is extracted by referring to the branch block 5c (address 4 in FIG. 42) (ST007). .

(3) The branch destination logical address is converted into a physical address by referring to the information (address 5 in FIG. 42) in the page management table 5b (ST008). (4) The program execution unit 7 executes the branch destination instruction using the converted physical address (a in FIG. 42) (ST
009).

Prior art 2. A case where tracing is performed and the trace information is collected when the control program is executed will be described. In FIG. 37, the program execution section 7 has a trace function for executing the control program shown in FIG. 43.

In FIG. 43, 400 is a trace memory for storing trace information, which stores the trace data collected by the trace data collecting unit 401.

The trace data collection unit 401
Trace data is collected while recording the trace history in the trace history register of a. Reference numeral 402 denotes a control program address for executing the control program, which stores the address of the executed control program. A program counter is used for this control address.

Reference numeral 403 is an address coincidence detection unit,
Monitor the control program address of 2. Reference numeral 403a is an address match start register, and 403b is an address match end register. A trace request signal 404 is output when it is detected that the control program address 402 exists between the address match start register 403a and the address match end register 403b.

FIG. 44 shows the trace history register 40.
1a is a structural diagram, and trace completion information (information of "1" in this case) is sequentially stored in a bit position corresponding to a relative number from an address match start address.

The operation of the conventional computer system shown in FIG. 37 for collecting trace data will be described below with reference to the flow chart shown in FIG. (1) The address match detection unit 403 monitors the control program address 402 and traces the trace start address 403a.
And trace end address 403b, the trace request signal 4
04 is output. (ST400)

(2) When the trace request signal 404 is output, the trace data collection unit 401 detects this (S
(T401), (3) It is determined whether or not the trace data has been collected from the trace history register 401a (ST402).

(4) If the trace data has been collected, the trace collection processing for that time is ended. If the trace data has not been collected, the trace data such as the execution result of the control program and access data is stored in the control program in the trace memory 400. The data is stored in the position corresponding to the address 402 (ST403). (5) After the trace data collection is completed, the trace completion information is stored in the trace history register 401a at a position corresponding to the control program address 402 (ST40).
4). (6) This series of operations is performed until it is determined whether the detected address is the trace end address and the trace data collection of the trace end address set in the address match end register 403b is completed (ST405).

Prior art 3. The operation of the control program rewriting process of the conventional computer system will be described with reference to the flowchart of FIG. Note that the configuration is the same as in FIG. (1) When a new control program is output from the maintenance tool 1, the request processing unit 6 detects this (ST500),

(2) Notifying the program execution section 7 of the detection, the receiving section 6a receives the new control program (ST501). (3) The receiving unit 6a determines whether or not the control program relating to the change is being executed (ST502),

(4) If execution is stopped, the program rewriting processing unit 6c is instructed to rewrite the control program 5a (ST503). (5) Upon receiving the instruction, the program rewrite processing unit 6c updates the new control program and management information (ST5).
04).

(6) If necessary, the changed program is made executable (ST505). (7) If the control program is being executed, such as temporarily transferring to another process during execution, wait until the execution is completed (ST5
06), after the control program is stopped, the control program 5a is rewritten.

Prior art 4. The interrupt processing of the computer system will be described. FIG. 47 shows, for example, JP-A-7-141.
It is a block diagram which shows the conventional computer system shown by the No. 228 publication.

In the figure, 3 is an input / output interface (IO interface) connected to the plant system 4. Reference numeral 605 is an interrupt detection unit that detects an interrupt from the plant system 4, and 602 is an interrupt detection unit 605.
An interrupt number, which sets an interrupt number when a normal is detected, 603
Is an error number that sets an error number when an error is detected, 6
Reference numeral 01 is an interrupt notification unit for notifying the processor 10 of an IO interrupt or an error.

Reference numeral 604 is plant data input / output between the plant system 4 to be controlled and the processor 10. An IO interrupt / error reception 600 receives an interrupt notification from the IO interface 3, and instructs the program execution unit 7 to start the control program 5a corresponding to the interrupt or error.

The operation of IO interrupt notification in the conventional computer system will be described. 48 and 49 are flowcharts of the interrupt notification process of the conventional IO interface 3 and the interrupt reception process of the processor 10, which will be described below.

(1) The interrupt detection unit 605 detects an interrupt from the plant system 4 (ST700). (2) If the interrupt is normally detected (ST701), (3) Set the interrupt number 602 (ST702),

(4) The interrupt notification unit 601 is the processor 10
Is notified of the IO interrupt (ST703). (5) On the other hand, if the interrupt detection is not normal, an error number 603 is set (ST704), and (6) the interrupt notification unit 601 notifies the processor 10 of an IO error (ST705).

(7) In the processor 10, the IO interrupt / error reception 600 receives the notification from the IO interface 3 (ST710). (8) If it is an IO interrupt notification (ST711), (9) the interrupt number 602 is read (ST71
2),

(10) The control program 5a having the read interrupt number is started (ST713). (11) On the other hand, if it is not an IO interrupt notification (ST711),
The error number 603 is read (ST714), and (12) the control program 5a having the read error number is activated (ST715).

Prior art 5. FIG. 50 shows a failure processing control unit of a conventional failure monitoring processor disclosed in, for example, Japanese Patent Laid-Open No. 5-12236. In the figure, 2 is a system bus that connects the processors, 11 is a failure monitoring processor that monitors the failure of the entire computer system, outputs failure processing to the outside, and leaves an error history.
0-N is a processor whose main function is arithmetic.

Reference numeral 20 denotes a configuration table section having card configuration information connected to the current system bus, the details of which are shown in FIG. Reference numeral 21 denotes a failure processing setting table portion for the cards connected to the current system bus, which is mapped in the rewritable nonvolatile memory, and defines a processing method when a failure occurs in each card.

Reference numeral 22 is failure information notified from the processors 10-1 to 10-N via the system bus 2. Reference numeral 23 is 22.
A failure output unit that outputs a failure state to the outside based on the failure information of 24, a reference numeral 24 generates a configuration table unit 20, a failure processing setting table unit 21, receives failure information 22, and controls a failure output unit 23. It is a failure monitoring unit.

FIG. 51 shows a conventional fault processing setting table section 2
1 is the internal structure. In the figure, 30-1 is the number of cards connected to the system bus 2, 31-1 to 31-N are slot numbers in which the processors 10-1 to 10-N are inserted,

32-1 to 32-N are card type codes 33-1 to 33 for discriminating the type of the card inserted in the slot indicated by the slot numbers 31-1 to 31-N.
-N is configured by the contents of the failure processing of the card, and is compressed into a table of only the number of cards inserted in the slot.

FIG. 52 shows the internal structure of the conventional configuration table section 20. In the figure, 30-1b is the system bus 2
32-0b to 32-Nb, which are the number of cards connected to, are configured by a card type code that determines the type of card corresponding to slots 0 to N, and the card type code includes data (other than 0, for example, "1"). ) Is entered, the slot number is valid.

Next, the operation will be described. When a card of a certain processor has a defect such as a parity error and the defective card is removed and restarted, the initialization process of the failure monitoring unit 24 is performed with the current system configuration and the system configuration before the restart. Check for changes.

In order to perform this check, the configuration table unit 20 is compared with the card configuration of the failure processing setting table unit 21 used until the last time. If the card is being removed at the time of comparison, the current configuration table unit 20
Since the information of the failure processing setting table section 21 is different from that of the failure processing setting table section 21, the failure monitoring section 24 determines that the system has been reconstructed and cannot determine which setting content should be used for operation.

In this case, the setting contents that were set last time are ignored, and the standard failure processing setting that is newly prepared in advance, for example, if the processor status is a major failure, the computer system status is also a major failure, is set. The failure information setting table unit 21 was overwritten with data information to operate.

A comparison between the configuration table unit 20 and the failure processing setting table unit 21 is made by comparing the total number of cards 30-1 in the failure processing setting table unit and the slot numbers 31-1 to 31-N of the inserted cards. It is determined whether the card type codes 32-1 to 32-N for the respective card number numbers are consistent with the information in the configuration table section. The conventional comparison method will be described below with reference to the flowchart of FIG.

(1) In order to check whether the card configuration of the current system is the same as that of the system before restarting, the total number of cards 30-1 in the configuration table section 20-1
b is read (ST700), (2) It is compared whether or not the current number of system configuration cards is equal to the total number of cards 30-1 in the failure processing setting table section 21 indicating the number of system configuration cards before startup ( ST701).

(3) If they do not match (ST702), (4) there is a change in the system configuration, so standard settings prepared in advance are written in the failure processing setting table section 21 (ST707).

(5) If the number of system configuration cards is the same (ST702), (6) the slot number of the valid card in the configuration table section 20 is checked in order to check the valid slot number currently inserted. The slot number 31-1 of the failure processing setting table 21 is compared to see if it matches (ST703).

(7) If they do not match (ST704), (8) the standard value is written in the failure processing setting table section 21 (ST707).

(9) If they match (ST704), (10) In order to check the type of the card currently inserted in the slot, the card type code 31-2b of the configuration table section 20 was previously changed to that slot. Is compared with the card type code 32-1 of the failure processing setting table section 21 indicating the type of the card inserted in the card (ST
705).

(11) If they do not match (ST706), (12) the standard value prepared in advance is written in the failure processing setting table section 21 (ST707).

(13) If they match (ST706), (14) The setting contents 33-1 of the failure processing setting table section 21 are not rewritten because the card configuration does not change for that slot number. (15) The above process is repeated for the current number of cards of 30-1b (ST708).

If there is no change in the current system configuration and the system configuration before restarting, the failure processing setting table section 2
The value of 1 is used as it is without rewriting 1, and it is used as a condition for controlling the failure output to the outside such as a serious / light failure of the computer system.

[0054]

(1) Since the conventional computer system is configured as described above, it requires a memory capacity for a branch block for executing a branch instruction, which causes an increase in cost. At the same time, since memory management is required, the processing is complicated, and
It is necessary to refer to the branch block, convert to the branch destination physical address, and branch to the branch destination physical address every time a branch instruction is executed during execution of the control program, which causes a problem that the execution performance of the control program is degraded. It was

The present invention eliminates the need for a branch block memory relating to a branch instruction, reducing the cost and
The purpose is to improve the execution performance of the control program.

(2) When the maintenance tool is disconnected from the processor during the maintenance processing, the processor performs the timeout processing after a lapse of a certain time, but during the timeout time, the processor is in a high load state and has few resources. There was a problem of becoming.

The present invention has been made in order to solve the above problems, and the processor recognizes disconnection of a maintenance tool at the time of returning a response to the maintenance tool, and terminates other maintenance requests. With the goal.

(3) In addition, when a control program that repeats execution is described between the trace start address and the trace end address when tracing the program, the trace data is repeated after the second execution. The trace request signal is output even though it has been collected.

Since the trace data collection unit determines whether or not to collect the trace data based on the contents of the trace history register, the trace data will not be collected after the second execution. As the number of times increases, there is a problem that the determination process of whether or not to collect the trace data becomes a wasteful process and becomes an overhead of execution of the control program, resulting in a decrease in execution efficiency.

The present invention has been made in order to solve the above problems, and eliminates wasteful determination processing in the repeated portion of the control program in advance, reduces the overhead of the control program execution by the trace processing, The purpose is to obtain a computer that does not reduce the execution efficiency.

(4) Also, in the conventional computer system, when a control program is being executed and a request is made to rewrite the control program with a new one, it is necessary to wait until the control program is completed and stopped. Therefore, there is a problem that the control program cannot be rewritten within a certain time.

The present invention has been made to solve the above problems, and when a control program rewriting request is issued to a control program being executed,
An object of the present invention is to obtain a computer that starts time monitoring and forcibly stops the control program being executed when a time-out occurs to complete the requested rewriting.

(5) Also, a plurality of processors (computers)
When configured with, the error at the time of interrupt or interrupt detection is notified to all the processors, but if the notification is given to the processor that does not have the control program to be executed in response to the notification, the processor overhead will be increased. However, there is a problem in that the processing capacity of the processor increases and the processing capacity of the processor decreases.

The present invention has been made in order to solve the above problems, and notifies an error from the plant of an interrupt and an error at the time of detecting an interrupt only to the processors associated with the interrupt. It is an object of the present invention to obtain a computer system that does not affect the processing capacity of a processor without a processor.

(6) Further, in order to solve the above-mentioned problem (5), the present invention notifies an error from the plant and an error notification at the time of detecting an interrupt when the associated processors are in a failure state. If so, the purpose is to notify another processor and obtain a computer system that does not affect the plant system.

(7) Further, in the conventional computer system having the failure processing setting table section, when the configuration of the card connected to the system bus changes, the setting contents of the failure processing setting table section set up to now are standard. There was a drawback that it was set. For example, when a defect occurs and the faulty part is identified, if the defective card is removed and restarted, the contents of the fault processing setting table will be standardized, and it will differ from the operating environment, so it will be necessary to set it again. The work that must be done occurred. In addition, due to a human error such as forgetting to set the card when replacing the card, the set value returns to the standard value, and there is a drawback that the set value that should be set during operation does not work.

The present invention has been made to solve the above problems. Even if the card configuration is changed, if the previous setting is made, the information is used to improve the maintainability and human error. It is possible to use it in various systems (industrial plant system, various systems such as power plant system) to which the failure processing setting table section is applied without changing the existing H / W configuration of the existing card. To aim.

[0068]

[Means for Solving the Problems]

(1) In a computer according to the present invention, when a program is registered in a memory in advance, the branch destination of a branch instruction in the program is a branch logical address indicated by the number of instruction steps from the beginning of the program, and this branch logical address Is registered as an operand of a branch instruction, and when executing the branch instruction, means for converting the branch destination logical address of the branch instruction operand into a branch destination physical address and executing the branch instruction. is there.

(2) When the program is registered in the memory in advance, the branch destination of the branch instruction in the program is set to the branch physical address indicated by the offset address from the head of the memory, and the branch physical address of the branch instruction is set. It is provided with means for registering as an operand and means for executing the branch instruction based on the branch destination physical address of the operand of the branch instruction when executing the branch instruction.

(3) In a computer that executes maintenance in response to a maintenance request from a plurality of maintenance tools, an error detecting means for detecting an abnormal state of the maintenance tool and an error detected by the error detecting means
And a canceling means for canceling the maintenance process corresponding to the maintenance request from the maintenance tool in which the error is detected.

(4) Further, in the computer that stores the trace data in the trace memory while monitoring the trace data collection range from the trace data collection start address to the trace data collection end address during the execution of the program, one address correspondence When the data of is collected, a means for updating the trace data collection start address to the address of the next program that collected the trace data is provided,
The trace data is stored in the trace memory while monitoring the trace data collection range from the updated trace data collection start address to the trace data collection end address.

(5) Further, when a rewriting request is made to the program being executed, and if the program is being executed even after a predetermined time has passed, a means for stopping the execution of the program and rewriting the program is provided. Be prepared.

(6) In the computer system of the present invention, the controlled object is controlled by a plurality of computers via the input / output interface, and the input / output interface notifies each computer as an interrupt signal from the controlled object as an input. In the computer system described above, the input / output interface includes means for setting a computer to be executed in advance according to the content of the interrupt signal and notifying only the computer that executes the input interrupt signal. .

(7) Further, in the computer system in which the control target is controlled by a plurality of computers via the input / output interface, and the input / output interface notifies each computer as an input of an interrupt signal from the control target, The input / output interface sets a computer to be executed in advance according to the contents of the interrupt signal, and means for notifying only the computer that executes the input interrupt signal, and the input interrupt signal is normal. Otherwise, it is provided with a means for notifying a preset computer of error information.

(8) Further, in the above (6) or (7), the input / output interface is set with a failure detecting means for detecting a failure of the computer and a computer to be changed when the computer fails in advance. Every time, a computer changing means for switching to the computer to be changed is provided, and when the failure of the interrupt notification destination or the error information notification destination is detected by the failure detecting means, the computer is changed by the computer changing means. It is a thing.

(9) Further, in a computer system in which each computer is arranged on a card and the computers are connected to each other, the setting contents of each computer corresponding to the type of each card and its mounting position. Backup means and a first setting means for setting a card of the type corresponding to the mounting position at the mounting position when the card is mounted, and the first setting means for setting the setting contents held by the backup means, and the card. When installing, if you attach a card of a type that does not correspond to the mounting position to that mounting position,
Second setting means for setting using a standard value set in advance is provided.

[0077]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the program rewriting of the computer system of the present invention, and the explanation of the same reference numerals as those of the conventional one will be omitted.

2 and 3 are flowcharts, FIG. 4 is an instruction operand configuration diagram, FIG. 5 is a diagram exemplifying address conversion processing at the time of execution of the control program, and FIG. 6 is an explanation at the time of execution of branch processing of the control program. It is a figure.

FIG. 5 will be described. Program 1,
Each of 2, 3, ... Is composed of a plurality of blocks, and is divided into 4 blocks in the program 1, and each block has a fixed length of 128 steps, for example. The target table of the physical address corresponding to the start address of each block is registered in the page management table 5b. With this content, in the program 1, 0 of the control program,
The program having the physical addresses 3, 5, 6 as the start addresses is executed. When executing the program, the branch address does not require the conventional branch block 5c shown in FIGS. 37 and 42. However, a branch block is required when rewriting the program.

The execution of branch processing will be described with reference to FIG.
As can be seen from a comparison with the conventional FIG. 42, at the time of program execution, the branch block is eliminated, and the number of steps from the beginning of the program is directly described in the operand of FIG. Management table 5b
Referring to, the address obtained by adding the number of steps of the operand to "address 5" which is the start address of the program 5 represents the branch destination physical address (a), and the control program 5a
The a-th address of is the branch destination, and the program at that position is executed.

Next, the operation will be described with reference to the flow charts of FIGS. FIG. 2 shows an operation flow of a program rewriting process including a branch instruction. (1) The program rewriting processing request sent from the maintenance tool 1 is received by the receiving unit 6a of the request processing unit 6 and sent to the program rewriting processing unit 6c (ST100).

(2) The program rewrite processing section 6c
The control program is written in the control program 5a area of the memory unit 5 (ST101), and (3) the write position in the control program 5a is expressed by a physical address that is an offset address from the beginning of the memory unit 5, and the specified program It is registered in the page management table 5b in association with the number (ST102).

(4) When the program writing is completed, the program rewriting processing unit 6c extracts the branch destination of the branch instruction from the program for which the program rewriting processing is requested, and uses the branch block number held in the operand as an identifier. The branch block information is used to refer to the branch destination logical address, which is the number of instruction steps from the beginning of the program (ST103).

(5) Since the acquired branch destination logical address needs to be known as a branch destination when executing a branch instruction, it is registered as an operand of the branch instruction as shown in FIG. 4 (ST104).

(6) The steps ST103 to ST104 are performed for all branch instructions in the program (ST105).

FIG. 3 shows an operation flow of branch instruction processing when executing a branch instruction. (1) The program execution unit 7 extracts an instruction from the control program 5a of the memory unit 5 (ST106). (2) If it is a branch instruction (ST107), in FIG. 6, "branch 3" of the program 5. (3) Referring to the page management table 5b, the physical offset address (address 5 in FIG. 6) from the beginning of the memory 5 corresponding to the program number and the branch destination stored in the branch instruction operand shown in FIG. Logical address (Fig. 6
And the logical address of branch 3) are obtained to obtain the branch destination physical address (ST108).

(4) The program execution section 7 branches to the calculated branch destination physical address and executes it (ST109). (5) If the instruction extracted in ST106 is not a branch instruction (ST107), (6) execute according to each instruction (ST
110). (7) When the execution of all the instructions in the program is completed (ST111), the program execution is ended.

As described above, when the instruction is executed, the logical address of the branch destination can be converted into the physical address and the control program can be transferred to the specified physical address without referring to the branch block. After that, there is no need to retain branch block information,
By deleting the branch block, the backup memory size required at the time of instruction execution can be significantly reduced, so that the cost of the computer is reduced and the execution performance of the control program is improved. Therefore, the performance of computer processing can be improved.

The backup memory is usually a memory that is backed up by another power source even when the power is turned off, but it can also be applied to a memory that the power source does not back up.
Further, the memory can be reduced by, for example, about 25%.

Embodiment 2. In FIG. 7, the page management table 5b is referred to when the program is executed, and the process of converting the branch destination logical address into the branch destination physical address is performed. In contrast to FIG. 1, the branch destination logical address is converted into the branch destination physical address when rewriting the program. When the branch instruction is executed, the branch processing is performed based on the branch destination physical address directly described in the program without referring to the page management table.

In FIG. 7, description of the same reference numerals as those of the conventional one will be omitted. 8 and 9 are flowcharts, and FIG.
0 is an instruction operand configuration diagram. FIG. 11 is an explanatory diagram when the branch process is executed.

Next, the operation will be described with reference to the flow charts of FIGS. FIG. 8 shows an operation flow of a program rewriting process including a branch instruction. (1) The program rewriting processing request sent from the maintenance tool 1 is received by the receiving unit 6a of the request processing unit 6 and sent to the program rewriting processing unit 6c (ST200).

(2) The program rewrite processing unit 6c
The control program is written in the control program 5a area of the memory unit 5 (ST201), and (3) the writing position in the control program 5a is expressed by a physical address that is an offset address from the beginning of the memory unit 5, and the designated program is specified. The page management table 5b is registered in association with the number (ST202).

(4) When the program writing is completed, the program rewriting processing unit 6c extracts the branch destination of the branch instruction from the program for which the program rewriting processing is requested, and uses the branch block number held in the operand as an identifier. The branch block information is used to obtain the branch destination logical address, which is the number of instruction steps from the beginning of the program (ST203).

(5) When the branch destination logical address is acquired,
The program rewriting unit 6c uses the page management table 5
Referring to b, the branch destination logical address is added to the physical offset address from the beginning of the memory 5 corresponding to the program number to obtain the branch destination physical address (ST20).
4).

(6) The branch destination physical address is written in the branch instruction operand as shown in FIG. 10 (ST20
5). (7) The steps ST203 to ST205 are performed for all branch instructions in the program (ST206).

FIG. 9 shows an operation flow of branch instruction processing when executing a branch instruction. (1) The program execution unit 7 extracts an instruction from the control program 5a (explained with the program 5 in FIG. 11) of the memory unit 5 (ST207),

(2) If it is a branch instruction (ST208),
For example, in the case of “branch 3” in FIG. 11, (3) branch is executed to the branch destination physical address stored in the branch instruction operand shown in FIG. 10 (ST209).

(4) If the extracted instruction is not the branch instruction, the instruction is executed according to each instruction (ST211). (5) When the execution of all the instructions in the program is completed (ST210), the program execution is ended.

As described above, when the instruction is executed, the control program control can be transferred to the specified physical address without referring to the branch block and the page management table. It is no longer necessary to maintain the management table, and by deleting branch blocks and page management tables, the backup memory size required for instruction execution can be significantly reduced, reducing computer cost and improving control program execution performance. .

Furthermore, since the process of converting a logical address to a physical address when an instruction is executed is deleted, there is an effect that the instruction execution speed is improved. Therefore, the processing performance of the computer is improved.

Embodiment 3 FIG. In this embodiment, maintenance processing is performed efficiently. FIG. 12 is a configuration diagram thereof, 6d is a maintenance processing unit for processing the request received by the receiving unit 6a, 6f is a cancellation processing unit for canceling the maintenance process, and 5d is a processing buffer used in the maintenance request process. 13, 14, and 15
Is a flowchart of the processing operation.

Here, the maintenance includes various things such as program change / correction, control information change, trace start, and trace data read. Cancellation is also one of maintenance, but here, cancellation will be explained separately from maintenance. In addition, the maintenance request from a maintenance tool such as a PC is often the maintenance request itself which is the change / correction content of the program, but according to the maintenance request (command) from the maintenance tool, the prescribed maintenance is performed on the computer side. It may be processed.

Next, the operation will be described. FIG. 13 is a flowchart showing the operation flow of request reception processing in the computer of the third embodiment. (1) When the receiving unit 6a receives the maintenance process request from the maintenance tool 1, it is determined whether the request is a cancel request (ST300).

(2) If the judgment result is not a cancel request,
If it is a maintenance processing request, the receiving unit 6a sends the received data to the maintenance processing unit 6d (ST301), and (3) the maintenance processing unit 6d registers the received data in the processing buffer 5d (ST302). (4) If the determination result is a cancel request, the received data is sent to the cancel processing unit 6f (ST303).

(5) As in the flowchart of FIG. 15, the cancel processing unit 6f determines whether the maintenance processing being executed in the processing buffer 5d is a command from the maintenance tool 1 (ST304), (6) If the command is from the maintenance tool 1, the processing buffer 5d in which the maintenance processing of the maintenance tool 1 is registered is deleted (ST305).

FIG. 14 is a flow chart showing the flow of transmission processing. (1) Waiting state for receiving response for maintenance processing (ST30
In 6), if there is no maintenance processing response from the maintenance processing unit 6d, the reception waiting is continued. (2) When a response is received from the maintenance processing unit 6d, the response is sent to the maintenance tool 1 (ST307).

(3) When an error of disconnection of the maintenance tool 1 such as a timeout is detected in the response process (ST30
8), (4) The response is retried again, and when the number of retries specified is exceeded, the response is aborted as a retry over (ST309) (ST310).

(5) At this time, a cancel request command is generated to end another request from the same maintenance tool 1, and the request is sent to the receiving section 6a (ST311). (6) Receiving the cancel request, the receiving unit 6a performs the cancel processing of the command processing received from the maintenance tool in the flowchart of FIG.

As described above, when the maintenance tool is disconnected, an error is detected when the maintenance tool responds to the maintenance request. Therefore, one or more maintenance tools from which the error was detected are detected. Since all the maintenance processing corresponding to the maintenance request of will be canceled, the maintenance processing from other maintenance tools that have already been accepted will not be canceled, and the maintenance of only the disconnected maintenance tool will be canceled. The maintenance process request from the maintenance tool can be accepted, and the maintenance process can be performed efficiently. Therefore, the performance of computer processing can be improved.

Fourth Embodiment In this embodiment, the efficiency of the trace processing of the control program is improved. 16 is a block diagram showing a fourth embodiment of the computer system according to the present invention. In the figure, 400 is a trace memory, 401 is a trace data collection unit, 402 is a control program address, and the address of the executed control program is stored. A program counter is used for this control address.

Reference numeral 403 is an address coincidence detector, and 404 is a trace request signal. An address rewriting unit 405 uses the next control program address as a new address match start address, and the address match start register 40
3a.

Next, the operation will be described with reference to the flowchart of FIG. (1) The address match detection unit 403 detects an address match between the control program address (program counter) 402 and the address match start register 403a, and outputs a trace request signal 404 to the trace data collection unit 401 (ST410).

(2) The trace data collecting unit 401 detects the trace request signal 404 (ST411), and (3) it is determined whether the address where the address match is detected is the trace data uncollected or not.
It is judged by a (ST412).

(4) If the trace data has not been collected, the trace data is collected (ST413). (5) After the trace data collection is completed, the trace completion information is stored in the trace history register 401a at a position corresponding to the control program address 402 (ST41).
4).

(6) The address rewriting unit 405 uses the address obtained by adding 1 to the control program address 402 as a new trace start address, and the address matching detection unit 4
The address match start register 403 of No. 03 is set (ST415).

(7) It is judged whether or not the address detected after the trace collection is the trace end address, and the process is executed until the data collection of the trace end address is completed (ST
416).

Conventional address match start register 403a
44, all the addresses to be traced are registered, but in this embodiment, the start address of the trace end of the address match start register 403a of FIG. 44 is rewritten to the start address to be traced next. Therefore, it is not necessary to determine the necessity of tracing up to the address at the end of tracing.

As described above, by excluding the control program for which the trace data has been once collected from the trace target range, an address match is not detected at the control program address for which the trace data has been collected, so that it is not necessary to perform unnecessary judgment processing. The overhead of trace data collection in the repeated execution part such as loop control is reduced, and the load on the computer system is reduced. Therefore, the performance of computer processing can be improved.

Embodiment 5. In this embodiment, the control program is efficiently rewritten. FIG.
FIG. 13 is a configuration diagram of a computer system showing a fifth embodiment of the present invention. In the figure, the same reference numerals as those of the conventional one indicate the same or corresponding portions, and the description thereof will be omitted.

Reference numeral 6e is a time monitoring unit for time-monitoring the completion of execution of the control program, which is the time until the execution is completed for the module which is being executed, for example, the temporary processing is being transferred to perform other processing. Monitor. When the time monitoring unit 6e outputs a time-out for execution completion, the program forced stop unit 6g stops the timed-out program by a forced error.

Next, the operation will be described with reference to the flowchart of FIG. (2) When a new control program is output from the maintenance tool 1, the request processing unit 6 detects this (ST510), and (3) the program execution unit 7 is informed of the detection and the receiving unit 6a receives the new control program. The control program is received (ST511).

(4) The receiving unit 6a determines whether or not the control program related to the update is being executed (ST512). (5) If the execution is stopped, the program rewriting processing unit 6c is instructed to rewrite the control program. (ST513).

(6) The program rewrite processing unit 6c
Upon receiving the instruction, the control program is updated to a new control program (ST5
14). (7) If the control program is being executed, the time monitoring unit 6
e is instructed to monitor the time of, for example, three times the execution cycle, and the completion of execution of the control program related to the change is monitored (ST516).

(8) When the execution is not completed even after the elapse of a certain time, the program forced stop unit 6g instructs the program execution unit 7 to stop the forced error and stops the program (ST517). After the control program is stopped, the control program 5a is rewritten.

As described above, when a rewriting request is made to the control program being executed, the time until the program execution is completed is monitored, and when it is not completed within a certain time,
Since the program is rewritten after the forced error stop and the program rewritable state are set, the control program is rewritten within a fixed time without waiting for a long time, and the maintainability is improved. Therefore, the performance of computer processing can be improved.

Embodiment 6 FIG. Embodiments of the present invention efficiently perform interrupt processing in a computer system composed of a plurality of computers. FIG. 20 is a block diagram showing the configuration of the computer system showing the sixth embodiment of the present invention. In the figure, a detailed description of the same or corresponding parts as those of the conventional device denoted by the same reference numerals in FIG.

In FIG. 20, 10-1 to 10-N are processors (computers). These processors 10-
1 to 10-N are connected by a system bus 2. In addition, each processor 10-
Each of 1 to 10-N is connected to the IO interface 3. A plant system 4 is connected by the IO interface 3. Here, each processor 10-1 to 10-N and the IO interface

The case 3 is realized as a card to be inserted into the slot. Each processor 10-2 to 10-
N also has the same configuration as the processor 10-1, and also has the same configuration as the conventional processor 10 of FIG. Reference numeral 606 is interrupt-corresponding information that holds information relating to the notified processor for each interrupt from the plant system 4. The detailed data structure is shown in FIG.

In the example of the interrupt correspondence information of FIG. 21, when the value of the interrupt number is 0, the processor 10-1 is notified, and when the value of the interrupt number is 1, neither processor is notified.
This is information indicating that the processor 10-N is notified when the value of the interrupt number is 2.

Next, the operation will be described. FIG. 22 and FIG.
3 is a flowchart of the interrupt notification process of the IO interface 3 and the interrupt reception process of the processors 10-1 to 10-N, which will be described with reference to the flows of FIGS. 22 and 23. (1) The interrupt detection unit 605 detects an interrupt from the plant system 4 (ST600).

(2) If the interrupt is normally detected (ST60
1), go to step ST602. Whether or not the interrupt is normal is checked, for example, by checking the range of the interrupt numbers, and if the range is within the range, it is determined to be normal, and if it is out of the range, it is determined to be abnormal. (3) The interrupt notification unit 601 sends the interrupt corresponding information 60 to, for example, the processor corresponding to the interrupt number of the interrupt corresponding information 606.
If the interrupt number of 6 is the processor 10-1, the interrupt number is notified to the processor (ST602).

(4) On the other hand, if the interrupt detection is not a normal detection, an error number 603 is set (ST604), and (5) the interrupt notification unit 601 is set to, for example, the processor 10-
1 is notified of an IO error (ST605).

(6) In FIG. 23, in the processor 10, I
The O interrupt / error reception 600 receives the notification from the IO interface 3 (ST610). (7) If the notification is an IO interrupt notification (ST611), (8) the control program 5a having the notified interrupt number is activated (ST612).

(9) On the other hand, if it is not an IO interrupt notification (ST
611), (10) The error number 603 is read (ST61
4), (11) The control program 5a having the read error number is activated and the process corresponding to the error is executed (ST61).
5).

As described above, when the IO interface of the computer system detects an interrupt, only the processor designated in the interrupt corresponding information is notified of the interrupt, and the processor not designated is not notified of the interrupt. Therefore, the overhead of the processor that does not require the notification of the interrupt is reduced, and the throughput of the computer system is improved. Therefore, it is possible to prevent performance degradation of the computer system.

Seventh Embodiment The embodiment of the present invention efficiently performs the same interrupt processing as that of the sixth embodiment in a computer system composed of a plurality of computers.
24 is a block diagram showing the configuration of a computer system showing Embodiment 7 of the present invention.

In FIG. 24, reference numeral 608 is a multi-interrupt correspondence information which holds information relating to the notification destination processor for each interrupt from the plant system 4, the details of which are shown in FIG. The detailed description of the same symbols as those in FIG. 20 of the sixth embodiment will be omitted.

FIG. 25 exemplifies the data structure of the interrupt correspondence information. When the value of the interrupt number is 0, the processor 1
0-1 and the processor 10-5, when the value of the interrupt number is 1, neither processor is notified, and the value of the interrupt number is 2
At the time of, it is information indicating that the processor 10-2, the processor 10-3, and the processor 10-N are notified.

Next, the operation will be described. FIG. 26 shows I
7 is a flowchart of an interrupt notification process of the O interface 3. The flowchart of the interrupt reception processing of the processors 10-1 to 10-N is the same as that of FIG.

Description will be given according to the flow of FIG. (1) The interrupt detection unit 605 detects an interrupt from the plant system 4 (ST620). (2) If the interrupt is normally detected (ST621),

(3) The interrupt notification unit 601 notifies the interrupt number to one or a plurality of processors corresponding to the interrupt number of the multiple interrupt correspondence information 608 (ST622). (4) On the other hand, if the interrupt detection is not normal, an error number 603 is set (ST624), and (5) the interrupt notification unit 601 notifies the processor of an IO error (ST625). The subsequent processing is the same as in FIG.

As described above, when the IO interface of the computer system detects an interrupt, it notifies the interrupt to one or more processors specified in the interrupt correspondence information, and interrupts the unspecified processors. Is not notified,
It is possible to prevent performance degradation of the computer system. Also,
There is an effect that optimal load distribution to each processor becomes possible by appropriate setting. Therefore, the performance of computer processing can be improved.

Embodiment 8 FIG. Embodiments of the present invention efficiently perform interrupt processing in a computer system composed of a plurality of computers. FIG. 27 is a block diagram showing the configuration of the computer system showing the eighth embodiment of the present invention. In the figure, those denoted by the same reference numerals as those in the conventional FIG. 47 are the same parts, and therefore detailed description thereof will be omitted.

In the figure, 10-1 to 10-N are processors. These processors 10-1 to 10-N are connected by a system bus 2. Further, each processor 10-1 to 10-N is connected to the IO interface 3 by the system bus 2. And I
The O interface 3 is connected to the plant system 4.

Here, each of the processors 10-1 to 10-1
The case where the 0-N and the IO interface 3 are realized as a card inserted into the slot is taken as an example. Each of the processors 10-2 to 10-N has the same configuration as the processor 10-1, and also has the same configuration as the conventional processor 10 of FIG.

Reference numeral 607 is error correspondence information which holds information relating to the notified processor for each error number.

Further, FIG. 28 exemplifies the data structure of the error correspondence information of the eighth embodiment, for example, and when the value of the error number is 0, the error numbers of the error numbers are sent to the processors 10-1 and 10-5. When the value is 1, no processor is notified, and when the error number is 2, the processors 10-2, 10-3 and 1
This is information indicating that 0-N is notified.

Next, the operation will be described. 29 and 3
0 is a flowchart of the interrupt notification process of the IO interface 3 and the interrupt reception process of the processors 10-1 to 10-N. Description will be given according to the flows of FIGS. 29 and 30.

(1) The interrupt detection unit 605 detects an interrupt from the plant system 4 (ST630). (2) If the interrupt is normally detected (ST631), the interrupt notification unit 601 displays the interrupt correspondence information 606 shown in FIG. 28, for example.
The interrupt number (processor shown in FIG. 21 or FIG. 25) is notified to one or more processors corresponding to the interrupt number (ST632).

(3) On the other hand, if the interrupt detection is not normal, the interrupt notification unit 601 notifies the error number to one or more processors corresponding to the error number of the error correspondence information 607 (ST634). (4) In the processor 10, IO interrupt / error reception 60
0 receives the notification from the IO interface 3 (ST
640).

(5) If it is an IO interrupt notification (ST64
1), (6) Start the control program 5a having the notified interrupt number (ST642). (7) On the other hand, if it is not an IO interrupt notification (ST641), (8) The control program 5a having the notified error number is activated and the process corresponding to the error is executed (ST64).
4).

As described above, the IO interface of the computer system does not notify the interrupt when an error is detected in the interrupt detection operation, but instead of sending it to one or more processors specified by the error correspondence information for each error factor. Since the error is notified and the error is not notified to the unspecified processor, it is possible to prevent performance deterioration of the computer system.

Further, it is possible to notify each error in the interrupt detection processing from the plant to a single processor, to each processor for each factor, or to notify all the processors. Therefore, it is possible to build a variety of systems, such as a system that does not affect the error to other processors by notifying a single processor, or a system that notifies all processors of the same abnormal processing. The effect is that it will be possible. Therefore, the performance of computer processing can be improved.

Embodiment 9 FIG. The embodiment of the present invention is to back up a failure in a computer system composed of a plurality of computers. FIG. 31 is a block diagram showing the configuration of the computer system showing the embodiment of the present invention.

In the figure, reference numeral 653 is a failure detection section for detecting an error occurring in the processor and notifying this error information to other processors and the IO interface 3, and 650 is a failure occurrence notification from the processors 10-1 to 10-N. A processor card failure detection unit 651 that receives the interrupt is an interrupt / error correspondence information update unit that changes the interrupt correspondence information 606 and the error correspondence information 607 when a processor failure occurs.

Reference numeral 652 is an interrupt / error correspondence information section 651.
Is a processor change card table used as a reference for changing a failed processor, and details thereof are shown in FIG. FIG.
Is set by, for example, a maintenance tool connected to the IO interface 3.

Next, the operation will be described. FIG. 32 is a flow chart showing the operation when a failure occurs in the processor. (1) If a failure such as a memory parity error occurs in the processor 10-1, the failure detection unit 653 recognizes it (ST670),

(2) Notify that another processor and IO interface 3 have failed (ST671). (3) The processor card failure detection unit 650 of the IO interface 3 recognizes the failure notification from the processor.
(ST672)

(4) Processor failure card detection unit 650
Indicates to the interrupt / error correspondence information updating unit 651 that the interruption correspondence information 6
06 and the error correspondence information 607 are notified that the notification destination processor needs to be changed (ST673). (5) The interrupt / error correspondence information updating unit 651 refers to the processor change card table 652 shown in FIG. 33, for example (ST674),

(6) Obtain a changed processor for the failed processor (ST675). In FIG. 33, as an example,
When the processor 10-1 fails, the processor 10-2,
When the processor 10- (N-1) has a failure, the case where the processor 10-N corresponds is shown.

(7) Interrupt / error correspondence information updating unit 651
Searches for the interrupt correspondence information 606 and the error correspondence information 607 and checks whether or not the failed processor number is included (ST676).

(8) If the processor number is included (ST677), (9) according to the changed processor number corresponding to the processor number, the interrupt correspondence information 606 and the error correspondence information 607.
Change the processor number of the failed processor (ST67
8). (10) If the processor number is not included (ST6
77), the interrupt handling information 606 and the error handling information 607 are left as they are (ST679).

As described above, this computer system has a processor card failure recognition unit for recognizing a failure state of a request destination processor and a notification destination thereof at the time of interrupt detection / error detection even when the request destination processor is in a failure state. Since the request / destination processor is changed by the interrupt / error handling process updating unit that changes the number, the request from the plant system can be processed even when the processor fails. Therefore, the performance of the computer system can be improved.

Embodiment 10. FIG. According to the embodiment of the present invention, in a computer system in which a plurality of computers (processors) are configured for each card, when a card is replaced due to a failure of the computer (processor) or a new card is attached, The contents of the card settings are automatically set.

FIG. 34 is a diagram showing an embodiment of the present invention. This diagram shows the conventional fault monitoring processor 11 of FIG.
A backup data information area 25 is added to the inside. The backup data information area 25 is provided in a rewritable non-volatile memory in the failure monitoring processor 11 and stores the contents of the previously set failure processing setting table section.

FIG. 35 shows detailed information of the backup data information area 25. In the figure, 32-0a to 32
-Na is a card type code 33-0a to 33-N for discriminating the card type corresponding to the number of cards.
Since a is composed of the setting contents of the card and serves as setting information for each slot, the backup data information area has a fixed length regardless of the number of cards inserted in the slot.

Further, the data structure of the configuration table unit 20 is the conventional data structure of FIG. 52, and the data structure of the failure processing setting table unit 21 is the conventional data structure of FIG. FIG. 36 is a flowchart of the operation in the initialization processing of the failure processing setting table unit 21 of the failure monitoring unit 24.

Next, the operation will be described. (1) Fault monitoring processor 1 configured as shown in FIG.
1, in the initialization process of the failure monitoring unit 24, in order to check whether the current system configuration is the same as the system configuration before the restart, the card type codes 32-0b to 32-Nb (from the configuration table unit 20 52) is other than 0, the slot number is regarded as an effective slot number, and the card type code 32-0b-corresponding to the effective slot number.
Read 32-Nb (ST710).

(2) The effective slot number obtained in ST710 and the slot number 3 of the failure processing setting table 21 used until the last time in the system configuration before restarting.
It is compared whether or not 1-1 matches (ST713).

(3) If they match (ST714), (4) In order to check the type of the card inserted in the slot, the card type code 32-1b of the valid slot obtained in ST710 (see FIG. 52) (Shown) is compared with the card type code 32-1 of the failure processing setting table section 21 (shown in FIG. 51) to determine whether the card type is before starting (ST715).

(5) If they match (ST716), it is determined that there is no change in the card configuration, and the previously set setting content 33-1 is used as it is.

(6) On the other hand, the configuration table section 20 of FIG.
53 and the slot number 31-1 of the failure processing setting table unit 21 of FIG. 53 (ST713), (7) When a mismatch occurs (ST714),

(8) In order to operate with the settings before restarting, the setting contents are collected from the backup data information area 25 in which the previously set failure processing setting table portion 21 is saved, but the backup data information area 2
Check whether the contents of 5 satisfy the current system configuration. First, the card type code 32 of the backup data information area 25 of FIG. 35 corresponding to the corresponding slot
-0a is compared with the card type code of the configuration table 20 of FIG. 52 (ST719).

(10) If they match (ST720), (11) Since the setting content 33-0a of the backup data information area 25 of the corresponding slot is the setting that was set last time, that data is stored in the failure processing setting table section. 21
Is written in the setting contents 33-1 of the corresponding card setting information (ST722).

(12) If they do not match (ST720), (13) it is determined that a card type that has not been set in the corresponding slot before is newly inserted, and the standard value of the setting contents prepared in advance is used. The setting contents 33-0a of the backup data information area 25 and the setting contents 33-1 of the failure processing setting table unit 21 are written (ST7).
21).

(14) By repeating the above processing for the number of cards (ST723), the failure processing setting table section becomes effective.

For example, when a parity error occurs in a certain processor and the processor is removed and restarted, the configuration table section 20 is effective for other inserted processors other than the removed processor. Since the card type code 32-1b of the slot number and the card type code of the failure processing setting table unit 21 corresponding to the slot match, the setting contents are processed without change.

When a processor having the same card type as the defective processor is inserted into the slot and restarted, only the setting contents of the newly inserted processor are read from the backup data information area 25 and the setting contents are broken. Write to the applicable area of the processing setting table.

Therefore, the computer system can be operated with the setting contents before the occurrence of the trouble without new manual setting associated with the new card.

On the other hand, the backup data information area 25
When the failure processing setting table is rewritten from a maintenance tool or the like, the set values are written by classifying the set contents at the same time, so the set values are saved at the time of setting. Also, backup data information area 2
If no data is set in 5, the standard value prepared in advance is written in the backup memory data information area and the start-up is performed.

The failure processing processor 11 may have any of the processors 10-1 to 10-N have that function.

As described above, in this computer system, the failure monitoring processor is provided with the backup data information area, and even if the card configuration is changed, the contents of the failure processing setting table section use the previously used setting contents. You can
In addition, the interface compatibility with the existing S / W can be maintained, and it can be realized without changing the H / W.

Therefore, once remove the card from the slot,
Even if it is restarted, there is no change in the failure processing setting table part set for other cards, and if the same card is inserted in the same slot, it can operate with the setting contents previously set for that card, Also, if you insert a card that was not previously set, or if you insert a card to a slot that was not previously set, predetermined setting data such as the standard value is stored in the failure processing setting table section and the setting The data can be used for external output and unit control.

Eleventh Embodiment As a modified example of the tenth embodiment, an example in which the failure processing setting table unit 21 has the function of the backup data information area 25 will be described.

In the tenth embodiment described above, for example, when the contents of the currently set failure processing setting table 21 are changed by using a maintenance tool or the like, and when the card is removed and restarted due to a trouble, a failure occurs. The setting contents of the removed card are deleted from the processing setting table unit 21.

After that, when the card is inserted again into the slot for booting due to repair, replacement, etc., the previously set contents are not in the failure processing setting table section 21, so the previously set contents from the backup area are deleted. I try to get it.

In the eleventh embodiment, a flag is provided in the data of the failure processing setting table section 21, and when the card is removed, a flag of "no card" is set to prevent the setting contents from being deleted. Then, when a card is inserted, the flag is set as “with card” and the inserted card is set according to the setting contents of the failure processing setting table unit 21.

As described above, the eleventh embodiment has the same effects as the tenth embodiment.

[0190]

【The invention's effect】

(1) As described above, according to the computer of the present invention, since a branch destination logical address is designated as a branch instruction as a branch instruction, it can be directly handled as a branch instruction when the instruction is executed. It is possible to delete the branch block that stores the branch destination address,
This has the effect of significantly reducing the backup memory size required when executing instructions. In addition, the execution performance of the program is improved.

(2) As a branch instruction, since the instruction operand points to the physical address of the branch destination, it can be directly handled as a branch instruction when the instruction is executed. Therefore, the address of each branch destination is stored. The branch block to be placed can be deleted, and the backup memory size required for executing instructions can be significantly reduced. Further, since the process of converting the logical address to the physical address is deleted when the instruction is executed, there is an effect that the instruction execution speed is improved.

(3) Further, since one or more maintenance requests being processed by the maintenance tool are canceled due to error detection when the maintenance tool responds to the maintenance request, maintenance processing requests from other maintenance tools are cancelled. Can be accepted.

(4) By configuring the trace start address to the next program address,
Since the address match is no longer detected in the program that once collects the trace data, the overhead of collecting the trace data in the repeatedly executed part such as loop control is reduced, and the load on the computer is reduced.

(5) Further, since the program execution time is monitored, and if the program is not completed within a fixed time, the program is rewritten after the forced error stop is made to make the program rewritable state, so that it is not necessary to wait for a long time. This has the effect of improving the maintainability by rewriting the program within a fixed time.

(6) Further, according to the computer system of the present invention, since the interrupt notification is given only to the computer which needs the interrupt notification, the overhead of the computer which does not need the interrupt notification is reduced, and the system is reduced. Has the effect of improving the throughput. In addition, since it is possible to process a program by notifying one or more computers of one interrupt, it is possible to optimally distribute the load to each computer by appropriately setting the computers to be notified. .

(7) Further, in the IO interface, each error in the interrupt detection processing from the controlled object can be notified to a single computer, or to each computer for each factor, or to all computers. It is also possible to notify.
For this reason, it is possible to build a variety of systems, such as a system that does not affect the error on other computers by notifying a single computer, or a system that notifies all computers of the same abnormal processing. Has the effect of becoming.

(8) Further, in the IO interface, even if the requested computer becomes a failure state, the requested computer is changed, so that there is an effect that the request from the controlled object can be processed even when the computer fails.

(9) Even if the computer card is once removed from the slot and restarted, the setting contents set in other computer cards are not changed, and if the same card is inserted into the same slot, It becomes possible to operate with the setting contents set in the card, and when the card is inserted into the previously set card or the slot not previously set, there is an effect that predetermined setting data can be set.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a computer system according to Embodiment 1 of the present invention.

FIG. 2 is a flowchart showing the operation of a program rewriting unit of the computer system shown in FIG.

FIG. 3 is a flowchart showing an operation of a program execution unit of the computer system shown in FIG.

4 is an operand configuration diagram of the computer system of FIG.

FIG. 5 is a diagram illustrating address conversion processing when a control program is executed according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram when a branch process is executed according to the first embodiment of the present invention.

FIG. 7 is a configuration diagram showing a computer system according to a second embodiment of the present invention.

8 is a flowchart showing an operation of a program rewriting unit of the computer system shown in FIG.

9 is a flowchart showing an operation of a program execution unit of the computer system shown in FIG.

FIG. 10 is a diagram of operand creation of the computer system of FIG. 7.

FIG. 11 is an explanatory diagram when a branch process is executed according to the second embodiment of the present invention.

FIG. 12 is a configuration diagram showing a computer system according to a third embodiment of the present invention.

FIG. 13 is a flowchart showing an operation of a receiving unit of the computer system shown in FIG.

FIG. 14 is a flowchart showing an operation of a transmission unit of the computer system shown in FIG.

15 is an example of a cancel command structure of the computer system of FIG.

FIG. 16 is a configuration diagram showing a computer system according to a fourth embodiment of the present invention.

17 is a flowchart showing the operation of the computer system shown in FIG.

FIG. 18 is a configuration diagram showing a computer system according to a fifth embodiment of the present invention.

19 is a flowchart showing the operation of the program rewrite processing unit of the computer system shown in FIG.

FIG. 20 is a block diagram showing a computer system according to a sixth embodiment of the present invention.

FIG. 21 is interrupt corresponding information according to the sixth embodiment of the present invention.

FIG. 22 is a flowchart showing the flow of an IO interface interrupt notification process according to the sixth embodiment.

FIG. 23 is a flowchart showing the flow of an interrupt reception process of the processor according to the sixth embodiment of the present invention.

FIG. 24 is a block diagram showing a computer system according to a seventh embodiment of the present invention.

FIG. 25 is a diagram of interrupt corresponding information according to the seventh embodiment of the present invention.

FIG. 26 is a flowchart showing the flow of an IO interface interrupt notification process according to the seventh embodiment of the present invention.

FIG. 27 is a block diagram showing a computer system according to an eighth embodiment of the present invention.

FIG. 28 is a diagram of error correspondence information according to the eighth embodiment of the present invention.

FIG. 29 is a flowchart showing the flow of an IO interface interrupt notification process according to the eighth embodiment of the present invention.

FIG. 30 is a flowchart showing the flow of an interrupt reception process of a processor according to the eighth embodiment of the present invention.

FIG. 31 is a block diagram showing a computer system according to a ninth embodiment of the present invention. .

FIG. 32 is a flowchart showing a process according to the ninth embodiment of the present invention.

FIG. 33 is a configuration diagram of a processor change card table according to the ninth embodiment.

FIG. 34 is a configuration diagram of a computer system according to the tenth embodiment of the present invention.

FIG. 35 is a configuration diagram of a backup data area according to the tenth embodiment of the present invention.

FIG. 36 is a flowchart showing a management means of the failure processing setting table according to the tenth embodiment of the present invention.

FIG. 37 is a block diagram of a conventional computer system.

FIG. 38 is a flowchart showing the operation of the rewrite processing unit of the conventional computer system.

FIG. 39 is a flowchart showing the operation of the instruction execution unit of the conventional computer system.

FIG. 40 is a configuration diagram of a page management table of a conventional computer system.

FIG. 41 is an operand configuration diagram of a conventional computer system.

FIG. 42 is an explanatory diagram of a branch process of a conventional computer system.

FIG. 43 is a block diagram of a trace function of a program execution unit of a conventional computer system.

FIG. 44 is a data structure diagram of the trace history register of FIG. 43.

FIG. 45 is a flowchart of the trace function of the program execution unit of the conventional computer system.

FIG. 46 is a flowchart showing an operation of a program rewrite processing unit of a conventional computer system.

FIG. 47 is a block diagram of an IO interrupt notification function of a conventional computer system.

48 is a flow chart showing a flow of interrupt notification processing of the IO interface of FIG. 47.

49 is a flowchart showing a flow of an interrupt reception process of the processor of FIG. 47.

FIG. 50 is a block diagram of a conventional computer system.

FIG. 51 is a configuration diagram of a conventional failure processing setting table.

FIG. 52 is a configuration diagram of a conventional configuration table unit.

FIG. 53 is a flowchart showing a conventional means for managing a failure processing setting table.

[Explanation of symbols]

1 maintenance tool, 1a hard disk, 2 system bus, 4 plant, 3 IO interface, 4
Plant system, 5 memory, 5a control program, 5b page management table, 5c branch block,
6 request processing unit, 6a receiving unit, 6b transmitting unit, 6c
Program rewriting unit, 6d Maintenance processing unit, 6e
Time monitoring unit, 6f cancellation processing unit, 6g program forced stop unit, 7 program execution unit, 8 IO
Interrupt reception 10, 10-1 to 10-N processor, 2
0 configuration table section, 21 failure processing setting table section,
22 failure information of each card, 23 failure processing output section, 2
4 failure processing failure monitoring section, 25 backup data information area, 400 trace memory, 401 trace data collection section, 401a trace history register, 40
2 control program address, 403 address match detection unit, 403a address match start register, 403b
Address match end register, 404 trace signal,
405 address rewriting unit, 600 IO interrupt / error reception, 601 interrupt notification unit, 602 interrupt number, 60
3 error number, 604 plant data, 605 interrupt detection unit, 606 interrupt support information, 607 error support information, 608 multiple interrupt support information, 650 processor card failure detection unit, 651 interrupt / error support information update unit, 652 Processor change card table, 653
Failure detector.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 11/30 305 G06F 11/30 305F 12/00 514 12/00 514E 15/16 450 15/16 450D 470 470U (72) Inventor Mamoru Miyoshi 6-1-2 Hamayama-dori, Hyogo-ku, Kobe-shi, Hyogo Mitsubishi Electric Control Software Co., Ltd. (72) Masatoshi Saito 6-1-1 Hamayama-dori, Hyogo-ku, Kobe, Hyogo Prefecture No. 2 Mitsubishi Electric Control Software Co. Ltd. (72) Inventor Hiroyuki Nakano 2-6-2 Otemachi, Chiyoda-ku, Tokyo Sanryo Engineering Co., Ltd. (72) Inventor Akio Toda 2-chome Marunouchi, Chiyoda-ku, Tokyo No. 2 and 3 Sanryo Electric Co., Ltd.

Claims (9)

[Claims] 1. When registering a program in a memory in advance, a branch destination of a branch instruction in the program is a branch logical address indicated by the number of instruction steps from the beginning of the program, and the branch logical address is an operand of the branch instruction. And a means for executing the branch instruction by converting the branch destination logical address of the operand of the branch instruction into a branch destination physical address when executing the branch instruction. 2. When registering a program in a memory in advance, a branch destination of a branch instruction in the program is a branch physical address indicated by an offset address from the head of the memory, and the branch physical address is registered as an operand of the branch instruction. And a means for executing a branch instruction based on a branch destination physical address of an operand of the branch instruction when the branch instruction is executed. 3. A computer that executes maintenance in response to a maintenance request from a plurality of maintenance tools, and error detection means for detecting an abnormal state of the maintenance tools.
A computer comprising: a stopping unit that, when the error detecting unit detects an error, stops the maintenance process corresponding to the maintenance request from the maintenance tool in which the error is detected. 4. A computer which stores trace data in a trace memory while monitoring a trace data collection range from a trace data collection start address to a trace data collection end address during execution of a program, stores data corresponding to one address. When the data is collected, a means for updating the trace data collection start address to the address of the next program that collected the trace data is provided, and the trace data collection range from the updated trace data collection start address to the trace data collection end address is monitored. However, the computer is characterized in that the trace data is stored in the trace memory. 5. When a rewriting request is made to a program being executed, if the program is being executed and the program is still running even after a lapse of a predetermined time, the execution of the program is stopped to rewrite the program. A computer comprising means for performing. 6. A computer system in which a control target is controlled by a plurality of computers via an input / output interface, and the input / output interface notifies each computer as an interrupt signal from the control target as an input. A computer system characterized in that the interface has means for setting a computer to be executed in advance according to the contents of an interrupt signal and notifying only the computer that executes the input interrupt signal. 7. A computer system in which a control target is controlled by a plurality of computers through an input / output interface, and the input / output interface notifies each computer as an interrupt signal from the control target as input. The interface sets a computer to be executed in advance according to the contents of the interrupt signal, and means for notifying only the computer that executes the input interrupt signal, and if the input interrupt signal is not normal. A computer system comprising: a unit configured to notify a preset computer of error information. 8. The input / output interface according to claim 6 or 7, wherein failure detecting means for detecting a failure of the computer and a computer to be changed when the computer fails are set in advance, and the computer to be changed is set. A computer system comprising: a computer changing means for switching to a computer, the computer being changed by the computer changing means when the failure is detected in the interrupt notification destination or the error information notifying destination computer. 9. In a computer system in which each computer is arranged on a card and the computers are connected to each other, the settings of each computer are backed up in correspondence with the type of each card and its mounting position. A backup means to be stored and a first setting means for setting a card of a type corresponding to the mounting position at the mounting position when the card is mounted, and the setting means held by the backup means, and when mounting the card, A computer system, comprising: a second setting means for setting a standard value set in advance when a card of a type that does not correspond to the mounting position is mounted at the mounting position.