JPH09289324A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for the manufacture of a semiconductor device that uses SOI(Silicon On Insulator) substrates and enables the reduction of both time and cost required for manufacture. SOLUTION: A semiconductor device is manufactured as follows: The active silicon layer 1c of a SOI substrate 1 is subjected to element isolation to form a plurality of element isolation regions 8. An impurity for n-type well region formation is ion-implanted in the entire surface with the element isolation regions 8 formed thereon, and then an impurity for p-type well region formation is ion-implanted using photoresist 10 as a mask 9. Next, two types of impurities are ion-implanted using photoresist 11 as a mask, and then two types of impurities are ion-implanted using photoresist 12 as a mask. Subsequently, a polysilicon layer 7a is deposited in desired positions. Then its resistance value is adjusted and the polysilicon layer is patterned into a specified shape to form a polysilicon resistor 7. A gate oxide film 13 is formed on the element isolation regions 8 and the polysilicon resistor 7, and contact holes 15 are formed. Finally, metal wiring 16 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Conventionally, a high density semiconductor integrated circuit such as a gate array using CMOS is mainly made of bulk Si, and few ones use an SOI (Silicon on Insulator) substrate. This is partly because the cost of the SOI substrate is about 10 times higher than that of bulk Si.

[0003]

However, bulk Si
In the process using, the standard number of masks is 10 or more even in the process of single-layer wiring, and there is a problem that it takes about 2 months due to a long well drive and the like in the manufacturing period.

Further, when a passive element such as a resistor, a diode or a capacitor is incorporated, there is a problem that the number of steps is increased and the manufacturing period is further lengthened.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device using an SOI substrate, which has a short manufacturing period and can reduce the cost. It is to provide a manufacturing method.

[0006]

According to the first aspect of the present invention,
A silicon oxide film is formed on the active silicon layer of an SOI substrate in which a supporting silicon substrate, an insulating film formed on the supporting silicon substrate, and an active silicon layer formed on the insulating film are integrally configured. A silicon nitride film is formed, etching is performed until a desired position of the silicon nitride film reaches the silicon oxide film, and LOCOS oxidation is performed using the silicon nitride film as a mask to form a plurality of elements including the active silicon layer. The separation area is formed, and the S
By implanting an impurity ion for forming an N-well region on the entire surface of the OI substrate on which the element isolation region is formed, the threshold value in the MOS structure of the element isolation region for PMOS formation is controlled, and A photoresist is applied on the element isolation region, and a photoresist is not applied on the element isolation region for forming the NMOS, and impurities are ion-implanted for forming the P well region so that the NMOS for forming the NMOS is formed. MO of the element isolation region
After controlling the threshold in the S structure, the photoresist is removed, the photoresist is applied at a desired position, and ion implantation of impurities for forming the source and drain regions of the PMOS and NMOS is performed. Is removed and the silicon oxide film formed on the active silicon layer is removed by etching, and then a gate oxide film is formed on the element isolation region by thermal oxidation and the device is formed at a desired position of the oxide film. The CMOS is formed by forming an opening reaching the isolation region and performing metal wiring so as to fill the opening.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the PMOS and NMO are provided.
A plurality of types of impurities are ion-implanted as impurities for forming the source and drain regions of S, and a concentration gradient is applied to the source and drain regions by utilizing the difference in diffusion rate.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, among the plurality of element isolation regions, the element isolation region for forming the NMOS and the element isolation region for forming the PMOS are formed. Using at least one of the element isolation regions excluding the element isolation region as a resistance element,
When performing ion implantation of impurities for forming the source and drain regions, a contact is formed by simultaneously performing ion implantation at a desired position in the element isolation region for forming the resistance element. It is a thing.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first to third aspects, among the plurality of element isolation regions, the element isolation region for forming the NMOS and the element isolation region for forming the PMOS are formed. At least one of the element isolation regions excluding the element isolation region is used as a capacitor,
When the impurities are ion-implanted for forming the source and drain regions, the ion-implantation is simultaneously performed on the element isolation region for the capacitor.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first to fourth aspects, among the plurality of element isolation regions, the element isolation region for forming the NMOS and the element isolation region for forming the PMOS are formed. At least one of the element isolation regions excluding the element isolation region is used as a diode,
When performing the ion implantation of the impurities for forming the source and drain regions, the contacts are formed by simultaneously performing the ion implantation at a desired position of the element isolation region for the diode. is there.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first to fifth aspects, a polysilicon layer is formed at a desired position after completion of all the ion implantation, and the polysilicon layer is formed. It is characterized in that the resistance value is adjusted by ion-implanting impurities into and the polysilicon layer is used as a polysilicon resistor.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. 1 is a schematic cross-sectional view showing a front stage of a process of manufacturing a CMOS and a passive device on an SOI substrate 1 according to an embodiment of the present invention, and FIG. 2 is a CMOS on the SOI substrate 1 according to the present embodiment. FIG. 6 is a schematic cross-sectional view showing a latter stage of the process of manufacturing the passive element. In the present embodiment, for convenience of description, an NMOS is formed on the SOI substrate 1.
2, the case of forming the PMOS 3, the diffusion resistor 4, the diode 5, the capacitor 6, and the polysilicon resistor 7 will be described. An SOI (Silicon on Insulator) substrate 1 includes a supporting silicon substrate 1a, an insulating film 1b such as a silicon oxide film formed on the supporting silicon substrate 1a, and an insulating film 1.
The active silicon layer 1c which is to be the semiconductor element region and is formed on b is integrally formed (FIG. 1A).

As a method of forming the SOI substrate 1,
An SOI growth method for growing single crystal silicon in each phase of a gas phase, a liquid phase, and a solid phase on an insulating layer, a bonding SOI method for bonding substrates, and an oxygen ion implantation into a single crystal silicon substrate SIMOX (Silicon
Implanted Oxidation) method, a method of partially oxidizing silicon by anodic oxidation, and then forming it by oxidation.

First, the active silicon layer 1c of the SOI substrate 1
Are isolated by LOCOS (Local Oxidation of Silicon) oxidation to form a plurality of element isolation regions 8 made of the active silicon layer 1c (FIG. 1B). As an example of a method for element isolation by LOCOS oxidation of the active silicon layer 1c, a silicon oxide film 9 is formed on the active silicon layer 1c by thermal oxidation, and silane (SiH _{4) is used} as a source gas on the silicon oxide film 9. ) And ammonia (NH ₃ ) are used to form a silicon nitride film by a low pressure CVD method, a photoresist is applied on the silicon nitride film, and exposure and development are performed to form an opening in the photoresist. Then, after etching the silicon nitride film with fluorine radicals in CF4 gas plasma using the photoresist with the opening formed as a mask, the photoresist is removed by plasma ashing or the like, and LOCOS oxidation is performed using the silicon nitride film as a mask. To do. Finally, the silicon oxide film formed by LOCOS oxidation on the silicon nitride film is removed by etching using an etchant such as an HF aqueous solution, and then the silicon nitride film is removed by hot phosphoric acid or the like.

Next, in order to control the threshold value of the PMOS 3, an impurity such as phosphorus (P ⁺ ) for forming an N well region is ion-implanted over the entire surface of the SOI substrate 1 on which the LOCOS oxidation has been performed (see FIG. c)), a photoresist 10 is applied on a portion where the PMOS 3 is manufactured, and impurities for forming a P well region such as boron (B ⁺ ) are subjected to LOCOS oxidation of the SOI substrate 1 for controlling the threshold value of the NMOS ^2. Ions are implanted into the exposed surface (FIG. 1D), and the photoresist 10 is removed by plasma ashing or the like.

In the present embodiment, FIGS.
Diffuser resistor 4, diode 5 and capacitor 6 at N
The case of manufacturing with a mold is shown, but the invention is not limited to this.
In the process of 2, the photoresist may be applied on the diffusion resistor 4, the diode 5 and the capacitor 6.

Subsequently, in order to form the source and drain regions of the PMOS 3, the contact of the diffused resistor 4 and the diode 5, and the capacitor 6, a photoresist 11 is applied at a desired position and ions of a P-type high concentration impurity are formed. After injection (FIG. 1 (e)), the photoresist is removed,
In order to form the source and drain regions of the NMOS 2, the photoresist 12 is applied at a desired position and ion implantation of N-type high concentration impurities is performed (FIG. 1F), and then the photoresist 12 is removed.

When implanting N-type and P-type high-concentration impurities, two types of ion sources are used, for example, phosphorus (P ⁺ ) and arsenic (As ⁺ ) in the case of N-type, and P-type in the case of N-type. Then, boron (B ⁺ ) and boron difluoride (BF ₂ ⁺ ) are simultaneously injected, and a concentration gradient is applied to the source and drain regions by utilizing the difference in diffusion rate between these two types of ion sources in the subsequent thermal diffusion process. If it is attached, the breakdown voltage can be improved.

When the diffusion resistor 4, the diode 5 and the capacitor 6 are made of P type, P type high concentration impurity diffusion is performed to form the contact between the diffusion resistor 4 and the diode 5 and the capacitor 6.

In this embodiment, the N-type high-concentration impurity ion implantation is performed after the P-type high-concentration impurity ion implantation. However, the present invention is not limited to this. The ion implantation of the P-type high-concentration impurity may be performed after the ion implantation of the N-type high-concentration impurity.

Further, although the case where two types of ion sources are ion-implanted has been described in the present embodiment, the present invention is not limited to this, and three or more types of ion sources may be ion-implanted. .

Then, silane (Si
The polysilicon layer 7 is formed by a low pressure CVD method using H ₄ ).
a is deposited, and phosphoryl trichloride (POCl ₃ ) is thermally diffused to adjust the resistance value of the polysilicon layer 7a, and then patterned into a predetermined shape to manufacture a polysilicon resistor 7 (FIG. 2 (g)). . As an example of a method of manufacturing the polysilicon resistor 7, a photoresist is applied on the polysilicon layer 7a, exposed and developed to form an opening at a desired position, and the photoresist is used as a mask for dry etching. After the polysilicon layer 7a is etched by the method described above, the photoresist is removed by plasma ashing or the like to manufacture the polysilicon resistor 7.

Then, the active silicon layer 1 of the SOI substrate 1
The silicon oxide film 9 formed on c is removed by etching using an etchant such as an HF aqueous solution, and then the NMOS 2, PMOS 3, diffusion resistor 4, diode 5, capacitor 6, and polysilicon resistor 7 are manufactured. A gate oxide film 13 such as a silicon oxide film is formed on the element isolation region 8 of FIG. 2 (FIG. 2 (h)), a photoresist 14 is applied at a desired position, and dry etching or the like is performed to form a contact hole 15. (FIG. 2B (i)),
The photoresist 14 is removed by plasma ashing or the like.

Here, in the present embodiment, the gate oxide film 13 is formed by thermal oxidation, and the impurities that have been ion-implanted in the previous steps are collectively subjected to thermal diffusion (drive) by individual thermal oxidation steps. )can do.

Finally, metal wiring 16 is formed so as to fill the contact hole 15 to manufacture the NMOS 2, PMOS 3, diffusion resistor 4, diode 5, capacitor 6 and polysilicon resistor 7 on the SOI substrate 1 (FIG. 2). (J)). As an example of a method for forming the metal wiring 16, an Al-Si-Cu layer is formed by performing sputtering using Al-Si-Cu as a target,
It is formed by patterning into a predetermined shape using photolithography technology and etching technology.

Therefore, in the present embodiment, when the CMOS is manufactured on the SOI substrate 1, the diffusion resistor 4, the diode 5, the capacitor 6, the polysilicon resistor 7 and the like necessary for the analog circuit are mixed. However, there is almost no need to change the process, and the manufacturing period can be reduced. Further, in the present embodiment, since the step difference on the surface is very small, the step of smoothing the surface can be omitted, and it is also effective when multilayer wiring is performed.
Further, in the present embodiment, the silicon oxide film 9 is removed by etching after the completion of all the ion implantations, so that it is possible to prevent the deterioration of the surface of the element isolation region 8 during the ion implantation, and Channeling can be prevented.

[0027]

According to the first aspect of the present invention, an SOI substrate is formed by integrally forming a supporting silicon substrate, an insulating film formed on the supporting silicon substrate, and an active silicon layer formed on the insulating film. Forming a silicon oxide film and a silicon nitride film on the active silicon layer, etching at a desired position of the silicon nitride film until the silicon oxide film is reached, and performing LOCOS oxidation using the silicon nitride film as a mask. In the MOS structure of the element isolation region for PMOS formation, by forming a plurality of element isolation regions made of layers and performing ion implantation of impurities for N well region formation on the entire surface of the SOI substrate on which the element isolation region is formed. The threshold is controlled, photoresist is applied on the element isolation region for PMOS formation, and photoresist is applied on the element isolation region for NMOS formation. NM by ion implantation of impurities for the P-well region formed in the door so as not applied
After controlling the threshold in the MOS structure of the element isolation region for OS formation, the photoresist is removed, the photoresist is applied at a desired position, and ion implantation of impurities for forming source and drain regions of PMOS and NMOS is performed. After that, the photoresist is removed, and the silicon oxide film formed on the active silicon layer is removed by etching,
A gate oxide film is formed on the element isolation region by thermal oxidation, an opening reaching the element isolation region is formed at a desired position of the oxide film, and a metal wiring is formed so as to fill the opening to form a CMOS. As a result, the number of times of masking can be reduced, and it is possible to provide a method for manufacturing a semiconductor device that uses an SOI substrate, has a short manufacturing period, and can reduce costs.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, a plurality of types of impurities are ion-implanted as impurities for forming the source and drain regions of the PMOS and NMOS, and a difference in diffusion rate is obtained. Since a concentration gradient is applied to the source and drain regions using
The breakdown voltage of S and PMOS can be improved.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, among a plurality of element isolation regions, an element isolation region for forming an NMOS and a P element isolation region are formed.
At least one element isolation region other than the element formation region for MOS formation is used as a resistance element, and when ion implantation of impurities for source and drain region formation is performed, a desired element isolation region for resistance element formation is desired. Since the contact is formed by simultaneously performing ion implantation in the position, the resistance element can be manufactured without changing the process when forming the CMOS.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first to third aspects, among a plurality of element isolation regions, an element isolation region for forming an NMOS and a PM are formed.
At least one of the element isolation regions other than the element isolation region for OS formation is used as a capacitor, and when ion implantation of impurities for source and drain region formation is performed, ion implantation is performed simultaneously on the element isolation region for the capacitor. Since this is done, the capacitor can be manufactured without changing the process when forming the CMOS.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first to fourth aspects, among a plurality of element isolation regions, an element isolation region for forming an NMOS and a PM are formed.
At least one of the element isolation regions other than the element isolation region for OS formation is used as a diode, and when ion implantation of impurities for source and drain region formation is performed, it is simultaneously performed at a desired position of the element isolation region for diode. Since the contact is formed by performing the ion implantation, the diode can be manufactured without changing the process for forming the CMOS.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first to fifth aspects, a polysilicon layer is formed at a desired position after the completion of all ion implantations, and impurities are added to the polysilicon layer. Since the resistance value is adjusted by performing the ion implantation of and the polysilicon layer is used as the polysilicon resistor, the polysilicon resistor can be manufactured with almost no process changes when forming the CMOS.

[Brief description of drawings]

FIG. 1 is a CM on an SOI substrate according to an embodiment of the present invention.
It is a schematic sectional drawing which shows the front | former stage of the process of manufacturing OS and a passive element.

FIG. 2 is a schematic cross-sectional view showing a latter stage of a process of manufacturing a CMOS and a passive element on the SOI substrate according to the present embodiment.

[Explanation of symbols]

 1 SOI substrate 1a Supporting silicon substrate 1b Insulating film 1c Active silicon layer 2 NMOS 3 PMOS 4 Diffusion resistance 5 Diode 6 Capacitor 7 Polysilicon resistance 7a Polysilicon layer 8 Element isolation region 9 Silicon oxide film 10-12 Photoresist 13 Gate oxide Film 14 Photoresist 15 Contact hole 16 Metal wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location // H01L 29/861 H01L 27/08 321B 29/78 613Z 621 29/91 E

Claims (6)

[Claims] 1. An active silicon layer of an SOI substrate in which a supporting silicon substrate, an insulating film formed on the supporting silicon substrate, and an active silicon layer formed on the insulating film are integrally configured. A silicon oxide film and a silicon nitride film are formed on the silicon nitride film, etching is performed until a desired position of the silicon nitride film reaches the silicon oxide film, and LOCOS oxidation is performed using the silicon nitride film as a mask to form the active silicon layer. A plurality of element isolation regions made of, and ion-implanting impurities for forming an N well region to the entire surface of the SOI substrate on which the element isolation regions are formed, thereby forming M of the element isolation region for forming the PMOS.
A threshold is controlled in the OS structure, a photoresist is applied on the element isolation region for forming the PMOS, and NMO is applied.
The threshold value in the MOS structure of the element isolation region for forming the NMOS is controlled by performing ion implantation of impurities for forming the P well region without applying photoresist on the element isolation region for forming S. After that, the photoresist is removed, a photoresist is applied at a desired position and ion implantation of impurities for forming the source and drain regions of the PMOS and NMOS is performed, and then the photoresist is removed to remove the active silicon. After removing the silicon oxide film formed on the layer by etching, a gate oxide film is formed on the element isolation region by thermal oxidation, and an opening is formed to reach the element isolation region at a desired position of the oxide film. And forming a CMOS to form a CMOS by forming a metal wiring so as to fill the opening. Method of manufacturing a body apparatus. 2. A plurality of types of impurities are ion-implanted as impurities for forming the source and drain regions of the PMOS and NMOS, and a concentration gradient is applied to the source and drain regions by utilizing a difference in diffusion rate. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is manufactured. 3. The NM among the plurality of element isolation regions
At least one of the element isolation regions excluding the element isolation region for OS formation and the element isolation region for PMOS formation is used as a resistance element, and ion implantation of impurities for source and drain region formation is performed, 3. The method of manufacturing a semiconductor device according to claim 1, wherein a contact is formed by simultaneously performing ion implantation at a desired position in the element isolation region for forming the resistance element. 4. The NM among the plurality of element isolation regions
At least one of the element isolation regions excluding the element isolation region for forming the OS and the element isolation region for forming the PMOS is used as a capacitor, and when ion implantation of impurities for forming the source and drain regions is performed, 4. The method of manufacturing a semiconductor device according to claim 1, wherein ion implantation is performed simultaneously on the element isolation region for the capacitor. 5. The NM among the plurality of element isolation regions
At least one of the element isolation regions excluding the element isolation region for forming the OS and the element isolation region for forming the PMOS is used as a diode, and when ion implantation of impurities for forming the source and drain regions is performed, 5. The method of manufacturing a semiconductor device according to claim 1, wherein the contact is formed by simultaneously performing ion implantation at a desired position in the element isolation region for the diode. 6. A polysilicon layer is formed at a desired position after the completion of all the ion implantation, and impurity ions are implanted into the polysilicon layer to adjust the resistance value. The semiconductor device manufacturing method according to claim 1, wherein the method is used as a resistor.