JPH09284636A - Camera device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert the aspect ratio of an image pickup signal to be supplied to a view finder. SOLUTION: When a prescribed operation is executed in an operating part 18, a microcomputer 19 supplies respective segmenting signals to an aspect ratio converting circuit 5 and supplies a clock rate signal to a clock generating circuit 20. Respective FIFO memories in the aspect ratio converting circuit 5 are respectively set a segment position and a clock generating circuit 20 generates a writing and reading clock by a prescribed clock rate. Therefore, image element data with respectively different sample numbers are read at every 1H so that the video signals with the different aspect ratios are respectively outputted in 1V period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a camera device capable of converting the aspect ratio of an image pickup signal.

[0002]

2. Description of the Related Art Television broadcasting is, for example, an NTSC (Natinal Television System Comm) with an aspect ratio of 4: 3.
HDTV (Hig with aspect ratio of 16: 9)
h Definition Television) system is moving to the system. Therefore, the present applicant has proposed an aspect ratio conversion device as disclosed in Japanese Patent Laid-Open No. 5-252538. A camera device to which such an aspect ratio conversion device is applied converts the aspect ratio of a video signal and supplies the video signal to a recording / reproducing system and a viewfinder. Therefore, when the aspect ratio of the video signal is converted, the camera device converts not only the video signal supplied to the recording / reproducing system but also the aspect ratio of the imaging signal supplied to the viewfinder.

[0003]

However, in the above camera device, the aspect ratio of the image pickup signal supplied to the viewfinder cannot be converted without changing the aspect ratio of the image pickup signal supplied to the recording / reproducing system. . Therefore, when the user is capturing an image of a subject with such a camera device, a part of the image by the image pickup signal supplied to the recording / reproducing system cannot be enlarged and displayed on the viewfinder and confirmed. Also, it was very inconvenient because it was not easy to check the image that was about to enter the image area to be recorded from the outside.

The present invention has been made in view of such circumstances, and an object thereof is to provide a camera device capable of converting the aspect ratio of an image pickup signal supplied to a viewfinder.

[0005]

In order to solve the above problems, a camera device according to the present invention comprises an image pickup means for generating an image pickup signal having a first aspect ratio based on an image pickup signal from a subject. A storage unit that stores the image pickup signal having the first aspect ratio, and a second image pickup signal having the first aspect ratio and a part of the first aspect ratio cut out in the horizontal direction from the storage unit. Control means for selectively reading the image pickup signal having the aspect ratio and display means for displaying a subject image based on the image pickup signal read from the storage means are provided.

The camera device selectively selects, from the storage means, an image pickup signal having a first aspect ratio and an image pickup signal having a second aspect ratio obtained by cutting out a part in the horizontal direction from the first aspect ratio. And the subject image based on the image pickup signal read from the storage means is displayed on the display means.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A camera device to which the present invention is applied is
For example, as shown in FIG. 1, CCD image sensors 1R, 1G, and 1B that output pixel signals R (red), G (green), and B (blue) of three primary colors in accordance with imaging light of a subject, and a CCD image sensor. CDS (correlated double sampling) circuits 2R, 2G, and 2B for removing random noise included in pixel signals from 1R, 1G, and 1B, and CDS circuits 2R, 2G, and
A / D converters 3R, 3G, 3B for converting pixel signals from 2B into pixel data of digital signals, and a process processing unit 4 for performing so-called process processing on the pixel data from the A / D converters 3R, 3G, 3B, Aspect ratio conversion circuits 5 and 8 are provided for converting the aspect ratio of the video signal in the vertical scanning period (V period) by controlling the writing / reading of the pixel data supplied from the process processing unit 4.

The camera device further includes an operating section 18 for setting read / write operations in the aspect ratio converting circuits 5 and 8, and an aspect ratio converting circuits 5 and 8 according to the operation of the operating section 18. A microcomputer 19 for controlling (hereinafter referred to as a microcomputer) and a clock generation circuit 20 for generating a clock to be supplied to the aspect ratio conversion circuits 5, 8 under the control of the microcomputer 17 are provided.

CCD image sensors 1R, 1G, 1B
Is, for example, the imaging light incident from an imaging lens (not shown) through an optical low-pass filter is decomposed into three primary color light components by a photolytic prism, and a three primary color image of a subject image is
The image is picked up by one CCD image sensor, and pixel signals R, G,
B is output.

Here, the CCD image sensors 1R, 1
The G and 1B are adapted to be driven based on the horizontal synchronizing signal and the vertical synchronizing signal from the timing generator 16 via the driver 17. The timing generator 16 is adapted to generate the horizontal synchronization signal and the vertical synchronization signal based on the synchronization pulse supplied from the sync generator 15.

The CDS circuits 2R, 2G, 2B remove random noise contained in the pixel signals R, G, B supplied from the CCD image sensors 1R, 1G, 1B, and remove the pixel signals from the A / D converter 3R, Supply to 3G and 3B.

The A / D converters 3R, 3G, 3B use a sampling clock based on the synchronization signal from the timing generator 16 to convert pixel data into pixel data of 10 bits for each pixel signal. Is supplied to the process processing unit 4.

The process processor 4 includes an A / D converter 3
Each pixel data R, G, B supplied from R, 3G, 3B
On the other hand, so-called process processing such as image enhancement processing, pedestal addition, and non-linear processing such as gamma knee is performed. Then, the process processing unit 4 performs a matrix process on the pixel data R, G, B to generate pixel data Y, RY,
The pixel data Y for viewfinder conversion is supplied to the aspect ratio conversion circuit 5, and so-called main line pixel data Y, RY, BY are supplied to the aspect ratio conversion circuit 8.

The aspect ratio conversion circuit 5 includes FIFO memories 5a to 5d connected in parallel. In this aspect ratio conversion circuit 5, pixel data Y of, for example, an odd line (odd field) is written in the FIFO memory 5a and the FIFO memory 5b, and the FIFO memory 5
For example, pixel data Y of even lines (even fields) is written in the c and FIFO memories 5d.

Here, the FIFO memory 5a and the FIFO memory
When the pixel data Y of the odd line is written in the memory 5b, the FIFO memory 5c and the FIFO memory 5
The even line pixel data Y is read out to d, and when the odd line pixel data Y is read out to the FIFO memory 5c and the FIFO memory 5d, the FIFO memory 5c and the FIFO memory 5d are read out.
The pixel data Y of even-numbered lines are written in. Further, odd-numbered pixel data of odd-numbered lines is written in the FIFO memory 5a, and even-numbered pixel data of odd-numbered lines is written in the FIFO memory 5b. Further, odd-numbered pixel data of even lines are written in the FIFO memory 5c, and even-numbered pixel data of even lines are written in the FIFO memory 5d.

The FIFO memory 5a and the FIFO memory 5b have a capacity capable of storing pixel data Y for at least H periods in total, and the FIFO memory 5c and the FIFO memory 5d have at least H in total.
It has a capacity capable of storing pixel data Y for a period.

Further, the aspect ratio conversion circuit 8 includes an aspect ratio conversion section 11 in which the main line luminance data Y is written.
And an aspect ratio conversion unit 12 in which main line color difference data RY is written and an aspect ratio conversion unit 13 in which main line color difference data B-Y is written.

The aspect ratio conversion section 11 has substantially the same structure as the aspect ratio conversion circuit 5 described above, and includes FIFO memories 11a to 11d connected in parallel. In the aspect ratio conversion unit 11, for example, pixel data Y of an odd line is written in the FIFO memory 11a and the FIFO memory 11b, and the FIFO memory 11
Pixel data Y of even lines, for example, is written in the c and FIFO memory 11d.

Here, the FIFO memory 11a and the FIFO memory
When the odd line pixel data Y is written to the O memory 11b, the even line pixel data Y is read to the FIFO memory 11c and the FIFO memory 11d, and the FIFO memory 11c and the FIFO memory 11d are read. When the pixel data Y of the odd line is read to 11d, the FIFO memory 11c and FI
Pixel data Y of even lines is written in the FO memory 11d. In addition, FIFO memory 1
The odd-numbered pixel data of the odd-numbered line is written in 1a, and the even-numbered pixel data of the odd-numbered line is written in the FIFO memory 11b. Further, odd-numbered pixel data of even lines are written in the FIFO memory 11c, and even-numbered pixel data of even lines are written in the FIFO memory 11d.

The FIFO memory 11a and the FIFO memory
The memory 11b has a capacity capable of storing at least the pixel data Y for at least the H period, and the FIFO memory 11c and the FIFO memory 11d can store at least the pixel data Y for at least the H period. Has capacity.

The aspect ratio conversion section 12 includes FIFO memories 12a to 12d connected in parallel.
In the aspect ratio converter 12, the FIFO memory 12
For example, odd-numbered line pixel data R-Y is written in the a and FIFO memory 12b, and even-line pixel data R-Y is written in the FIFO memory 12c and FIFO memory 12d.

Here, the FIFO memory 12a and the FIFO memory
When the odd-numbered line pixel data RY is written in the O memory 12b, the FIFO memory 12c and the FIFO memory 12c
Even-numbered lines of pixel data RY are read out to the O memory 12d.
2c and the FIFO memory 12d read the odd line pixel data RY, the FIFO memory 1
2c and the FIFO memory 12d are adapted to write pixel data RY of even lines. further,
The odd-numbered pixel data of the odd-numbered line is written in the FIFO memory 12a, and the even-numbered pixel data of the odd-numbered line is written in the FIFO memory 12b. Further, odd-numbered pixel data of even lines are written in the FIFO memory 12c, and even-numbered pixel data of even lines are written in the FIFO memory 12d.

The FIFO memory 12a and the FIFO memory
The memory 12b has a capacity capable of storing at least the pixel data RY for at least the H period, and has a FIF.
The O memory 12c and the FIFO memory 12d together have a capacity capable of storing at least the pixel data RY for the H period.

The aspect ratio conversion unit 13 includes FIFO memories 13a to 13d connected in parallel.
In the aspect ratio conversion unit 13, the FIFO memory 13
For example, odd-numbered line pixel data BY is written in the a and FIFO memory 13b, and even-line pixel data BY is written in the FIFO memory 13c and FIFO memory 13d.

Here, the FIFO memory 13a and the FIFO memory
When the odd line pixel data BY is written in the O memory 13b, the FIFO memory 13c and the FIFO memory 13c
Even-numbered lines of pixel data BY are read out to the O memory 13d.
3c and the FIFO memory 13d read the odd line pixel data BY, the FIFO memory 1
3c and the FIFO memory 13d are configured to write the pixel data BY of even lines. further,
The odd-numbered pixel data of the odd-numbered line is written in the FIFO memory 13a, and the even-numbered pixel data of the odd-numbered line is written in the FIFO memory 13b. Further, odd-numbered pixel data of even lines are written in the FIFO memory 13c, and even-numbered pixel data of even lines are written in the FIFO memory 13d.

The FIFO memory 13a and the FIFO memory
The memory 13b has a capacity capable of storing pixel data BY of at least H period in total, and has a FIF
The O memory 13c and the FIFO memory 13d together have a capacity capable of storing at least the H period of pixel data BY.

Then, in the aspect ratio conversion circuits 5 and 8 as described above, each of the FIFO memories described above writes the supplied pixel data and reads a part of the written pixel data for a period of 1V. , The aspect ratio of the field signal can be converted.

For example, taking the aspect ratio conversion circuit 5 as an example, each of the FIFO memories 5a to 5d is 1H.
Pixel data is written during the period, and the pixel data is read out in the written order. Each of the FIFO memories 5a to 5d sets a cutout position, which is a position where reading of pixel data is started, based on a cutout signal from the microcomputer 19. Then, the FIFO memory sequentially reads pixel data written later from this cutout position.

Specifically, as shown in FIG. 2, the FIFO
Pixel data of N samples (all pixel data in 1H period) in the odd line is written in the memories 5a and 5b in synchronization with the write clock CK1 from the clock generation circuit 20. Then, the microcomputer 19 uses the FIFO memory 5
The cutout signal in which the information of the cutout positions in a and 5b is overlapped is supplied to the FIFO memories 5a and 5b, and the clock rate signal in which the information indicating the clock rate of the read clock CK3 is overlapped is clocked. It is supplied to the generation circuit 20. The clock rate of the read clock CK3 is less than or equal to the clock rate of the write clock CK1.

Here, the cut-out signal is the FIFO memory 5
It is a signal indicating the length from the register position where the pixel data is written to a and 5b at the end of the 1H period to the register position where the pixel data is read. Therefore, FIF
When the cutout signal is supplied to the O memories 5a and 5b,
Set the cutout position. The clock rate signal is a signal determined according to the amount of pixel data read from the cutout position in the 1H period. Therefore, the clock generation circuit 20 generates the read clock CK3 based on the clock rate signal, and uses the read clock CK3 as a FIFO.
It is supplied to the memories 5a and 5b.

In the FIFO memories 5a and 5b, the period for reading pixel data is 1H period. Therefore, the pixel data of E samples (<N samples) is delayed by 1H in synchronization with the read clock CK3 from the set cutout position. (Group delay)
Occurs and is read. As a result, the aspect ratio conversion circuit 5 can cut out the pixel data in the 1H period, and by cutting out the pixel data in the 1V period, the aspect ratio converted field signal can be output. it can.

Note that the FIFO memories 5c and 5d are also FI
Similarly to the FO memories 5a and 5b, the even-numbered line pixel data is written in synchronization with the write clock CK1, the cutout position is set based on the cutout signal, and the pixel data of the pixel data is synchronized with the read clock CK3. It can be cut out. However, the FIFO memories 5a and 5b and the FIFO memories 5c and 5d are in the opposite phase in writing and reading of pixel data.

Further, the aspect ratio conversion circuit 5 applies a group delay of 1H period to the pixel data even when reading out all the written pixel data, as in the case of cutting out the pixel data. Then, this pixel data can be read.

The aspect ratio conversion circuit 5 will be described as an example. In the aspect ratio conversion circuit 5, every 1H period,
Pixel data for one line supplied from the process processing unit 4 is distributed and written in the FIFO memories 5a to 5d in synchronization with the write clock CK1H. The pixel data written in the FIFO memories 5a to 5d are written in the write clock C in the order in which they are written.
All are read in synchronization with K1H.

Specifically, the FIFO memories 5a to 5d
When a cutout signal is supplied from the microcomputer 19, the cutout position for reading all the written pixel data is set.

Here, the cutout signal is the FIFO memory 5a.
Is a signal indicating the length from the register position where the pixel data is written to the end of the 1H period to 5d to the register position where the pixel data is read out.
The position of the register where the pixel data is first written in the memories 5a to 5d is shown. The cutout positions of the FIFO memories 5a to 5d are set based on the cutout signal.

The clock rate signal is a signal determined according to the amount of all pixel data written in the FIFO memories 5a and 5b in the 1H period from the cutout position. In this case, the write clock CK1 is used. It shows the same clock rate. The clock generation circuit 20 generates a read clock CK1H based on the clock rate signal, and uses the read clock CK1H as the FIFO memory 5a.
Supply to ~ 5d.

Then, the FIFO memories 5a to 5d can read the pixel data for 1H period in the order in which the pixel data is written from the position of the register in which the pixel data was first written. As a result, the aspect ratio conversion circuit 5 does not cut out the pixel data in the 1H period,
It is possible to directly output the pixel signal in which the group delay in the H period has occurred.

At this time, the aspect ratio conversion circuit 5 is set to 1
4 lines of pixel data instead of 2 FIFO memories
By writing the data in each of the FIFO memories 5a to 5d separately, the clock rates of the write clock and the read clock required for the FIFO memories 5a to 5d can be reduced to half of the normal rate, and the power consumption can be reduced.

As described above, the aspect ratio conversion circuit 5
Is capable of writing pixel data of odd or even lines of N samples in 1H period at the timing of clock CK1H, and reading all pixel data of even or odd lines written before the above 1H period at timing of clock CK1H. it can. That is, the aspect ratio conversion circuit 5 can output the pixel data in which the group delay of the 1H period occurs without cutting out the written pixel data. In other words, the aspect ratio conversion circuit 5
Even if you set / cancel aspect ratio conversion, you can output pixel data without changing the group delay.
Since the clock rates of the write clock and the read clock can be reduced, power consumption can be reduced.

The aspect ratio conversion circuit 5 and the aspect ratio conversion units 11, 12 and 13 have the same configuration, and the microcomputer 19 stores the pixel data in the aspect ratio conversion circuit 5 and the aspect ratio conversion circuit 8. By controlling the cutouts independently, the aspect ratios of the main line field signal and the viewfinder system field signal can be independently controlled. That is, the microcomputer 19 can combine the aspect ratios of the field signals to be supplied to the viewfinder system and the main line system to perform aspect ratio conversion of images of type 1 to type 6 as shown in FIG. 3, for example. .

Here, the CCD image sensors 1R, 1
In G and 1B, the number of effective pixels is 500,000, the aspect ratio is 16: 9, and 2288 sample pixel signals are output in the 1H period. That is, the CCD image sensors 1R, 1G, 1B output a field signal having an aspect ratio of 16: 9 for each 1V period. Further, it is assumed that pixel data of 1144 samples, which is half of 2288 samples, is written in each FIFO memory.

When the operation unit 18 is operated to enter the type 1 operation mode, the microcomputer 19 sets the cutout position of each FIFO memory in the aspect ratio conversion circuits 5 and 8 and the predetermined clock in the clock generation circuit 20. Generates a rate write / read clock. Then, as shown in Table 1, in the aspect ratio conversion circuit 5, the FIF
Pixel data of odd lines of, for example, 858 samples are cut out from the O memories 5a and 5b, respectively. In the aspect ratio conversion circuit 8, for example, the FIFO memories 11a and 11b are extracted.
The pixel data of odd lines of, for example, 858 samples are read out from each of.

[0044]

[Table 1]

Therefore, the aspect ratio conversion circuit 5 is
171 from 2288 sample pixel data every 1H period
Pixel data of 6 samples is cut out, and the number of samples of pixel data for one line is set to 3/4. Then, the aspect ratio conversion circuit 5 cuts out the pixel data so that the aspect ratio of the number of samples becomes 4: 3 in the 1V period, and reads the cut out pixel data over the 1H period, so that the aspect ratio 4: 3. Output the field signal of
This field signal is supplied to the viewfinder 7 via the D / A converter 6.

Similarly, the aspect ratio conversion circuit 8 also has a voltage of 1V.
During the period, a field signal having an aspect ratio of the number of samples of 4: 3 is output, and this field signal is supplied to the encoder 10 via the D / A converter 9. Therefore, the camera device can supply the cut-out video signal to the main line system and the same video signal as the main line system to the viewfinder 7 to display the mainline system image on the viewfinder 7.

When the operation unit 18 is operated to enter the type 2 operation mode, the microcomputer 19 sets the cutout position of each FIFO memory in the aspect ratio conversion circuits 5 and 8 and the predetermined clock in the clock generation circuit 20. Generates a rate write / read clock. Then, in the aspect ratio conversion circuit 5, the FIFO memories 5a and 5b are
The pixel data of odd lines of, for example, 429 samples are cut out from the respective pixels, and the aspect ratio conversion circuit 8 reads pixel data of odd lines of, for example, 858 samples from the FIFO memories 11a and 11b, respectively.

Therefore, the aspect ratio conversion circuit 5
Pixel data of 858 samples is cut out from the 2288 sample pixel data, and the cut-out pixel data is read out for 1H period, whereby the sample number of the pixel data for one line is set to 3/8. Then, the aspect ratio conversion circuit 5 has an aspect ratio of the number of samples of 2: in a 1V period.
Pixel data is cut out so that the field data has an aspect ratio of 4: 3, and the pixel data cut out so as to have a field ratio of 4: 3 is read over a period of 1V, and this field signal is read through the D / A converter 6 to the viewfinder 7 Supply to.

Further, the aspect ratio conversion circuit 8 has 228
The pixel data of 1716 samples is cut out from the 8-sample pixel data, and the cut-out pixel data is read out for 1H period, whereby the sample number of the pixel data for one line is set to 3/4. Then, the aspect ratio conversion circuit 8 cuts out the pixel data so that the aspect ratio of the number of samples becomes 4: 3 in the 1V period, and the aspect ratio 4: 3.
Pixel data cut out so as to become the field signal of
It is supplied to the encoder 10 via the / A converter 9.
Therefore, the camera device supplies the cut-out video signal to the main line system and also supplies the cut-out video signal to the viewfinder 7 so that the viewfinder 7 displays an enlarged image of a part of the main line system. By displaying the image on the screen, it is possible to improve the convenience of the user when performing the manual focus control.

When the operation unit 18 is operated to enter the type 3 operation mode, the microcomputer 19 sets the cut-out position of each FIFO memory in the aspect ratio conversion circuits 5 and 8 and the predetermined clock in the clock generation circuit 20. Generates a rate write / read clock. Then, in the aspect ratio conversion circuit 5, the FIFO memories 5a and 5b are
The pixel data of the odd line of, for example, 1144 samples are respectively cut out from the
For example, pixel data of odd lines of, for example, 858 samples are cut out from the FIFO memories 11a and 11b, respectively.

Therefore, the aspect ratio conversion circuit 5
1 written by cutting out all 2288 sample pixel data from 2288 sample pixel data
The pixel data for the line is output as it is. That is,
The aspect ratio conversion circuit 5 outputs a field signal having an aspect ratio of 16: 9 in a 1V period, and supplies this field signal to the viewfinder 7 via the D / A converter 6.

Further, the aspect ratio conversion circuit 8 has 228
The pixel data of 1716 samples is cut out from the 8-sample pixel data, and the cut-out pixel data is read out for 1H period, whereby the sample number of the pixel data for one line is set to 3/4. Then, the aspect ratio conversion circuit 8 sets the aspect ratio of the number of samples to 4: 3 in the 1V period.
Pixel data is cut out so that the aspect ratio is 4:
Pixel data cut out so as to have a field signal of 3 is read over a 1 V period, and this field signal is supplied to the encoder 10 via the D / A converter 9. Therefore, the camera device supplies the cutout video signal to the main line system and the uncut video signal to the viewfinder 7 as it is, so that the user can see the video area in the future. Therefore, it is possible to improve the convenience when confirming an image that is about to enter from a region that is outside the range.

When the operation unit 18 is operated to enter the type 4 operation mode, the microcomputer 19 sets the cut-out position of each FIFO memory in the aspect ratio conversion circuits 5 and 8 and the predetermined clock in the clock generation circuit 20. Generates a rate write / read clock. Then, in the aspect ratio conversion circuit 5, the FIFO memories 5a and 5b are
For example, the pixel data of the odd line of 572 samples is cut out, respectively, and the aspect ratio conversion circuit 8 reads the pixel data of the odd line of 858 samples from the FIFO memories 11a and 11b, respectively.

Therefore, the aspect ratio conversion circuit 5
Pixel data of 1144 samples is cut out from the 2288 sample pixel data, and the cut-out pixel data is read out for 1H period, so that the number of samples of the pixel data for one line is halved. Then, the aspect ratio conversion circuit 5 cuts out the pixel data so that the aspect ratio of the number of samples becomes 8: 9 in the 1V period, and cuts out the pixel data cut into the field signal having the aspect ratio of 16: 9 in the 1V period. This field signal is read out and supplied to the viewfinder 7 via the D / A converter 6.

Further, the aspect ratio conversion circuit 8 is provided with 228
The pixel data of 1716 samples is cut out from the 8-sample pixel data, and the cut-out pixel data is read out for 1H period, whereby the sample number of the pixel data for one line is set to 3/4. Then, the aspect ratio conversion circuit 8 cuts out the pixel data so that the aspect ratio of the number of samples becomes 4: 3 in the 1V period, and the aspect ratio 4: 3.
The pixel data that has been cut out is read out for 1 V period so as to become the field signal of (1), and this field signal is supplied to the encoder 10 via the D / A converter 9. Therefore, the camera device supplies the cut-out video signal to the main line system and also supplies the cut-out video signal to the viewfinder 7 so that the viewfinder 7 displays an enlarged image of a part of the main line system. It is possible to improve the convenience of the user in the case of performing the manual focus control.

When the operation unit 18 is operated to enter the type 5 operation mode, the microcomputer 19 sets the cut-out position of each FIFO memory in the aspect ratio conversion circuits 5 and 8 and the predetermined clock in the clock generation circuit 20. Generates a rate write / read clock. Then, in the aspect ratio conversion circuit 5, the FIFO memories 5a and 5b are
The pixel data of the odd line of, for example, 1144 samples are respectively cut out from the
For example, pixel data of odd lines of, for example, 1144 samples are cut out from the FIFO memories 11a and 11b, respectively.

Therefore, the aspect ratio conversion circuit 5
1 written by cutting out all 2288 sample pixel data from 2288 sample pixel data
The pixel data for the line is output as it is. That is,
The aspect ratio conversion circuit 5 outputs a field signal having an aspect ratio of 16: 9 in a 1V period, and supplies this field signal to the viewfinder 7 via the D / A converter 6.

Further, the aspect ratio conversion circuit 8 similarly
1 written by cutting out all 2288 sample pixel data from 2288 sample pixel data
The pixel data for the line is output as it is. That is,
The aspect ratio conversion circuit 5 outputs a field signal having an aspect ratio of 16: 9 in a 1V period, and supplies this field signal to the encoder 10 via the D / A converter 9. Therefore, the camera device supplies the image signal of the imaged subject as it is to the main line system, and also supplies the same image signal to the viewfinder 7,
It is convenient for the user to confirm the image of the main line system.

When the operation unit 18 is operated to enter the type 6 operation mode, the microcomputer 19 sets the cutout position of each FIFO memory in the aspect ratio conversion circuits 5 and 8 and the predetermined clock in the clock generation circuit 20. Generates a rate write / read clock. Then, in the aspect ratio conversion circuit 5, the FIFO memories 5a and 5b are
For example, 572 samples of odd line pixel data are cut out, and the aspect ratio conversion circuit 8 cuts out, for example, 1144 samples of odd line pixel data from the FIFO memories 11a and 11b, respectively.

Therefore, the aspect ratio conversion circuit 5
Pixel data of 1144 samples is cut out from the 2288 sample pixel data, and the cut-out pixel data is read out for 1H period, so that the number of samples of the pixel data for one line is halved. Then, the aspect ratio conversion circuit 5 cuts out the pixel data so that the aspect ratio of the number of samples becomes 8: 9 in the 1V period, and cuts out the pixel data cut into the field signal having the aspect ratio of 16: 9 in the 1V period. This field signal is read out and supplied to the viewfinder 7 via the D / A converter 6.

Further, the aspect ratio conversion circuit 8 has 228
By cutting out all the pixel data of 2288 samples from the pixel data of 8 samples, the written pixel data for one line is output as it is. That is, the aspect ratio conversion circuit 5 has an aspect ratio of 16: 1V period.
9 field signal is output, and this field signal is D
It is supplied to the encoder 10 via the / A converter 9.
Therefore, the camera device supplies the image signal of the imaged subject as it is to the main line system and also supplies the cut-out image signal to the viewfinder 7.
An image obtained by enlarging a part of the main line system can be displayed on the viewfinder 7 for convenience of the user when performing the manual focus control.

As described above, in the above camera device, the microcomputer 19 controls the aspect ratio conversion circuits 5 and 8 independently of each other, so that the microcomputer 19 can control the aspect ratio conversion circuits 5 and 8 in accordance with the use condition of the user.
The aspect ratio of the field signal supplied to the main line system and the aspect ratio of the field signal supplied to the viewfinder system can be changed.

Next, a second embodiment according to the present invention will be described. It is to be noted that the same components as those of the above-described embodiment are denoted by the same reference numerals, and detailed description is omitted.

In the camera device according to the second embodiment,
For example, the aspect ratio conversion circuit 5A has an input side F and an output side F connected in parallel, as shown in FIG.
IFO memories 5a-5d and FIFO memories 5a, 5b
D-flip-flop 25 connected to the output side of
A D-flip-flop 26 connected to the output side of the IFO memories 5c and 5d is provided.

The D-flip-flop 25 is the microcomputer 1
It operates when an odd-numbered line read signal IDo of H level (hereinafter abbreviated as read signal IDo) is supplied from 9 and the pixel data read by the FIFO memories 5a and 5b is read by a 36 MHz read clock. Latch based on CK3, so that pixel data of an odd line can be output.

The D-flip-flop 26 is the microcomputer 1
It operates when an even-numbered line read signal IDe of H level (hereinafter abbreviated as read signal IDe) is supplied from 9, and the pixel data read by the FIFO memories 5c and 5d is read by a 36 MHz read clock. Latch based on CK3, whereby pixel data of even lines can be output. The microcomputer 19 outputs the L-level read signal IDe when outputting the H-level read signal IDo, and outputs the H-level read signal IDe when outputting the L-level read signal IDo. ing.

That is, the aspect ratio conversion circuit 5A is
By latching the D-flip-flops 25 and 26 based on a predetermined clock and reading the pixel data, the pixel data can be read at accurate timing.

In other words, the FIFO memories 5a and 5b
Is FIFO via D-flip-flops 25 and 26
By connecting to the memories 5c and 5d, it is possible to read out the pixel data of the odd lines without being affected by the load generated when the pixel data of the even memories are writing to the FIFO memories 5c and 5d.

Next, a third embodiment according to the present invention will be described. It is to be noted that the same components as those of the above-described embodiment are denoted by the same reference numerals, and detailed description is omitted.

In the camera device according to the third embodiment,
The aspect ratio conversion circuit 5B has an input side F and an output side F connected in parallel, as shown in FIG. 5, for example.
IFO memories 5a-5d and FIFO memories 5a, 5b
And a buffer 36 connected to the output side of the FIFO memories 5c and 5d.

The buffer 35 operates when the read signal IDo of H level is supplied from the microcomputer 19, and synchronizes the pixel data read by the FIFO memories 5a and 5b with the read clock CK3 of 36 MHz. Then, the pixel data of the odd line can be output.

The buffer 36 operates when the read signal IDe of H level is supplied from the microcomputer 19, and synchronizes the pixel data read by the FIFO memories 5c and 5d with the read clock CK3 of 36 MHz. Then, the pixel data of even lines can be output. Note that the microcomputer 19 outputs the L-level read signal IDo when outputting the H-level read signal IDo.
When the e signal is output and the L-level read signal IDo is output, the H-level read signal IDe is output.

Then, the aspect ratio conversion circuit 5B can read pixel data at accurate timing by reading pixel data in synchronization with a predetermined clock by the buffers 35 and 36.

In other words, FIFO memories 5a and 5b
Through the buffers 35 and 36, the FIFO memory 5c,
By connecting with the 5d, the FIFO memories 5c, 5
It is possible to read the pixel data of the odd lines without being affected by the load generated when d is writing the pixel data of the even lines.

In the above-described embodiment, the buffer memory used in the aspect ratio conversion circuits 5 and 8 has been described by taking a FIFO memory as an example, but the present invention is not limited to this. Of course, any buffer memory that writes / reads data based on the embedded clock and the read clock may be used.

[0076]

According to the camera device of the present invention, the image pickup signal having the first aspect ratio and the second portion obtained by cutting a part in the horizontal direction from the first aspect ratio are output from the storage means.
By selectively reading out the image pickup signal of the aspect ratio and supplying the image pickup signal of the first or second aspect ratio to the display means, the user can, for example, all or one of the images displayed on the display means. It is possible to easily perform, for example, manual focus control while confirming the subject image of the portion, and it is possible to easily confirm, for example, an image that is about to enter from an area outside the image area to be recorded.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a camera device to which the present invention is applied.

FIG. 2 is a diagram illustrating clipping of pixel data and group delay in an aspect ratio conversion circuit of the camera device.

FIG. 3 is a diagram illustrating a specific example of aspect ratio conversion in the aspect ratio conversion circuit.

FIG. 4 is a block diagram showing a configuration of an aspect ratio conversion circuit according to another embodiment.

FIG. 5 is a block diagram showing a configuration of an aspect ratio conversion circuit according to another embodiment.

[Explanation of reference numerals] 1R, 1G, 1B CCD image sensor, 5, 8 aspect ratio conversion circuit, 7 viewfinder, 19 microcomputer, 20 clock generation circuit

Claims (1)

[Claims] 1. A first method based on an image pickup signal from a subject.
Image pickup means for generating an image pickup signal having an aspect ratio, storage means for storing the image pickup signal having the first aspect ratio, image pickup signal having the first aspect ratio and the first aspect ratio from the storage means Control means for selectively reading out the image pickup signal of the second aspect ratio, which is cut out in a more horizontal direction, and display means for displaying a subject image based on the image pickup signal read out from the storage means. A camera device comprising.