JPH09284340A - Method for controlling communication and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication control device where a frame transferred by means of a communication line is efficiently stored in a buffer memory. SOLUTION: The communication controller 17a is constituted by adding the buffer memory 22, a buffer memory control part 21 dividing the null area of the buffer memory 22 into plural blocks, a reception block number detecting circuit 24 detecting the number of the blocks required for storing the received frame and a line control part 23 storing the received frame in the buffer memory. The reception block number detecting circuit 24 detects the number of the blocks required for storing the frame from header information which is added in the received frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control technique for efficiently storing frames having various frame lengths transferred using a communication network in a buffer memory.

[0002]

2. Description of the Related Art The development of data communication technology in LAN (regional communication network) and WAN (wide area communication network) has been remarkable with the recent trend of multimedia. In particular, the amount of communication data is increasing, and accordingly, the communication speed is required to be increased. In the conventional data communication technique, a transmitting terminal divides data to be transmitted into a plurality of blocks, and forms a frame by combining each division element and information including information necessary for data reconstruction. Each frame thus created is sent to the communication network.

The receiving terminal receives the transferred frame, and this frame is temporarily stored in the buffer memory. A communication control technique using this type of buffer memory is described in JP-A-02-310649. In the communication control technique described in the above publication, the header portion and the data portion of the received frame are separated and stored in the header buffer memory and the data buffer memory. At this time, in the line control unit that controls the communication line, a relatively large fixed buffer memory area is set so that a frame having a long data length can be stored. Alternatively, multiple buffer memories with small fixed lengths may be provided. At this time, if the long data part cannot be stored in one buffer memory, the buffer memory chain is executed.

[0004]

However, in the prior art described in the above publication, when the data portion in the received frame is stored in the buffer memory, the data is stored in the empty buffer memory address regardless of the length of the data. Therefore, there is a problem that the buffer memory is wasted when a frame having a short data portion is received. On the other hand, when a frame having a data portion of long data is received and it cannot be stored in the empty area of one buffer memory, the empty area address of the buffer memory is read again from the buffer information and the buffer chain operation is executed. Therefore, there is a problem in that the reception processing performance is deteriorated.

An object of the present invention is to perform communication for efficient reception by effectively utilizing the empty area of the buffer memory without waste even when the data portion of the received frame has various lengths. It is to provide a control method and apparatus.

[0006]

SUMMARY OF THE INVENTION The present invention provides a communication control method for solving the above problems. This communication control method
A communication control method in a communication device, comprising: a buffer memory for storing frame information including at least one data block; and a control means for controlling storage in the buffer memory, wherein the control means is the buffer memory. Detecting a free area and dividing the detected free area into a plurality of areas; specifying the number of data blocks that can be stored in the free area of the buffer memory from the frame information; and Storing the data block in the corresponding divided area of the buffer memory.

The present invention also provides a communication control device that solves the above problems. The communication control device detects and detects a receiving unit that receives frame information including at least one data block, a buffer memory that stores a data block included in the received frame information, and an empty area of the buffer memory. Corresponding to a block dividing means for dividing an empty area into a plurality of areas, a block number specifying means for specifying the number of data blocks that can be stored in the buffer memory from the received frame information, and a block number specified by the block number specifying means. Data storage means for storing the data block in the divided area of the buffer memory.

It is preferable that the apparatus further comprises means for converting the number of data blocks included in the received frame information into an integral multiple of each divided area of the buffer memory and adding the converted number to the frame information.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a data communication terminal according to an embodiment of the present invention. In this data communication terminal 1, a central processing unit (hereinafter CP
U) 11 and a main memory device (hereinafter referred to as MEM) 12 via a system bus 13 as a bus interface device (hereinafter referred to as BI).
U) 14. A bus interface adapter (hereinafter referred to as BIA) 15 is connected to the BIU 14, and further, the BIA 15 and a communication control device (hereinafter referred to as C
The CUs 17a to 17d are connected by the IO bus 16.

The MEM 12 is for storing transmission / reception data, and the CPU 11 includes a function of controlling storage of frames received by the CCUs 17a to 17d in the MEM 12 and transmission of transmission data stored in the MEM 12 to the CCUs 17a to 17d. I'm out.

FIG. 2 is a block diagram of the CCU 17a according to this embodiment. The CCU 17a includes a microprocessor unit (hereinafter referred to as MPU) 25, a buffer memory 22 functioning as a receiving buffer, a buffer memory control unit 21 having a block dividing unit, a line control unit 23 having a receiving block storing unit, and a receiving block number detecting unit. It is configured to include a reception block number detection circuit 24 having.

The buffer memory control unit 21 detects an empty area of the buffer memory 22 at the time of starting up the data communication terminal 1 and divides it into a plurality of blocks, each time a frame is received.
It holds information about the size of the remaining free area (for example, the number of blocks in the free area and their addresses). The MPU 25 controls the processing of each component of the CCU 17a. The configuration of the CCU 17a is the same for the other communication control devices CCUs 17b to 17d. Hereinafter, examples according to the above modes will be described.

(First Embodiment) FIG. 3 shows a frame structure when this embodiment is applied to a high-level transmission control system (HDLC). Control field 3 of each frame
1 includes a block number information field 32 indicating the number of blocks required to store the frame in the buffer memory.

First, when the CCU 17a is started up, the buffer memory control unit 21 defines the number of bytes of one block, here, for example, 64 bytes. This definition must be the same in the receiving and sending CCUs.

When the data communication terminal 1 is started up, the buffer memory control unit 21 divides an empty area in the buffer memory 22 into units of 64 bytes, which is one block size, and sets the number of divided blocks in the line control unit 23.

The CCU on the transmitting side sets, in the block number information field 32 in the control field 31 of the frame transmitted by the MPU 25, how many blocks are required to receive all the frames. At this time, the number of blocks to be set is the smallest multiple of 64 bytes that can include the entire frame length.

On the other hand, the CCU on the receiving side is the line control unit 23.
The received block number detection circuit 24 detects the number of blocks required to receive all the frames from the block number information field 32, and sets the free space set by the buffer memory control unit 21 when the data communication terminal 1 is started up. If it is receivable by comparing with the block value of the area, it is sequentially stored in the empty area (divided area) of the buffer memory 22.

When one frame is normally stored in the buffer memory 22, the line control unit 23 causes the buffer memory 22 to operate.
The number of blocks used in the empty area is reported to the buffer memory control unit 21, and the reception task of one frame is ended. The above steps are repeated for the reception of the frame transferred thereafter.

(Second Embodiment) FIG. 4 shows a frame structure when this embodiment is applied to Ethernet.
As in the case of the first embodiment, one block has 64 bytes. As shown in FIG. 4, the frame length of the Ethernet frame is described in the information length field 41.

At the time of receiving a frame having such a configuration, the reception block number detection circuit 24 in the line control unit 23
Reads the number of blocks required to receive all the frames from the information length field 41 and calculates the minimum number of blocks that can include this frame. If this frame is receivable by comparing the calculated number of blocks with the block numerical value set in the buffer memory control unit 21 set when the data terminal device 1 is started up, the free area of the buffer memory 22 is sequentially To store.

When one frame is normally stored in the buffer memory 22, the line control unit 23 causes the buffer memory 22 to operate.
It reports to the buffer memory control unit 21 how many blocks of the free area are used and ends the reception task. The above processing is repeated for each frame transferred thereafter on the Ethernet.

For the sake of convenience, the reception processing has been described by taking the CCU 17a as an example, but the other CCUs 17b to 17d are also C.
The same receiving process as that of the CU 17a is performed. Also, one block is described as 64 bytes, but the present invention is not limited to this.

[0023]

As is apparent from the above description, according to the present invention, even if a transmitted frame has various frame lengths, an empty area having a size suitable for receiving this frame is provided. Can be secured in the buffer memory, and the buffer memory can be used without waste. Also,
Since it is not necessary to use a buffer chain, the received frame can be efficiently and reliably stored in the buffer memory.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a data communication terminal which is an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a communication control device according to the present embodiment.

FIG. 3 is a frame configuration diagram in a high level transmission control procedure according to the first embodiment.

FIG. 4 is a frame configuration diagram of an Ethernet according to a second embodiment.

[Explanation of symbols]

 1 Data Communication Terminal 11 Central Processing Unit 12 Memory 13 System Bus 14 Bus Interface Device 15 Bus Interface Adapter 16 IO Bus 17a to 17d Communication Control Device 21 Buffer Memory Control Unit 22 Buffer Memory 23 Line Control Unit 24 Received Block Number Detection Circuit 25 MPU 30 and 40 frames 31 control field 32 block number information field 41 information length

Claims (3)

[Claims] 1. A communication control method in a communication device, comprising: a buffer memory for storing frame information including at least one data block; and a control means for controlling storage in the buffer memory. Detecting the free area of the buffer memory and dividing the detected free area into a plurality of areas; and specifying the number of data blocks that can be stored in the free area of the buffer memory from the frame information, A step of storing the data block in a divided area of the buffer memory corresponding to the number of data blocks that has been processed. 2. A receiving means for receiving frame information including at least one data block, a buffer memory for storing a data block included in the received frame information, a free area of the buffer memory and a detected free space. Block division means for dividing an area into a plurality of areas, block number specification means for specifying the number of data blocks that can be stored in the buffer memory from the received frame information, and block number specification means for specifying the number of blocks A communication control device comprising: a data storage unit that stores the data block in a divided area of the buffer memory. 3. A unit for converting the number of blocks of a data block included in the received frame information into an integral multiple of each divided area of the buffer memory and adding the converted number to the frame information. The communication control device described.