JPH09284267A - Change timing detection circuit and bit phase synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect a change timing of received data sufficiently even when a circuit element having a high speed leading or trailing performance is not employed in the case of reception of even a high speed digital signal. SOLUTION: A sampled output signal D31 from a D flip-flop circuit DFF31 based on a clock CLK2 is given to a DFF32. A sampled output signal D32 from a D flip-flop circuit DFF32 receiving the sample output signal D31 based on a clock CLK1 is given to a DFF33. A sampled output signal D33 from a D flip-flop circuit DFF33 receiving the sample output signal D32 based on a clock CLK0 is given to a CLK0 system synchronization circuit 1. A phase difference of 2T/3 is in existence between the sample output signals D31 and D32 and a phase difference of 2T/3 is in existence between the sample output signals D32 and D33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a change timing detecting circuit and a bit phase synchronizing circuit, and is a circuit suitable for a high speed data receiving circuit, for example.

[0002]

2. Description of the Related Art In recent years, construction of a high-speed digital communication system at a transmission rate of 50 Mbit / s or more has been advanced. In such a high-speed receiving apparatus for a digital communication system, a synchronizing circuit for detecting a change in a received signal at high speed and synchronizing the signals is required. First, a circuit for achieving bit synchronization is required in this synchronizing circuit, and further, a circuit for detecting a change point of received data is required as a pre-stage for achieving bit synchronization.

Therefore, FIG. 2 shows a conventional change point detection circuit for input data by a three-phase clock. FIG.
3 is an operation timing chart of the change point detection circuit of FIG. 2. The received data (DATA) is given to the D flip-flop circuits DFF11, DFF21, DFF31.
The three-phase clocks CLK0 to CLK2 are three-phase clocks that are phase-shifted by one pulse width (d) of the reception data as shown in FIGS.

The D flip-flop circuit DFF11 sample-outputs (latch-outputs) the received data at the clock CLK0 and supplies the sample output signal D11 (e) to the D-flip-flop circuit DFF13 at the next stage. The D flip-flop circuit DFF13 samples again with the clock CLK0 and outputs the sample output signal D13 (f) to CLK0.
It is given to the system synchronization circuit 1. Where the sample output signal D1
The phase difference between 1 (e) and the sample output signal D13 (f) is one clock length T.

The D flip-flop circuit DFF21
Outputs a sample output (latch output) of the received data at the clock CLK1 (b) and supplies the sample output signal D21 (g) to the D flip-flop circuit DFF23 at the next stage.
This D flip-flop circuit DFF23 has a clock C
In order to change the phase of LK0, sampling is performed again with CLK0 and the sample output signal D23 (h) is given to the CLK0 system synchronizing circuit 1. Here, the sample output signal D21
The phase difference between (g) and the sample output signal D23 (h) is 2/3 of one clock length T.

Further, a D flip-flop circuit DFF31
Outputs a sample output (latch output) of the received data with the clock CLK2 (c) and supplies the sample output signal D31 (i) to the D flip-flop circuit DFF33 of the next stage.
This D flip-flop circuit DFF33 has a clock C
In order to change the phase of LK0, sampling is performed again with CLK0, and the sample output signal D33 (j) is given to the CLK0 system synchronizing circuit 1. Here, the sample output signal D31
The phase difference between (i) and the sample output signal D33 (j) is 1/3 of one clock length T.

The CLK0 system synchronizing circuit 1 has a sample output signal D13 (f), a sample output signal D23 (h) and a sample output signal D33 (j) thus obtained.
Judging from the above, the sample output signal D13 (f) is low level, the sample output signal D23 (h) is high level, and the sample output signal D33 (j) is high level. The change point is detected because there is a level change between the low level of) and the high level of the sample output signal D23 (h).

[0008]

However, the sample output signal D31 (i) and the sample output signal D33 are not provided.
Since the phase difference with (j) is 1/3 of one clock length T, if the operation rising speed of the D flip-flop circuit DFF33 is not fast enough, the D flip-flop circuit DFF33 clocks the input data. It becomes impossible to sample at CLK0. For example, 50MHz
When operating with the clock of, the time of T / 3 is about 0.006 μsec, and D flip-flop circuits that operate at such a high speed are few in general purpose and have high performance. It is necessary to adopt a flip-flop circuit, which is not easy to realize.

From the above, a change timing detecting circuit and a bit phase for sufficiently detecting the change timing of received data without using a circuit element having a high-speed rising performance or a falling performance even when receiving a high-speed digital signal. Realization of a synchronous circuit is required.

[0010]

Accordingly, a first aspect of the present invention provides
In a change timing detection circuit that detects the change timing of received data, the pulse width of the received data is divided into n (n
Is a flip-flop circuit connected in n rows × n columns using a phase-shifted multiphase clock
Sampling means for sampling the received data and outputting an n-phase sample signal, and change timing determination means for determining the change timing of the received data from the relative relationship between the signal levels of these n-phase sample output signals. Prepare

In such a configuration, since the flip-flop circuits in each row are connected to columns 1 to n, when the pulse width of the received data is T, the phase difference between the sample output signals between the flip-flops is ( n-1) .T / n or more. For example, if n = 3, 2 · T
It can be / 3 or more. Therefore, compared to the conventional
The performance with respect to the rising or falling response speed of the flip-flops in each row will be relaxed.

The bit phase synchronization circuit of the second invention is any one of the n-phase clocks based on the change timing of the received data detected by the conversion timing detection circuit of the first invention. The clock and the received data are synchronized in bit phase.

With such a configuration, even when a high-speed digital signal is received and the bit phase is synchronized, the bit phase synchronization can be easily achieved without the flip-flop circuit used for detecting the change timing having high performance. You can

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. Therefore, in the present embodiment, as a function in the receiving circuit of the digital transmission device, when the change point position of the received signal is detected by multi-phase sampling (n-phase sampling of three or more phases), the D flip-flops adjacent The phase difference of the clocks input to (n-
1) Insert a D flip-flop circuit having a clock length of n, and (n-1) between all D flip-flops.
It is configured such that operation can be performed with a time difference of / n clock length or less.

"First Embodiment": FIG. 1 is a functional block diagram of a change point detection circuit according to the first embodiment. In FIG. 1, this conversion point detection circuit is composed of D flip-flop circuits DFF11, DFF13, DFF21, DFF.
23, DFF31 and DFF33, and an insertion D flip-flop circuit DFF2.

The characteristic feature of this change point detection circuit is that it includes an insertion D flip-flop circuit DFF. This insertion D flip-flop circuit DFF is
Flip-flop circuits DFF12, DFF22, DFF
It is composed of 32 parts.

The D flip-flop circuit DFF12 is D
The sample output signal D11 from the flip-flop circuit DFF11 is sampled using the clock CLK0, and the sample output signal D12 is given to the D flip-flop circuit DFF13 at the final stage. Further, the D flip-flop circuit DFF22 is a D flip-flop circuit D
The sample output signal D21 from the FF21 is sampled using the clock CLK0, and the sample output signal D22 is sampled at the final stage D flip-flop circuit DFF2.
Give to 3.

Further, the D flip-flop circuit DFF32
Uses the clock CLK1 to sample the sample output signal D31 from the D flip-flop circuit DFF31, and outputs this sample output signal D32 to the D of the final stage.
It is given to the flip-flop circuit DFF33.

In FIG. 1, the D flip-flop circuit D
FF11 to DFF13 are D flip-flop circuits in the first row, and D flip-flop circuits DFF21 to DFF
23 is a D flip-flop circuit in the second row, and D flip-flop circuits DFF31 to DFF33 are D in the third row.
It is a flip-flop circuit. Further, the D flip-flop circuits DFF11 to DFF31 are the D flip-flop circuits in the first column, and the D flip-flop circuit DFF12
To DFF32 are D flip-flop circuits in the second column, and D flip-flop circuits DFF13 to DFF33 are D flip-flop circuits in the third column. Three-phase sample output signals for detecting a change point (change timing) are obtained by these D flip-flop circuits connected in 3 rows × 3 columns.

(Operation): Next, the operation of the change point detection circuit of FIG. 1 will be described with reference to the operation timing chart of FIG. First, when the received data (d) is input to the D flip-flop circuits DFF11, 21, and 31, the clock CLK0 is input to the D flip-flop circuit DFF11.
The sample output signal D is sampled by (a).
11 (e) is given to the D flip-flop circuit DFF12. In this D flip-flop circuit DFF12,
Clock CLK for sample output signal D11 (e)
Is sampled using 0 and the sample output signal D1
2 (f) is given to the D flip-flop circuit DFF13. In the D flip-flop circuit DFF13, the clock CLK0 is applied to the sample output signal D12 (f).
Is sampled using the sample output signal D13
(G) is given to the CLK0 system synchronizing circuit 1.

Here, the sample output signal D11
The phase difference between (e), the sample output signal D12 (f), and the sample output signal D13 (g) is 1 clock length T, respectively.

Further, the D flip-flop circuit DFF21
Then, the sample output is performed by the clock CLK1 (b), and the sample output signal D21 (h) is given to the D flip-flop circuit DFF22. In this D flip-flop circuit DFF22, the sample output signal D21 (h)
Is sampled using the clock CLK0, and the sample output signal D22 (i) is given to the D flip-flop circuit DFF23. In the D flip-flop circuit DFF23, the sample output signal D22 (i)
Is sampled using the clock CLK0, and the sample output signal D23 (j) is given to the CLK0 system synchronizing circuit 1.

Here, the sample output signal D21
Between (h) and the sample output signal D22 (i) is 2.
Phase difference of T / 3, sample output signal D22 (i)
And the sample output signal D23 (j) has a phase difference of 1
The clock length is T.

Further, the D flip-flop circuit DFF31
Then, the sample output is performed by the clock CLK2 (c), and the sample output signal D31 (k) is given to the D flip-flop circuit DFF32. In the D flip-flop circuit DFF32, the sample output signal D31 (k)
Is sampled using the clock CLK1 (b), and the sample output signal D32 (l) is given to the D flip-flop circuit DFF33. In this D flip-flop circuit DFF33, the sample output signal D32
The sample output signal D33 (m) is sampled using the clock CLK0 (a) for
It is given to the 0-system synchronizing circuit 1.

Here, the sample output signal D31
(K) and the sample output signal D32 (l) are 2 ·
Phase difference of T / 3, sample output signal D32 (l)
And the phase difference between the sample output signal D33 (m) is 2
・ T / 3. The phase difference between the D flip-flop circuits DFF surrounded by the dotted line in FIG. 1 is 2 · T / 3.

Thus, the D flip-flop circuit DF
By inserting F in one stage, the phase difference is improved from the conventional 1/3 · T to 2/3 · T, so that the rising operation speed required for the D flip-flop can be selected slow.

In the CLK0 system synchronizing circuit 1, the sample output signal D13 (g) and the sample output signal D23 are used.
The conversion point is detected from (j) and the sample output signal D33 (m). Specifically, the sample output signal D13
(G) is at a high level and the sample output signal D23 (j)
Is low level and the sample output signal D33 (m) is low level, the sample output signal D13 (g)
It is detected that there is a change point of received data between the sample output signal D23 (j) and the sample output signal D23 (j).

When the change point is detected in this way, C
In the LK0 system synchronization circuit 1, the master clock is used as the clock CK0 from the detection result, the phase difference between the master clock CK0 and the data is detected, and the synchronization data obtained by delaying the phase difference data and the synchronization clock are detected. Is output. Alternatively, a clock having an optimum phase of any one of the clocks CK0 to CK2 and synchronous data may be output. With such a configuration, it can be realized as a bit phase synchronizing circuit.

(Effects of the first embodiment of the present invention):
According to the first embodiment of the present invention described above, since the D flip-flop circuits DFF12, 22 and 32 are inserted and sampled by the clock, the phase difference between the D flip-flop circuits is reduced to 2 /. Therefore, the change point detection circuit can be constructed without using the D flip-flop circuit which can be extended up to 3 · T and whose rising operation is fast.

[Second Embodiment]: In the second embodiment, a change point detection circuit for detecting a change point of received data by a multi-phase clock of four or more phases is configured.

Therefore, FIG. 5 is a functional block diagram of the change point detection circuit based on the n-phase clock. In FIG. 5, the change point detection circuit includes D flip-flop circuits DFF11 to DFF11.
DFFn1 and insertion D flip-flop circuit DFF3
And the D flip-flop circuits DFF1n to DFFnn
And a CLK1 system synchronizing circuit 1 '. The inserted D flip-flop circuit DFF3 includes the D flip-flop circuits DFF12 to DFFn2 to DFF1 (n-1).
To DFFn (n-1).

D flip-flop circuits DFF11 to DF
The function of Fnn is the same, and the clock CLK given to each of them is given any one of CLK1 to CLKn to perform sample output.

(Operation): Next, the operation of the change point detection circuit of FIG. 5 will be described with reference to the operation timing chart of FIG. First, the received data (e) is given to the D flip-flop circuits DFF11 to DFFn1. The D flip-flop circuit DFF11 samples and outputs the received data (e) by the clock CLK1 (a),
The sample output signal D11 (f) is given to the D flip-flop circuit DFF12. D flip-flop circuit DFF
12 samples the sample output signal D11 (f) by the clock CLK1 (a) and outputs the sample output signal D12 (g) to the next D flip-flop circuit D.
Give to FF13.

By repeating this, the D flip-flop circuit DFF1 (n-1) samples and outputs the sample output signal from the preceding stage using the clock CLK1 (a), and outputs the sample output signal D1 (n-1). ) (H) is given to the final stage D flip-flop circuit DFF1n. This D
The flip-flop circuit DFF1n receives the clock CLK1 (a) for the sample output signal D1 (n-1) (h).
To sample and output the sample output signal D1n (i)
To the clock CLK1 system synchronizing circuit 1 '.

In this way, the phase difference between the DFFs in the D flip-flop circuits DFF11 to DFF1n is T.
Becomes This is a D flip-flop circuit DFF11-
This is because all of them are sampled by the clock CLK1 (a) in the DFF1n.

The D flip-flop circuit DFF21
Performs sample output using the clock CLK2 (b), and supplies this sample output signal D21 (j) to the D flip-flop circuit DFF22. The D flip-flop circuit DFF22 samples and outputs using the clock CLK1 (a), and outputs the sample output signal D22.
(K) is given to the next D flip-flop circuit DFF23. By repeating this, the D flip-flop circuit DFF2
(N-1) outputs the sample output signal D2 (n-1) (l) to the final stage D flip-flop circuit by sampling the sample output signal from the previous stage using the clock CLK1 (a). It is given to DFF2n. The D flip-flop circuit DFF2n is provided with a sample output signal D2 (n
-1) (l) is sampled using the clock CLK1 (a), and the sample output signal D2n (m) is given to the clock CLK1 system synchronization circuit 1 '.

In this way, the phase difference between DFFs in the D flip-flop circuits DFF21 to DFF2n can be secured to be (n-1) .T / n or more. Further, the D flip-flop circuit DFF (n-1) 1 outputs a sample using the clock CLK (n-1) (c), and outputs the sample output signal D (n-1) 1 (n) to the D flip-flop. Circuit DFF (n-1) 2.

This D flip-flop circuit DFF (n-
1) 2 performs sample output using the clock CLK (n-2), and outputs the sample output signal D (n-1) 2
(O) is the next D flip-flop circuit DFF (n-1)
Give to 3. By repeating this, the D flip-flop circuit DFF (n-1) (n-1) performs sample output using the clock CLK1 (a) with respect to the sample output signal from the previous stage, and outputs the sample output signal D (n -1) (n-
1) (p) is the final stage D flip-flop circuit DFF
(N-1) Give to n. This D flip-flop circuit D
FF (n-1) n is the sample output signal D (n-1)
(N-1) (p) is sampled using the clock CLK1 (a), and the sample output signal D (n-1) n
(Q) is given to the clock CLK1 system synchronizing circuit 1 '.

In this way, the DF in the D flip-flop circuits DFF (n-1) 1 to DFF (n-1) n.
It is possible to secure a phase difference between F of (n-1) · T / n or more.

Furthermore, the final stage D flip-flop circuit D
The FFn1 samples and outputs using the clock CLKn (d), and supplies the sample output signal Dn1 (r) to the D flip-flop circuit DFFn2. The D flip-flop circuit DFFn2 has a clock CLK (n-1).
(C) is used for sample output, and this sample output signal Dn2 (s) is output to the next D flip-flop circuit DFF.
Give to n3. By repeating this, the D flip-flop circuit DFFn (n-1) outputs the sample output signal Dn (n-1) (t) by sampling the sample output signal from the previous stage using the clock CLK2 (b). ) Is given to the final stage D flip-flop circuit DFFnn. The D flip-flop circuit DFFnn receives the clock CLK1 with respect to the sample output signal Dn (n-1) (t).
Sampling using (a), sample output signal Dnn
(U) is given to the clock CLK1 system synchronizing circuit 1 '.

In this way, the phase difference between the DFFs in the D flip-flop circuits DFFn1 to DFFnn can be secured to be (n-1) .T / n or more. FIG.
The phase difference between the D flip-flop circuits DFF surrounded by the dotted line is (n-1) · T / n.

In the CLK1 system synchronizing circuit 1 ', the sample output signal D1n (i) and the sample output signal D2n (m) are used.
The conversion point of the received data (e) is detected from the sample output signal D (n-1) n (q) and the sample output signal Dnn (u).

When the change point is detected in this way, C
In the LK1 system synchronization circuit 1 ′, the master clock is used as the clock CK1 from the detection result, the phase difference between the master clock CK1 and the data is detected, and the synchronization data obtained by delaying the phase difference data and the synchronization clock are detected. Is output. Alternatively, a clock having an optimum phase of any one of the clocks CK1 to n and the synchronization data may be output. With such a configuration, it can be realized as a bit phase synchronizing circuit.

(Effects of the second embodiment of the present invention):
According to the second embodiment of the present invention described above, the (n−2) -stage insertion D flip-flop circuit D is driven by the phase-shifted n-phase clock that divides the pulse width of the reception data by n.
By including the FF ′, the phase difference between the D flip-flop circuits can be extended to (n−1) · T / n, and the change point detection circuit can be used without using the D flip-flop circuit having a fast rising operation. You can now configure.

(Other Embodiments) (1) In the change point (change timing) detection circuit and bit phase synchronization circuit of the above embodiments, the multiphase clocks CLK1 to CLKn are used.
It is also possible to generate a reference clock from the received data by using a PLL circuit or the like, and generate the reference clock by dividing the reference clock.

(2) Further, the change point detection circuit and the bit phase synchronization circuit of the above-mentioned embodiment are not only applied to continuous high-speed digital data reception, for example, ATM communication system, but also burst data reception. Can be fully dealt with.

[0047]

As described above, according to the present invention, the received data is sampled by the flip-flop circuit connected in n rows × n columns by using the phase-shifted multiphase clocks, and these n
Since the change timing of the received data is determined from the relative relationship of each signal level from the phase sample output signal,
Even when receiving a high-speed digital signal, it is possible to realize a change timing detection circuit and a bit phase synchronization circuit that sufficiently detect the change timing of received data without using a circuit element having high-speed rising performance or falling performance.

[Brief description of drawings]

FIG. 1 is a functional configuration diagram of a change point detection circuit according to a first embodiment of this invention.

FIG. 2 is a functional configuration diagram of a conventional change point detection circuit.

FIG. 3 is an operation timing chart of a conventional change point detection circuit.

FIG. 4 is an operation timing chart of the change point detection circuit according to the first embodiment.

FIG. 5 is a functional configuration diagram of a change point detection circuit according to a second embodiment.

FIG. 6 is an operation timing chart of the change point detection circuit according to the second embodiment.

[Explanation of symbols]

DFF11 to 33 ... D flip-flop circuit, 1 ... Clock CLK0 system synchronizing circuit, CLK0, 1, 2 ... Clock.

Claims (2)

[Claims] 1. A change timing detection circuit for detecting a change timing of received data, wherein a phase-shifted multi-phase clock that divides a pulse width of the received data into n (n is an integer of 3 or more) is used, Row xn
A flip-flop circuit connected to the column samples the reception data to output an n-phase sample signal, and a sampling means for outputting the n-phase sample output signal from the relative relationship between the respective signal levels. A change timing detection circuit, comprising: a change timing determination means for determining a change timing. 2. Based on the change timing of the reception data detected by the change timing detection circuit according to claim 1,
A bit phase synchronizing circuit, wherein any one of the n-phase clocks is bit-phase synchronized with the received data.