JPH09284052A - Phase difference signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately set a phase difference of an output signal. SOLUTION: A digital synthesizer circuit 6 generates two signals with the same frequency but different phases based on entered setting data. PLL circuits 7, 8 corresponding to respective output signals of the digital synthesizer circuit 6 generate signals whose phases are locked to the phases of respective output signals. That is, a phase difference signal with a low frequency is generated first in the digital synthesizer circuit 6, and the phase difference signals are generated by the corresponding the PLL circuits 7, 8. Thus, the phase and the frequency of output signals are revised simply with high accuracy without increasing the circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase difference signal generator, and more particularly to a phase difference signal generator used for a modulator / demodulator such as a quadrature amplitude modulator.

[0002]

2. Description of the Related Art As a conventional phase difference signal generator, for example, there is one described in Japanese Patent Laid-Open No. 5-191466. This is, as shown in FIG. 4, a quadrature phase comparator 304 that detects a deviation from a quadrature state of the phase difference between the two signals, the input signal and the output signal of the voltage controlled oscillator 307,
A DC amplifier 305 that amplifies the output signal of the quadrature phase comparator 304, and a low-pass filter 306 that removes high frequency components from the output signal of the DC amplifier 305 and outputs only the phase difference component of the two signals. Having, this low-pass filter 306
Is used as the control voltage of the voltage controlled oscillator 307. That is, P that holds the phase difference between the two signals at 90 degrees
An LL circuit (Phase Locked Loop) is configured. The quadrature comparator 304 has a Gilbert
An analog multiplier such as a multiplier is used.
This phase difference signal generator is referred to as a first conventional phase difference signal generator.

Further, as another conventional phase difference signal generator, Japanese Patent Laid-Open No. 2-312320 or Japanese Patent Laid-Open No. 3-60 is known.
There is one described in Japanese Patent Publication No. 501. The phase difference signal generators described in these publications, as shown in FIG. 5, divide a reference signal into quadrature components and then multiply each component by an output signal of a quadrature digital synthesizer. Thus, the phase modulator is configured to generate an arbitrary phase difference signal. This phase difference signal generator is referred to as a second conventional phase difference signal generator.

[0004]

In the above-mentioned first conventional phase difference signal generator, an analog multiplier is used as a quadrature phase comparator to determine the phase of two signals, an input signal and an output signal of the voltage controlled oscillator. Since the comparison is performed, the output signal of the quadrature comparator becomes a high frequency signal, and when the signal from the low pass filter circuit disappears, the PLL circuit does not lock. That is, when the frequency of the input signal is changed, the change width is increased or the free running frequency of the voltage controlled oscillator is far from the operating frequency of the PLL.
There is a drawback that the L circuit does not lock.

Further, in the above-mentioned first conventional phase difference signal generator, if the frequency difference between the two signals is large, the bandwidth of the low-pass filter is widened so that the PLL circuit can be locked. In this case, the characteristics of the PLL circuit are deteriorated and the interfering signal removal performance is deteriorated, so that the noise due to the high frequency component from the analog multiplier is increased and the jitter is increased.

Further, in the above-mentioned first conventional phase difference signal generator, since the quadrature phase comparator is used as the phase comparator, there is a drawback that an arbitrary phase difference signal other than 90 degrees cannot be generated. .

On the other hand, in the above-mentioned second conventional phase difference signal generator, the analog delay device is used as the quadrature distributor of the phase modulator of the reference signal, and the phase changes depending on the characteristic of the circuit element of the delay device. Then, there is a drawback that the output signal waveform of the phase modulator is distorted and spurious is generated.

Further, the above-mentioned second conventional phase difference signal generator requires a clock four times as high as the reference frequency,
A delay device and a multiplier that operate at high speed are required. Therefore, if the delay device and the multiplier are realized by a digital circuit, there is a drawback that the circuit scale becomes large.

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and its object is to provide a phase difference signal generator capable of appropriately setting the phase difference of output signals. .

Another object of the present invention is to provide a phase difference signal generator which can easily change the phase and frequency of an output signal with high accuracy without increasing the circuit scale. .

[0011]

A phase difference signal generator according to the present invention receives N different initial values and a common increase value as input, and outputs N values obtained by sequentially adding the increase value to the initial value. (N is an integer of 2 or more) and this N
N counters provided corresponding to the respective counters and converting the outputs from the corresponding counters into sine wave data and outputting the same, and synchronization with the outputs of the corresponding tables provided corresponding to the N tables. And N phase-locked loop means for respectively generating the generated signals.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the present invention is as follows.

A digital synthesizer circuit for generating two or more signals having different phases but the same frequency based on the input setting data, and a plurality of PLL circuits corresponding to the respective output signals of the digital synthesizer circuit are provided. ,
A signal whose phase is synchronized with the output signal is generated. In the digital synthesizer circuit, a phase difference signal having a low frequency is first generated, and a corresponding PLL circuit generates the phase difference signal.

By implementing the phase comparator of the PLL circuit with a digital circuit, the PLL circuit can be locked even when the frequency change width to be set is increased. Further, by optimizing the synchronous loop of the PLL circuit, it is possible to improve the characteristics of the PLL circuit such as interference signal removal performance. Furthermore, an arbitrary phase difference signal can be generated by using a plurality of independent PLL circuits. Since the analog delay device is not used, the spurious of the voltage controlled oscillator can be reduced. Since the operating frequency of the digital synthesizer circuit is low, the circuit scale can be reduced. By providing the high frequency oscillator inside the PLL circuit, it is possible to generate a signal having a frequency sufficiently higher than the oscillation frequency of the digital synthesizer circuit.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a phase difference signal generator according to the present invention. In the figure, a phase difference signal generator according to an embodiment of the present invention includes a digital synthesizer circuit 6 having a frequency setting data input terminal 4 and phase setting data input terminals 3-1 and 3-2, and the digital synthesizer circuit 6 SIN to be output
The PLL circuit 7 having the wave signal 61 as an input and the PLL circuit 8 having the SIN wave signal 62 as an input are included. The digital synthesizer circuit 6 is provided with a common reset signal input terminal 1, a clock input terminal 2, and a selection signal input terminal 5.

In such a configuration, the initial values input from the phase setting data input terminals 3-1 and 3-2 are held in the registers in the digital synthesizer circuit 6.
The increment value input from the frequency setting data input terminal 4 is also held in the register in the digital synthesizer circuit 6. As a result, the digital synthesizer circuit 6 outputs two SIN wave (sine wave) signals 61 and 62 having the same frequency but different phases.

The PLL circuit 7 receives the SIN wave signal 61 as an input, and has a high-frequency SI phase-synchronized with the SIN wave signal 61.
The N-wave signal 71 is output to the output terminal 9. Similarly, PLL
The circuit 8 receives the SIN wave signal 62 as an input and outputs a high frequency SIN wave signal 81 phase-locked to the SIN wave signal 62 to the output terminal 10.

Here, an example of the internal configuration of the digital synthesizer circuit will be described. FIG. 2 is a block diagram showing a configuration example of the digital synthesizer circuit 6 in FIG. 1, and the same parts as those in FIG. 1 are designated by the same reference numerals.

In the figure, the digital synthesizer circuit 6 includes two initial value registers 13-1 and 13-2 which respectively hold different initial values respectively inputted from the phase setting data input terminals 3-1 and 3-2. , And an increment value register 14 that holds the increment value input from the frequency setting data input terminal 4.

Further, the digital synthesizer circuit 6 is
An address counter 11-1, which receives the contents held in the initial value register 13-1 and the increment value register 14, and a SIN wave table which generates a SIN wave signal 61 in response to the input of the address signal from the address counter 11-1. 12
-1, the initial value register 13-2 and the increment value register 1
Address counter 11-2 that inputs the contents held in 4
And a SIN wave table 12-2 which generates a SIN wave signal 61 in response to the input of the address signal from the address counter 11-2.

Phase setting data input terminals 3-1 and 3-2
May be a common terminal, and a selector may be provided to input to either one of the initial value registers 13-1 and 13-2.

SIN wave tables 12-1 and 12-2
Is a 32-bit output SI for a 32-bit input x
ROM (Read Only) so that Nx is output.
Memory). 32 for input x
A table for outputting the output COSx of bits, that is, C
Obviously, an OS wave table may be used.

Here, the address counters 11-1 and 11-1
The internal configuration of 1-2 will be described. FIG. 3 is a block diagram showing an internal configuration example of the address counter in FIG. 2, and the same portions as those in FIGS. 1 and 2 are indicated by the same reference numerals.

In the figure, the address counter adds a D-type flip-flop (hereinafter referred to as DFF) 32 holding the phase setting data 311 which is an initial value, the output data 312 of this counter and the frequency setting data 310 which is an increment value. Adder 35 and D that holds the output of this adder 35
Selector (SEL) that selectively sends out the holding values of both FF31 and DFF31 and DFF32 according to the selection signal 5.
34 and a DFF 33 that holds the output of this selector 34
It is comprised including.

The reset signal 1 is input to the DFF 32 as a clock. Therefore, the phase setting data 311 is input to the DFF 32 when the reset signal 1 is input, and the same data is held thereafter.

On the other hand, the clock signal 2 is input as a clock to the DFF 31 and the DFF 33. Therefore, at the transition timing (rising or falling) of the clock signal 2, the output of the adder 35 is input and held in the DFF 31, and the output of the selector 34 is input and held in the DFF 33.

The frequency setting data 310 and the output data 312 are all 32-bit data. The selection signal 5 is assumed to be 1-bit data.

In such a configuration, when the reset signal 1 is input at the beginning of the operation of this circuit, the phase setting data 31
1 is held in the DFF 32. At this time, the selector 34
Selects and outputs the value held in the DFF 32 by the selection signal 5.

Next, at the transition timing of the clock signal 2, the output of the selector 34 is held in the DFF 33 and output as output data 312. This output data 312 is
It is added to the frequency setting data 310 in the adder 35. The output of the adder 35 is held in the DFF 31 at the transition timing of the clock signal 2.

The selector 34 selects and outputs the value held in the DFF 32 only in the initial operation of this circuit, and thereafter, the DFF 3
It operates to select and output the held value of 1. Therefore, it is assumed that the selection signal 5 is input as a level for selecting the holding value of the DFF 32 only in the initial stage of operation and thereafter as a level for selecting the holding value of the DFF 31.

As a result, the phase setting data 311 is initially set.
(That is, the initial value) is output as it is, but thereafter, the frequency setting data 310 (that is, the increasing value) is sequentially added to the phase setting data 311, and the phase setting data 311 is output. As described above, in the address counters 11-1 and 11-2,
The value of the frequency setting data 310 is common, but the value of the phase setting data 311 is different, so the initial value output at the first time is different, and the value obtained by sequentially adding the same increment value is output thereafter. Therefore, the address counters 11-1, 11-2
If the output of is input to the SIN wave table, SIN wave data having different phases and the same frequency can be obtained.

In short, in this circuit, different initial values and a common increment value are set from the outside, the increment value is sequentially added to the initial value, and the addition result is converted by the SIN wave table and output. is there.

Returning to FIG. 2, in such a configuration, different initial values are held in the initial value registers 13-1 and 13-2, and these values are stored in the SIN wave signal 61 and the SIN wave signal 6 respectively.
The phase difference from 2 will be determined. In addition, the common increment value is held in the increment value register 14, and this value is SIN.
The frequencies of the wave signal 61 and the SIN wave signal 62 will be determined. In other words, this digital synthesizer circuit 6
The SIN wave signal 61 and the SIN wave signal 62 output from are different in phase depending on the contents held in the initial value registers 13-1 and 13-2 and the increment value register 14 and have the same repetition frequency. Of.

By performing such initialization to the digital synthesizer circuit 6, the phase is different and the frequency is the same according to the reset signal and the clock signal input from the common reset signal input terminal 1 and the clock input terminal 2. It is possible to generate two SIN wave signals.

Referring again to FIG. Each SIN wave signal 6 generated in the digital synthesizer circuit 6
1 and 62 are input to the PLL circuits 7 and 8. PL
Since each of the L circuits 7 and 8 has a phase-locked loop having a voltage-controlled oscillator therein, it can generate a high-frequency SIN wave signal phase-locked with the SIN wave signal input from the digital synthesizer circuit 6. it can.

When the conventional circuit is used, even if it is desired to make the phase difference between the finally output signals 90 degrees, each PL
It is difficult to set the phase difference to 90 degrees correctly due to the difference in the characteristics of the L circuit, but in this circuit, if the optimum initial value is set in consideration of the difference in the characteristics of each PLL circuit, the phase difference can be surely set to 90 degrees.
It can be done once.

In this example, the case of two outputs is shown, but it goes without saying that three or more outputs are possible. In this case, by increasing the number of address counters, SIN wave tables, and PLL circuits, the phase difference between the outputs can be controlled freely.

The digital synthesizer circuit 6 described above can also be realized by an arithmetic circuit or the like. That is,

[Equation 1] Since a series expansion can be performed, a circuit for performing this operation is provided, and i
The calculation may be aborted at about 0 to 4 and the approximate calculation may be performed.

As described above, since the phase comparator of the PLL circuit can be realized by a digital circuit, the PLL can be locked even when the set frequency change width is increased. Moreover, since a plurality of independent PLL circuits are used, an arbitrary phase difference signal can be generated. Further, since the digital multiplication circuit is not necessary, the circuit scale can be reduced. By providing a high frequency oscillator inside the PLL circuit, a signal having a frequency sufficiently higher than the oscillation frequency of the digital synthesizer circuit can be generated.

The present invention can take the following aspects in connection with the description of the claims.

(4) The phase difference signal generator according to any one of claims 1 to 3, wherein the N tables are constituted by ROM.

(5) Instead of the table of N tables, N tables provided corresponding to each of the N counters and converting the outputs from the corresponding counters into cosine wave data and outputting the cosine wave data are output. The phase difference signal generator according to any one of claims 1 to 4, further comprising:

[0044]

As described above, according to the present invention, different initial values and common increment values are set from the outside, the increment values are sequentially added to the initial values, and the addition results are converted in a table and output. By doing so, there is an effect that the circuit scale is not increased, the phase difference can be appropriately set, and the phase and frequency of the output signal can be easily and accurately changed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a phase difference signal generator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a digital synthesizer circuit 6 in FIG.

FIG. 3 is a block diagram showing an internal configuration example of an address counter in FIG.

FIG. 4 is a block diagram showing a configuration of a conventional phase difference signal generator.

FIG. 5 is a block diagram showing a configuration of another conventional phase difference signal generator.

[Explanation of symbols]

 6 Digital synthesizer circuit 7, 8 PLL circuit 11-1, 11-2 Address counter 12-1, 12-2 SIN wave table 13-1, 13-2 Initial value register 14 Increase value register 31-33 DFF 34 Selector 35 Addition vessel

Claims (3)

[Claims] 1. N counters (N is an integer of 2 or more) for inputting mutually different initial values and a common increment value and outputting a value obtained by sequentially adding the increment value to the initial value, and the N counters. N counters provided corresponding to the respective counters and converting the outputs from the corresponding counters into sine wave data and outputting the same, and synchronization with the outputs of the corresponding tables provided corresponding to the N tables. And N phase lock loop means for respectively generating the generated signals. 2. Each of the N counters includes a first holding unit that holds the initial value, an adding unit that adds the output value of the own counter and the increment value, the addition result and the initial value. 2. The phase difference signal generator according to claim 1, further comprising: selecting means for selectively outputting the value and the output of the selecting means is the output value. 3. The N is 2, and the initial value is determined so that the phase difference between the signals respectively generated by the phase locked loop means becomes 90 degrees. Phase difference signal generator.