JPH09283727A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacture which ensure uniformity in etching in the semiconductor device whose contact holes which penetrate a single layer and plural layer interlayer insulating films are formed in the same etching process. SOLUTION: On the bottom side interlayer insulating film 41 of the two layers of interlayer insulating films which are penetrated by contact holes formed in the same etching process, a recessed part 50 is formed, a wiring layer 33 on the bottom side interlayer insulating film is formed at the bottom of the recessed part 50, and on the bottom side interlayer insulating film 41, a top side interlayer insulating film 42 is formed. Then, a contact hole 62, which penetrates the interlayer insulating films 41 and 42 at a part to be energized, and a recessed part contact hole 63 which penetrates the top side interlayer insulating film and reaches the wiring layer 33 on the recessed part 50, are opened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an improved connection method between multi-layer wiring layers in a semiconductor device having multi-layer wiring layers and a method for manufacturing the same.

[0002]

2. Description of the Related Art An example of a plan view of a flash memory having a sub bit line structure is shown in FIG. In this figure, a sub-bit line SBL is branched from a main bit line (not shown) via a contact BC and a selection transistor ST, and the sub-bit line SBL is divided into memory transistors MT1 to MT4.
Is connected. The source SD of MT1 and MT2 is shared, and the source SD is an intermediate wiring ML formed of the same polycide as the sub bit line via the source contact SC.
Is connected to Further, the intermediate wiring ML is connected to the source line SL via the intermediate wiring contact MC. The gate electrode STG of the selection transistor ST is a contact G
It is connected via C to the select gate line STGL.

FIG. 6 is a sectional view taken along the line AA 'of FIG. In FIG. 6, the element isolation insulating film 21 is formed on the surface of the substrate 10.
The gate electrode STG of the select transistor having the polycide structure and the gate electrode MTG1 of the memory transistor MT1 are wired on the element isolation insulating film 21, and the first interlayer insulating film 41 is formed so as to cover them. There is. An intermediate wiring ML having a polycide structure is formed on the first interlayer insulating film 41, and is connected to the source SD of the substrate 10 via the contact SC. Further, a second interlayer insulating film 42 is formed so as to cover the intermediate wiring ML, and a select gate line STGL made of aluminum is formed on the second interlayer insulating film 42, and the gate electrode STG of the select transistor ST is formed. And the contact GC. Further, the source line SL is formed on the second interlayer insulating film 42, and is connected to the intermediate wiring ML via the contact MC.

The source line SL and the intermediate wiring ML are formed by a contact MC penetrating the second interlayer insulating film 42. On the other hand, the connection between the gate electrode STG of the selection transistor and the selection gate line STGL is made by the contact GC penetrating the first interlayer insulating film 41 and the second interlayer insulating film 42. As is clear from this figure, the contact MC is very shallow and the contact GC is deep.

On the other hand, FIG. 7 shows a sectional view taken along the line BB 'of FIG. In FIG. 7, a pair of select transistors ST1 and ST2 are formed on the surface of the substrate 10. The first interlayer insulating film 41 fills the gate electrodes STG1 and STG2 of the pair of select transistors formed of polycide. Further, the second interlayer insulating film 42 is formed on the first interlayer insulating film 41, and the second interlayer insulating film 42 is made of aluminum and has a large area to be connected to the aluminum wiring thereon. The connection part IP is formed. The connection part IP includes selection transistors ST1 and ST.
The two common diffusion layers are connected via a contact BC.

The contact BC is formed by the second interlayer insulating film 4
2 and the first interlayer insulating film 41 to penetrate the diffusion layer DR of the substrate.
Is deeper than the contact GC. Such deep contact BC, shallow contact M
The C and slightly deep contacts GC are formed by forming contact holes by etching in the same step and then filling the contact holes with tungsten or the like.
Therefore, the etching condition is adjusted to the deepest contact hole.

[0007]

However, in this etching, for example, the contact MC
Will be over-etched. For example, there is a case where over-etching of about 500% is performed on the shallow contact MC, which causes striations on the contact side wall and causes an unfavorable shape inside the contact. It has a bad effect such as a decrease in yield.

As a countermeasure against this, it is conceivable to increase the thickness of the second interlayer insulating film 42 to relatively reduce the depth ratio between the shallowest contact and the deepest contact.
In this case, the absolute depth of the deepest contact is increased, which again adversely affects the tungsten burying process.

Therefore, in the prior art, it was very difficult to simultaneously form contacts having greatly different depths. The present invention has been made in view of the above circumstances, and is a semiconductor capable of ensuring etching uniformity in a semiconductor device in which a contact hole that penetrates single-layer and multi-layer interlayer insulating films is formed in the same etching step. An object is to provide an apparatus and a manufacturing method thereof.

[0010]

According to the present invention, in order to achieve the above object, a multi-layered interlayer insulating film is formed on a substrate, and one of the upper interlayer insulating films penetrates through the upper interlayer insulating film. At an intermediate connection portion for connecting the upper wiring in and the intermediate wiring on the lower interlayer insulating film therebelow, and through the upper interlayer insulating film and the lower interlayer insulating film thereunder, In a semiconductor device having an upper wiring on an insulating film and a conductive portion connecting portion that connects a conductive portion covered by a lower interlayer insulating film, a connection recess formed in the lower interlayer insulating film. And the intermediate wiring formed over the lower interlayer insulating film and the connection recess, the intermediate wiring penetrating the upper interlayer insulation film in the connection recess and existing at the bottom of the connection recess, and the upper wiring. And a recess connecting portion for connecting with Providing conductor device.

In order to achieve the above object, the present invention further comprises the step of forming a lower interlayer insulating film on a substrate, the step of forming a connection recess in the lower interlayer insulating film, and the lower interlayer insulating film. A step of forming an intermediate wiring on the top and the bottom of the connection recess; a step of forming an upper interlayer insulating film covering the intermediate wiring; and a recess contact reaching the intermediate wiring layer at the bottom of the connection recess in the upper interlayer insulating film. A step of forming a hole and a contact portion contact hole that penetrates the upper interlayer insulating film and the lower interlayer insulating film and reaches the conductive portion covered with the lower interlayer insulating film; Provided is a method for manufacturing a semiconductor device, which comprises a step of filling a hole with a conductor to form a recess connection portion and a conductive portion to fill the contact hole with a conductor, respectively. To do.

According to the method of manufacturing a semiconductor device of the present invention, a contact hole formed in the same etching step is used to penetrate 2
Of the interlayer insulating film of the layer, a recess is formed in the lower interlayer insulating film, the wiring layer on the lower interlayer insulating film is arranged at the bottom of the recess, and the upper interlayer insulating film is formed on the lower interlayer insulating film. After the formation, the contacted portion contact hole penetrating these interlayer insulating films and the recess contact hole penetrating the upper interlayer insulating film and reaching the wiring layer in the recess are formed.

The recess contact hole penetrates the upper interlayer insulating film, but since it reaches the recess formed in the lower interlayer insulating film therebelow, the thickness of the upper interlayer insulating film is equal to that of the recess. Therefore, the difference in depth from the contact hole of the conductive portion is small.

Therefore, since the contact hole, which was conventionally shallow, can be deepened by the depth of the recess to minimize the difference in depth from the deep contact, it is possible to prevent overetching during etching. It is possible to prevent the deterioration of the shape of the contact hole.

In the semiconductor device of the present invention, the connection recess formed in the lower interlayer insulating film and the intermediate wiring penetrating the upper interlayer insulating film in the connection recess and existing at the bottom of the connection recess and the upper wiring are formed. And a recess connecting portion for connecting the. Since the recess connecting portion is longer by the length of the recess, the difference in length between the connecting portion penetrating both the upper interlayer insulating film and the lower interlayer insulating film is small, and the problem at the time of forming both connecting portions is avoided. can do.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described, but the present invention is not limited to the following embodiments. FIG. 1 shows a sectional structure of one embodiment of the semiconductor device of the present invention, and shows a structural portion corresponding to FIG. In this semiconductor device 1, an element isolation insulating film (LOCOS) 21 is formed on the surface of the semiconductor substrate 10, and the substrate surface where the element isolation insulating film 21 is not formed is, for example, the source diffusion layer SD of FIG. The diffusion layer 11 is formed. On the element isolation insulating film 21, for example, gate electrodes (two in the drawing) 31 (for example, the selection transistor STG2 in FIG. 6) and 32 (for example, the memory transistor MTG1 in FIG. 6) having a polycide structure are wired, and the first interlayer insulation is performed. Membrane 41
Covers these wires. This first interlayer insulating film 41
Has a connection recess 50 penetrating the first interlayer insulating film 41. The connection recess 50 is formed in the element isolation insulating film 2
1 also penetrates and reaches the surface of the substrate 10. Then, on the surface of the first interlayer insulating film 41, an intermediate wiring 33 having a polycide structure such as a source line of a flash memory having a double bit line structure is formed, and the intermediate wiring 33 is a diffusion layer of the substrate 10. 11 and the first connecting portion 34. The intermediate wiring 33a is also formed on the bottom of the connection recess 50.

The second interlayer insulating film 42 covers the first interlayer insulating film 41. In the second interlayer insulating film 42,
For example, the first upper wiring 36 made of aluminum (for example, the select gate wiring STGL in the flash memory having the double bit line structure of FIG. 6) and the second upper wiring layer 37 also made of aluminum (for example, FIG. 6). Source line SL) in FIG. The first upper wiring 36 is connected to the element isolation insulating film 2 by the connected portion 38 that penetrates the second interlayer insulating film 42 and the first interlayer insulating film 41.
1 is connected to the upper wiring layer 31. In addition, the second upper wiring layer 37 includes the intermediate wiring layer 3 existing at the bottom of the connection concave portion 50 due to the concave portion connecting portion 39 penetrating the second interlayer insulating film 42.
It is connected to 3a.

In the semiconductor device 1 having such a structure, the length of the recess connection portion 39 is equal to the thickness of the second interlayer insulating film 42 and the first
It is almost the same as the thickness of the interlayer insulating film 41. On the other hand, the length of the conductive portion connection portion 38 is the sum of the thickness obtained by subtracting the thickness of the wiring layer 31 from the second interlayer insulating film 42 and the first interlayer insulating film 41. In addition, the length of the connecting portion BC that penetrates the second interlayer insulating film 42 and the first interlayer insulating film 41 and reaches the substrate as shown in FIG. 6 is determined by the first interlayer insulating film 41 and the second interlayer insulating film. 42 and the total.

Therefore, these three connecting portions 38, 39,
Since the AC lengths are substantially the same, these three contact holes can be completed at approximately the same time when the contact holes are opened by etching using the resist formed on the second interlayer insulating film 42 as a mask. Therefore, it is possible to prevent the shape of the contact hole from being deteriorated due to overetching. Further, since the shallow contact hole is conventionally formed deeply, the depth of the deepest contact hole is not increased. So, for example, to form these connections,
When the contact hole is filled with tungsten or the like, the embedded shape does not deteriorate.

Next, the manufacturing process of the semiconductor device 1 will be described. First, as shown in FIG. 2A, the element isolation insulating film (LOCOS) 21 is formed by thermal oxidation in a state where the active region of the semiconductor substrate 10 is covered with, for example, silicon nitride. Next, as shown in FIG. 2B, various gate electrodes 31 and 32 are formed. For example, the gate electrode of the select transistor in the multi-bit line structure, the control gate of the memory transistor, the gate electrode of the transistor of the peripheral circuit, etc. are formed as the second polycide composed of, for example, polysilicon 31a and tungsten silicide 31b. When forming a memory transistor having a floating gate such as a flash memory, the floating gate and an insulating film such as ONO are formed before forming the gate electrode. Further, the diffusion layer 11 is formed by ion implantation or the like.

Thereafter, as shown in FIG. 2C, for example, silicon oxide is deposited by CVD or the like to form the first interlayer insulating film 41.
And the gate electrodes 31 and 32 are embedded. Then
As shown in FIG. 2D, after patterning a resist (not shown) on the first interlayer insulating film 41, contact holes 61 with the diffusion layer 11 of the substrate are formed by reactive ion etching or the like.
And the 1st etching process which forms the connection recessed part 50 grade | etc., Is performed. It is preferable that the etching for forming the connection recess 50 is performed so as to penetrate the element isolation insulating film 21 and reach the surface of the substrate 10 using the substrate as an etching stopper, as shown in FIG. The bottom surface of the connection recess 50 is composed of the surface of the substrate 10. Since the purpose of the connection recess 50 is to deepen the shallow contact hole to make the relative ratio of the depth to the deep contact as small as possible, the depth of the connection recess 50 is not limited to the substrate surface. Alternatively, it can be appropriately selected.

Then, as shown in FIG. 3E, for example, in the multi-bit line and the intermediate wiring layer 33 such as the source wiring layer in the flash memory having the multi-bit line structure, for example, a polycide structure of polysilicon 33a and tungsten silicide 33b is used. (Third polycide) or the like. The intermediate wiring layer 33 fills the contact hole 61 and is connected to the diffusion layer 11 of the substrate 10 at the first connection portion 34. Further, the connection recess 5 is formed so as to cover at least a part of the bottom surface of the connection recess 50.
It also forms 0.

Next, as shown in FIG. 3 (f), for example, B
PSG or the like is deposited by CVD or the like to form the second interlayer insulating film 42, the intermediate wiring layer 33 is filled, and a planarization process such as reflow is performed. Then, as shown in FIG. 3G, after patterning a resist (not shown) on the second interlayer insulating film 42, a second etching process is performed, and a flash of a double bit line structure is performed by reactive ion etching or the like. A conductive portion contact hole 62 for connecting to the gate electrode of the select transistor in the memory and a recess contact hole 63 for connecting to the intermediate wiring 33a on the bottom surface of the connection recess 50 are opened by reactive ion etching or the like. In this etching, the contacted portion contact hole 62 and the recessed contact hole 63 have substantially the same depth, and even when a deep contact hole directly connected to the substrate surface as shown in FIG. The contact holes have almost the same depth, and there is no risk of overetching.

Next, as shown in FIG. 4H, for example, by a method of depositing tungsten and then etching back,
The contact hole 62 is filled with tungsten to fill the connected portion 38, the contact hole 63 is filled with tungsten to fill the recessed connecting portion 39, and other contact holes to form a connecting portion.

Then, after depositing aluminum on the second interlayer insulating film 42, patterning is performed to form, for example, a select gate wiring 36 and a source line 37 in a flash memory having a multi-bit line structure which is connected to each connection portion. As a result, the semiconductor structure shown in FIG. 1 can be realized.

According to the above process, the connection recess can be formed in the first contact hole forming process using the same mask as the contact forming process and the same etching process, and therefore the number of process steps does not increase. Further, in the second contact hole forming step, since the depths of the contact holes are aligned, overetching can be prevented,
Since the filling of the contact hole is not deteriorated, the yield is improved.

[0027]

According to the semiconductor device of the present invention, since the length of the connection between the wiring on the upper interlayer insulating film and the wiring on the lower interlayer insulating film or the substrate surface is the same, the connection portion is formed. Over-etching is unlikely to occur and reliable connection is possible.

Further, according to the method of manufacturing a semiconductor device of the present invention, when forming the contact holes penetrating the plurality of interlayer insulating films, the depth of the contact holes is uniform, so that a contact hole having a good shape is formed. It can be formed and the yield is improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor device of the present invention.

2A to 2D are cross-sectional views showing a manufacturing process of a semiconductor device of the present invention.

3 (e) to 3 (g) are cross-sectional views showing the manufacturing process subsequent to FIG.

4 (h) and (i) are cross-sectional views showing the manufacturing process following FIG.

FIG. 5 is a plan view of a flash memory having a sub bit line structure.

FIG. 6 is a cross-sectional view taken along the line A-A ′ of FIG.

7 is a cross-sectional view taken along the line B-B ′ of FIG.

[Explanation of symbols]

10 ... Substrate, 21 ... Element isolation insulating film, 31, 32 ... Gate electrode, 33 ... Intermediate wiring layer, 38 ... Conductive connection part, 39
... Recess connection portion, 41 ... First interlayer insulating film, 42 ... Second interlayer insulating film, 50 ... Connection recess

Claims (5)

[Claims] 1. A multi-layered interlayer insulating film is formed on a substrate, one upper interlayer insulating film of which is penetrated, and an upper wiring on the upper interlayer insulating film and a lower interlayer insulating film below the upper wiring. An intermediate connection portion connecting the upper intermediate wiring, and the upper interlayer insulating film and the lower interlayer insulating film thereunder are penetrated to form an upper wiring on the upper interlayer insulating film and a lower interlayer insulating film. In a semiconductor device having a covered portion connecting portion that connects the covered portion to be covered, a connecting concave portion formed in the lower interlayer insulating film, and the lower interlayer insulating film and the connecting concave portion. It is characterized in that it has the formed intermediate wiring and a recess connection portion that penetrates the upper interlayer insulating film in the connection recess and connects the intermediate wiring and the upper wiring at the bottom of the connection recess. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a bottom surface of the connection recess is a substrate surface. 3. A step of forming a lower interlayer insulating film on a substrate, a step of forming a connecting recess in the lower interlayer insulating film, and an intermediate wiring on the lower interlayer insulating film and at the bottom of the connecting recess. A step of forming, an step of forming an upper interlayer insulating film covering the intermediate wiring, a concave contact hole reaching the intermediate wiring layer at the bottom of the connection concave, the upper interlayer insulating film and the lower side of the upper interlayer insulating film. A step of penetrating the interlayer insulating film and forming a contact hole of the conductive portion reaching the conductive portion covered with the lower interlayer insulating film; and filling the concave contact hole with a conductor to form a concave connecting portion. ,
A step of filling the contact hole of the conductive portion with a conductor to form a connecting portion of the conductive portion, respectively. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the connection recess is formed by penetrating an element isolation insulating film formed on the substrate surface. 5. The method of manufacturing a semiconductor device according to claim 3, wherein the etching for forming the connection recess and the etching for forming a contact hole formed in the lower interlayer insulating film are performed in the same etching step.