JPH09283673A - Heat sink structure - Google Patents

Heat sink structure

Info

Publication number
JPH09283673A
JPH09283673A JP8115538A JP11553896A JPH09283673A JP H09283673 A JPH09283673 A JP H09283673A JP 8115538 A JP8115538 A JP 8115538A JP 11553896 A JP11553896 A JP 11553896A JP H09283673 A JPH09283673 A JP H09283673A
Authority
JP
Japan
Prior art keywords
heat sink
heat
heat conduction
logic package
integrated circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8115538A
Other languages
Japanese (ja)
Other versions
JP2924788B2 (en
Inventor
Yuji Kuramitsu
裕二 倉光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8115538A priority Critical patent/JP2924788B2/en
Publication of JPH09283673A publication Critical patent/JPH09283673A/en
Application granted granted Critical
Publication of JP2924788B2 publication Critical patent/JP2924788B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a heat dissipating surface area of a heat sink by using a planar type heat sink in contrast to the conventionally realized three dimensional heat dissipation in a space above an integrated circuit plane by joining thermal conduction blocks whose heights being set separately to integrated circuits and by laminating a plate type heat sink on the integrated circuits in correspondence with above-mentioned heights so that the heat sink is counterposed with a logic package. SOLUTION: A plurality of integrated circuits 2 are mounted on a logic package 1 and thermal conduction blocks 3 are joined to the integrated circuits at the surfaces thereof, and the thermal conduction blocks 3 are provided with fixing means such as female screws on the surface thereof joining with the thermal conductor 3 and on the other surface thereof. The thermal conduction blocks 3 whose heights being set separately are joined on a plurality of integrated circuit 2 and a plate type heat sink 6 is stacked on the integrated circuits 2 in correspondence with above-mentioned heights so that the heat sink 6 is counterposed with a logic package 1. Thus, the heat dissipating surface area of the heat sink 6 can be realized in a planar form, the mounting efficiency of the logic package can be improved, the shape of the heat sink 6 can be simplified, and the cost can be reduced.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、ヒートシンク構造
に関し、特にコンピュータ等に用いて好適な論理パッケ
ージの、冷却構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a heat sink structure, and more particularly to a cooling structure for a logic package suitable for use in a computer or the like.

【0002】[0002]

【従来の技術】従来、論理パッケージ上に実装される集
積回路の放熱用ヒートシンクの構造は、放熱効率を向上
させるために、放熱フィンとして、例えば特開平3−2
11863号公報には図3および図4に示すような形状
が提案され、一般にも採用されている。図3は、上記公
報に提案される従来のヒートシンク付きセラミックパッ
ケージの斜視図であり、図4はその断面図を示してい
る。図3および図4を参照して、この従来のヒートシン
ク付きパッケージは、セラミック基板11上に接着され
たチップ12と、このチップ12を塞ぐようにセラミッ
ク基板11上に接着されたキャップ16と、このキャッ
プ16上に接着されたヒートシンク17からなり、ヒー
トシンク17には水平型フィン17bが取り付けられた
複数の支柱17aを放熱面上に並列に備えた構造とされ
ている。
2. Description of the Related Art Conventionally, in the structure of a heat sink for heat dissipation of an integrated circuit mounted on a logic package, in order to improve heat dissipation efficiency, for example, as a heat dissipation fin, for example, Japanese Patent Laid-Open No. 3-2.
Japanese Patent No. 11863 proposes a shape as shown in FIGS. 3 and 4 and is generally adopted. FIG. 3 is a perspective view of a conventional ceramic package with a heat sink proposed in the above publication, and FIG. 4 is a sectional view thereof. Referring to FIGS. 3 and 4, this conventional package with a heat sink has a chip 12 adhered on a ceramic substrate 11, a cap 16 adhered on the ceramic substrate 11 so as to cover the chip 12, and The heat sink 17 is adhered onto the cap 16, and the heat sink 17 has a plurality of columns 17a to which horizontal fins 17b are attached in parallel on the heat radiation surface.

【0003】このような放熱用ヒートシンク構造が用い
られる理由は、論理パッケージにおける、集積回路の実
装配置が、性能確保や低原価達成の目的で、年々密集し
てきており、ヒートシンクの放熱表面積を確保するため
には、真上、即ち個々の集積回路の表面上の空間に、図
3に示すように、ヒートシンク17のフィン17bの表
面積を必要なだけ確保する方法を採らざるを得ないこと
による。
The reason why such a heat sink structure for heat dissipation is used is that the mounting arrangement of integrated circuits in the logic package is becoming denser year by year for the purpose of ensuring performance and achieving low cost, and the heat dissipation surface area of the heat sink is ensured. In order to do so, it is necessary to adopt a method of securing the surface area of the fins 17b of the heat sink 17 as needed as shown in FIG. 3 in the space directly above, that is, on the surface of each integrated circuit.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記し
た従来の放熱用ヒートシンク構造における第1の問題点
は、前述した、ヒートシンクのフィンの必要放熱表面積
を、集積回路の表面上の空間で確保することが困難とな
ってきているということである。
However, the first problem with the above-described conventional heat sink structure for heat dissipation is to secure the required heat dissipation surface area of the fins of the heat sink in the space above the surface of the integrated circuit. Is becoming difficult.

【0005】これは、近時のコンピュータのダウンサイ
ジング化及び高性能化により、筐体内へ実装される複数
枚の論理パッケージの実装間隔を極力狭くすることの必
要性が生じてきており、このため上記従来技術のよう
に、集積回路の表面上の空間(表面実装高さ)で使用で
きる範囲が少なくなってきたことによる。
This is due to the recent downsizing and high performance of computers, and it has become necessary to make the mounting interval of a plurality of logic packages mounted in a housing as narrow as possible. This is because the usable range in the space above the surface of the integrated circuit (surface mounting height) has decreased as in the prior art.

【0006】従来の放熱用ヒートシンク構造における第
2の問題点は、ヒートシンクの構造が複雑になり、低原
価が望めないということである。
The second problem with the conventional heat sink structure for heat dissipation is that the structure of the heat sink is complicated and the low cost cannot be expected.

【0007】その理由は、従来の放熱用ヒートシンク構
造は、上記したように、集積回路表面上の空間で、放熱
効率の良い放熱フィンの形状を実現しなければならない
ため、フィン形状を複雑にして放熱表面積を増やさなけ
ればならないことによる。
The reason for this is that in the conventional heat sink structure for heat dissipation, as described above, the shape of the heat dissipation fin with good heat dissipation efficiency must be realized in the space on the surface of the integrated circuit. Due to the need to increase the heat dissipation surface area.

【0008】従って、本発明は、上記事情に鑑みて為さ
れたものであて、その目的は、集積回路面上の空間で立
体的に実現していたヒートシンクの放熱表面積を平面型
にて実現可能とし、論理パッケージの実装効率を向上で
きると共に、ヒートシンクの形状を簡素化し、低原価を
図るヒートシンク構造を提供することにある。
Therefore, the present invention has been made in view of the above circumstances, and an object thereof is to realize a heat dissipation surface area of a heat sink which is three-dimensionally realized in a space on the surface of an integrated circuit with a flat type. Another object of the present invention is to provide a heat sink structure capable of improving the packaging efficiency of the logic package, simplifying the shape of the heat sink, and reducing the cost.

【0009】[0009]

【課題を解決するための手段】前記目的を達成するた
め、本発明のヒートシンク構造は、論理パッケージ上に
搭載された複数の集積回路の上に、高さを個別に設定し
た熱伝導ブロックを接合し、前記熱伝導ブロックの高さ
に対応して平板状のヒートシンクを前記論理パッケージ
と対向するように積み上げてなることを特徴とする。
In order to achieve the above-mentioned object, the heat sink structure of the present invention joins a heat conduction block whose height is individually set on a plurality of integrated circuits mounted on a logic package. A heat sink having a flat plate shape is stacked corresponding to the height of the heat conduction block so as to face the logic package.

【0010】また、本発明のヒートシンク構造は、論理
パッケージの上に搭載された複数の集積回路の表面上に
一側端面を接合してなる熱伝導ブロックをそれぞれ備
え、前記複数の集積回路毎に設けられる熱伝導ブロック
の他側端面の高さの相違に応じ前記論理パッケージと対
向して個別に設けられる平板状のヒートシンク部材を積
み上げ、前記一又は複数の熱伝導ブロックに対応するヒ
ートシンク部材は、自ヒートシンク部材に対応する一又
は複数の熱伝導ブロックを固定する手段を有すると共
に、該自ヒートシンク部材に対応する熱伝導ブロックよ
りも高さの高い他の熱伝導ブロックがある場合には、該
熱伝導ブロックを上層に挿通させるための開口を備えた
ことを特徴とする。
Further, the heat sink structure of the present invention is provided with a heat conduction block formed by joining one end face on the surface of a plurality of integrated circuits mounted on the logic package, and each of the plurality of integrated circuits. The heat sink members corresponding to the one or more heat conduction blocks are stacked by stacking flat heat sink members individually provided facing the logic package according to the difference in height of the other end surface of the heat conduction block. If there is another heat conduction block having a height higher than that of the heat conduction block corresponding to the self heat sink member, the heat conduction block has means for fixing one or a plurality of heat conduction blocks corresponding to the heat sink member. It is characterized by having an opening for inserting the conductive block into the upper layer.

【0011】本発明においては、前記ヒートシンクの面
積が前記論理パッケージの面積と略等しいことを特徴と
する。
In the present invention, the area of the heat sink is substantially equal to the area of the logic package.

【0012】[0012]

【発明の実施の形態】本発明の実施の形態を、図1およ
び図2を参照して以下に説明する。なお、図1および図
2は、本発明の実施の形態を説明するための図である。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. 1 and 2 are diagrams for explaining the embodiment of the present invention.

【0013】本発明の実施の形態においては、論理パッ
ケージ1と、この論理パッケージ1上に複数個搭載され
た集積回路2の表面に垂直方向に半田等の熱伝導体3が
接合され、熱伝導体との接合面と他端面には雌ねじ5等
の固定手段を具備した熱伝導ブロック3を備え、この熱
伝導ブロック3は、集積回路面に対する垂直方向の高さ
が個別に設定された集積回路毎に個別に用意される。そ
して、論理パッケージ1とほぼ同等の面積を持ち、集積
回路毎に個別に用意される、一又は複数層の平板状ヒー
トシンク6を備え、各ヒートシンク6には、任意の熱伝
導体の端面に設けられた雌ねじに対向する固定孔7及
び、他の熱伝導体を貫通させるための干渉逃げ孔8が設
けられている。
In the embodiment of the present invention, a heat conductor 3 such as a solder is vertically joined to the surface of the logic package 1 and a plurality of integrated circuits 2 mounted on the logic package 1 so as to conduct heat. A heat conduction block 3 provided with fixing means such as an internal screw 5 is provided on the joint surface with the body and the other end surface. The heat conduction block 3 has an integrated circuit whose height in the vertical direction with respect to the integrated circuit surface is individually set. It is prepared separately for each. Further, it is provided with one or a plurality of layers of flat plate heat sinks 6 each having an area substantially equal to that of the logic package 1 and prepared individually for each integrated circuit. Each heat sink 6 is provided on an end face of an arbitrary heat conductor. A fixing hole 7 that faces the formed female screw and an interference escape hole 8 through which another heat conductor penetrates are provided.

【0014】本発明の実施の形態においては、上記の構
造を採ることで、論理パッケージ内の、他の集積回路の
配置に影響を受けずに論理パッケージと、ほぼ同等の広
い放熱表面積が確保できる。
In the embodiment of the present invention, by adopting the above structure, it is possible to secure a large heat dissipation surface area substantially equal to that of the logic package without being affected by the arrangement of other integrated circuits in the logic package. .

【0015】また、本発明の実施の形態においては、集
積回路表面上の空間をさほど占有する必要が無いため
に、複数毎の論理パッケージの実装間隔を狭められ、装
置の性能向上や、小型化に寄与できる。
Further, in the embodiment of the present invention, since it is not necessary to occupy the space on the surface of the integrated circuit so much, the mounting interval of each plurality of logic packages can be narrowed, the performance of the device can be improved, and the device can be miniaturized. Can contribute to.

【0016】さらに、本発明の実施の形態によれば、ヒ
ートシンクの形状が非常に簡素化できることで、低原価
を実現できる。
Furthermore, according to the embodiment of the present invention, the cost of the heat sink can be reduced because the shape of the heat sink can be greatly simplified.

【0017】[0017]

【実施例】次に、本発明の実施例を図面を参照して詳細
に説明する。
Embodiments of the present invention will now be described in detail with reference to the drawings.

【0018】図1および図2を参照して、論理パーケッ
ジ1には4つの集積回路2、2′、2″、2″′が搭載
されているものとする。なお、図1および図2には論理
パッケージ1上に集積回路が4個搭載された構成を示し
たが、本発明はこの構成に限定されるものでないことは
勿論である。
Referring to FIGS. 1 and 2, it is assumed that four integrated circuits 2, 2 ', 2 ", 2"' are mounted on the logic package 1. Although FIG. 1 and FIG. 2 show a configuration in which four integrated circuits are mounted on the logic package 1, it goes without saying that the present invention is not limited to this configuration.

【0019】図1(A)に平面図およびA−A′線矢視
図として示すように、論理パッケージ1に搭載された集
積回路2に予め設定された熱伝導ブロック3が半田にて
接合されている。集積回路2上の熱伝導ブロック3に
は、半田接合面と反対の端面には、雌ねじ5が、少なく
とも1ケ所以上具備されている。
As shown in FIG. 1A as a plan view and a view taken along the line AA ', a preset heat conduction block 3 is soldered to the integrated circuit 2 mounted on the logic package 1. ing. The heat conduction block 3 on the integrated circuit 2 is provided with at least one female screw 5 on the end surface opposite to the solder joint surface.

【0020】図1(A)を参照して、ヒートシンク6
は、論理パッケージ1面とほぼ同等の面積を持ち、集積
回路上2の熱伝導ブロック3に固定孔が対向すべく重ね
合わせられ、熱伝導ブロック3の雌ねじ5へ雄ねじ7に
て固定される。
Referring to FIG. 1A, the heat sink 6
Has a surface area substantially equal to that of the surface of the logic package 1, is fixed to the heat conduction block 3 on the integrated circuit 2 so that the fixing holes face each other, and is fixed to the female screw 5 of the heat conduction block 3 with the male screw 7.

【0021】このヒートシンク6には、熱伝導ブロック
3との固定孔以外に、他の熱伝導ブロック3′、3″、
3″′との干渉を避けるための所定のクリアランスを有
する干渉逃げ孔(開口)8、8′、8″が設けられてお
り、集積回路2′、2″、2″′上の熱伝導熱伝導ブロ
ック3′、3″、3″′はヒートシンク6の干渉逃げ孔
8、8′、8″を挿通している。
In this heat sink 6, in addition to the fixing holes for the heat conduction block 3, other heat conduction blocks 3 ', 3 ",
Interference escape holes (openings) 8, 8 ', 8 "having a predetermined clearance for avoiding interference with 3""are provided, and heat conduction heat on the integrated circuits 2', 2", 2 "'is provided. The conductive blocks 3 ′, 3 ″, 3 ″ ″ pass through the interference escape holes 8, 8 ′, 8 ″ of the heat sink 6.

【0022】本発明の実施の形態においては、高さがそ
れぞれ異なる熱伝導ブロック3、3″、3″′3に対応
して、ヒートシンク6、6′、6″、6″′が、それぞ
れ積層される如く取り付けられ、論理パッケージの冷却
構造を構成している。
In the embodiment of the present invention, the heat sinks 6, 6 ', 6 "and 6"' are laminated corresponding to the heat conduction blocks 3, 3 ", 3""3 having different heights. Are mounted as described above to form a cooling structure of the logic package.

【0023】すなわち、図1(B)を参照して、第2層
のヒートシンク6′は、論理パッケージ1面とほぼ同等
の面積を持ち、集積回路上2′の熱伝導ブロック3′に
固定孔が対向すべく重ね合わせられ、熱伝導ブロック
3′の雌ねじ5′へ雄ねじ7′にて固定される。このヒ
ートシンク6′には、熱伝導ブロック3′との固定孔以
外に、他の熱伝導ブロック3″、3″′との干渉を避け
るための所定のクリアランスを有する干渉逃げ孔(開
口)8′、8″が設けられており、集積回路2″、
2″′上の熱伝導熱伝導ブロック3″、3″′はヒート
シンク6′の干渉逃げ孔8′、8″を挿通している。
That is, referring to FIG. 1B, the heat sink 6'of the second layer has an area substantially equal to that of the surface of the logic package 1 and has a fixing hole in the heat conduction block 3'on the integrated circuit 2 '. Are superposed so as to face each other and fixed to the female screw 5'of the heat conduction block 3'with the male screw 7 '. The heat sink 6'has an interference escape hole (opening) 8'having a predetermined clearance for avoiding interference with other heat conduction blocks 3 ", 3"'in addition to the fixing hole with the heat conduction block 3'. , 8 "are provided for the integrated circuit 2",
The heat conduction blocks 3 "and 3""on the 2""are inserted through the interference escape holes 8'and 8" of the heat sink 6 '.

【0024】同様に、図2(A)を参照して、第3層の
ヒートシンク6″も、論理パッケージ1面とほぼ同等の
面積を持ち、集積回路2″上の熱伝導ブロック3″に固
定孔が対向すべく重ね合わせられ、熱伝導ブロック3″
の雌ねじ5″へ雄ねじ7″にて固定される。このヒート
シンク6″には、熱伝導ブロック3″との固定孔以外
に、他の熱伝導ブロック3″′との干渉を避けるための
所定のクリアランスを有する干渉逃げ孔(開口)8″′
が設けられており、集積回路2″′上の熱伝導熱伝導ブ
ロック3″′はヒートシンク6″の干渉逃げ孔8″′を
挿通し、図2(B)に示すように、熱伝導熱伝導ブロッ
ク3″′は第4層のヒートシンク6″′にてその固定孔
が対向すべく重ね合わせられ、熱伝導ブロック3″′の
雌ねじ5″′へ雄ねじ7″′にて固定される。
Similarly, referring to FIG. 2A, the heat sink 6 "of the third layer also has an area substantially equal to the surface of the logic package 1 and is fixed to the heat conduction block 3" on the integrated circuit 2 ". The holes are stacked so that they face each other, and the heat conduction block 3 "
It is fixed to the female screw 5 ″ of FIG. The heat sink 6 ″ has an interference escape hole (opening) 8 ″ ″ having a predetermined clearance for avoiding interference with another heat conduction block 3 ″ ″, in addition to a fixing hole for the heat conduction block 3 ″.
Is provided, the heat conduction heat conduction block 3 ″ ″ on the integrated circuit 2 ″ ″ is inserted through the interference escape hole 8 ″ ″ of the heat sink 6 ″, and as shown in FIG. The block 3 "" is superposed on the heat sink 6 "" of the fourth layer so that its fixing holes face each other, and is fixed to the female screw 5 "" of the heat conduction block 3 "" by the male screw 7 "".

【0025】[0025]

【発明の効果】以上説明したように、本発明によれば、
論理パッケージとほぼ同等の広い面積を有することが可
能とされており、集積回路の発熱を効率的に放熱可能と
なる。
As described above, according to the present invention,
It is possible to have a wide area almost equal to that of the logic package, and it is possible to efficiently dissipate the heat generated by the integrated circuit.

【0026】これは、本発明によれば、他の集積回路上
の熱伝導ブロックと干渉しない逃げ孔を有したヒートシ
ンクを、論理パッケージ上積層するべく取り付けられる
ことで、必要放熱表面積を、充分確保することが可能と
なる。
According to the present invention, a heat sink having an escape hole which does not interfere with a heat conduction block on another integrated circuit is attached so as to be stacked on the logic package, so that a necessary heat radiation surface area is sufficiently secured. It becomes possible to do.

【0027】また、本発明によれば、ヒートシンクの形
状が、非常に簡素化できるため、低原価が実現可能とな
る。
Further, according to the present invention, since the shape of the heat sink can be greatly simplified, low cost can be realized.

【0028】これは、本発明においては、論理パッケー
ジ内の集積回路の配置に、影響を受けることなく、広い
放熱面積が確保可能であることによる。
This is because, in the present invention, a large heat dissipation area can be secured without being affected by the arrangement of the integrated circuits in the logic package.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.

【図2】本発明の実施の形態を示す図である。FIG. 2 is a diagram showing an embodiment of the present invention.

【図3】従来技術の一例を示す斜視図である。FIG. 3 is a perspective view showing an example of a conventional technique.

【図4】従来技術の一例を示す断面図である。FIG. 4 is a cross-sectional view showing an example of a conventional technique.

【符号の説明】[Explanation of symbols]

1 論理パッケージ 2 集積回路 3 熱伝導ブロック 4 半田 5 熱伝導ブロック3の雌ねじ 6 ヒートシンク 1 Logic Package 2 Integrated Circuit 3 Thermal Conduction Block 4 Solder 5 Female Thread of Thermal Conduction Block 3 6 Heat Sink

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】論理パッケージ上に搭載された複数の集積
回路の上に、高さを個別に設定した熱伝導ブロックを接
合し、前記熱伝導ブロックの高さに対応して平板状のヒ
ートシンクを前記論理パッケージと対向するように積み
上げてなることを特徴とするヒートシンク構造。
1. A heat conduction block, the height of which is individually set, is bonded onto a plurality of integrated circuits mounted on a logic package, and a flat heat sink is provided corresponding to the height of the heat conduction block. A heat sink structure, wherein the heat sink structure is stacked so as to face the logic package.
【請求項2】複数の集積回路を搭載した論理パッケージ
と、 前記複数の集積回路の表面上にそれぞれ垂直方向に熱伝
導体にて接合され該接合面と他側端面とに固定用部材を
有する複数の熱伝導ブロックと、 前記論理パッケージと同等面積で、前記複数の前記熱伝
導ブロックうちの1又は複数の熱伝導ブロックに対向す
る固定孔と、他の熱伝導ブロックを貫通させる孔と、を
具備してなる1又は複数の平板状ヒートシンクと、 を含むことを特徴とするヒートシンク構造。
2. A logic package having a plurality of integrated circuits mounted thereon, and a fixing member on the surfaces of the plurality of integrated circuits which are vertically bonded to each other by a heat conductor and which are fixed to the bonding surface and the other end surface. A plurality of heat conduction blocks; a fixing hole having an area equal to that of the logic package and facing one or a plurality of the heat conduction blocks of the plurality of heat conduction blocks; and a hole through which another heat conduction block penetrates. A heat sink structure comprising: one or a plurality of plate-shaped heat sinks provided.
【請求項3】前記熱伝導ブロックが前記他側端面にネジ
部材を備え、対応する前記ヒートシンクと前記固定孔に
て重ね合わされてネジ固定されることを請求項2記載の
特徴とするヒートシンク構造。
3. The heat sink structure according to claim 2, wherein the heat conduction block is provided with a screw member on the other end surface, and is screwed by being superposed on the corresponding heat sink in the fixing hole.
【請求項4】論理パッケージの上に搭載された複数の集
積回路の表面上に一側端面を接合してなる熱伝導ブロッ
クをそれぞれ備え、 前記複数の集積回路毎に設けられる熱伝導ブロックの他
側端面の高さの相違に応じ前記論理パッケージと対向し
て個別に設けられる平板状のヒートシンク部材を積み上
げ、 前記一又は複数の熱伝導ブロックに対応するヒートシン
ク部材は、自ヒートシンク部材に対応する一又は複数の
熱伝導ブロックを固定する手段を有すると共に、該自ヒ
ートシンク部材に対応する熱伝導ブロックよりも高さの
高い他の熱伝導ブロックがある場合には、該熱伝導ブロ
ックを上層に挿通させるための開口を備えたことを特徴
とするヒートシンク構造。
4. A heat conduction block comprising a plurality of integrated circuits mounted on a logic package, one surface of which is joined to the surface of the integrated circuit, the other heat conduction blocks being provided for each of the plurality of integrated circuits. Plate-shaped heat sink members individually provided facing the logic package according to the height difference of the side end face are stacked, and the heat sink member corresponding to the one or the plurality of heat conduction blocks corresponds to its own heat sink member. Or, if there is a means for fixing a plurality of heat conduction blocks and there is another heat conduction block whose height is higher than the heat conduction block corresponding to the heat sink member, the heat conduction block is inserted into the upper layer. A heat sink structure, which is provided with an opening for.
【請求項5】前記ヒートシンクの面積が前記論理パッケ
ージの面積と略等しいことを特徴とする請求項4記載の
ヒートシンク構造。
5. The heat sink structure according to claim 4, wherein the area of the heat sink is substantially equal to the area of the logic package.
JP8115538A 1996-04-12 1996-04-12 Heat sink structure Expired - Lifetime JP2924788B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8115538A JP2924788B2 (en) 1996-04-12 1996-04-12 Heat sink structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8115538A JP2924788B2 (en) 1996-04-12 1996-04-12 Heat sink structure

Publications (2)

Publication Number Publication Date
JPH09283673A true JPH09283673A (en) 1997-10-31
JP2924788B2 JP2924788B2 (en) 1999-07-26

Family

ID=14665018

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8115538A Expired - Lifetime JP2924788B2 (en) 1996-04-12 1996-04-12 Heat sink structure

Country Status (1)

Country Link
JP (1) JP2924788B2 (en)

Also Published As

Publication number Publication date
JP2924788B2 (en) 1999-07-26

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