JPH09283573A - Tape carrier package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a tape carrier package stable by providing respective alignment marks on a pair of opposite corners of a device hole wherein the alignment mark is formed with a bar with a plurality of inner leads connected and a plurality of protrusions on a side not formed with the bar. SOLUTION: Alignment marks 6 are respectively provided on a pair of opposite corners of a device hole 8, while each alignment mark 6 is formed with one or a plurality of bars 6b with two inner leads 4 connected. One or a plurality of protrusions 6a are formed on an opposite side without the bars 6b formed. The alignment mark 6 enables the bars 6b to be formed to a tip of the two inner leads 4. Further the alignment mark 6 can be formed with a through hole provided at the bars 6b. Therefore a tape carrier package can be stable and reliability in quality can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape carrier package, and more particularly to a shape of an alignment mark formed on a tape carrier package.

[0002]

2. Description of the Related Art A conventional process for manufacturing a tape carrier package will be described below.

First, gold bumps are formed by plating electrodes (pads) on a wafer. The height and size of this gold bump vary depending on the bump pitch, but the bump size is 40 to 100 μm and the bump height is 10 to 20 μm.
m.

Next, the bumped wafer is attached to a dicing sheet and diced into a chip size by a dicing device. In the case of a chip for a liquid crystal driver, the aspect ratio of the vertical and horizontal sizes is about 10 to 20 and has an elongated shape.

Next, in the inner lead bonding process, a structure in which a conductor pattern is laminated on bumps on a chip and an insulating film such as polyimide via an adhesive layer, or a conductor is formed on the insulating film via an adhesive layer Inner leads of a tape carrier having a structure in which patterns are laminated are joined using an inner lead bonding apparatus. Bonding is completed by the bump gold and the inner lead tin forming a eutectic alloy. The inner leads are formed by etching from a copper foil, but in order to form a eutectic alloy, a tin plating layer of 0.1 to 0.3 μm is formed on the inner lead surface.

In the inner lead bonding apparatus, a tape carrier wound in a reel shape and a chip diced by being attached to a dicing tape are set. The operation of the inner lead bond device will be described below.

In order to align the polyimide tape, which is the tape carrier, with the silicon chip, two parts of the tape carrier and two parts of the silicon chip are previously prepared.
Image recognition is performed at the places. Next, the chip attached to the dicing tape is picked up, moved to and mounted on the bonding stage, adsorbed in a vacuum, and fixed to the bonding stage. The position of the chip is recognized by comparing the fixed chip pattern with the previously recognized image pattern.

At the time of recognition, the two corners of the chip are pattern-recognized. The chip can be recognized relatively accurately because the aluminum wiring on the chip is accurately formed in the photolithography process. Also, the recognition is CC
D The image taken from the camera is used.

When the tape carrier is conveyed to a predetermined position, the position of the tape is grasped by comparing the previously recognized image with the image of the conveyed tape carrier. As shown in FIGS. 7A and 7B, the tape carrier is aligned by using the inner leads 4 between the silicon chip 1 and the solder resist 3 in the X and Y directions in the alignment detection area. The center of gravity is calculated from the width between the respective straight line portions of the above, and it is recognized as an alignment mark, or the alignment marks 10a to 10c formed near the device hole as shown in FIGS.
Etc.

Next, after recognizing the positions of the silicon chip 1 and the tape carrier, the bonding stage 11 moves below the tape carrier, and the alignment between the silicon chip 1 and the tape carrier is completed. At this point, as shown in FIG. 8, the aligned silicon chip 1 is located under the tape carrier, and the bonding tool 11 is located on the tape carrier.

Incidentally, FIGS. 7A to 7C show the first to third parts.
FIG. 8 is a plan view in the pattern recognition area of the inner lead bonding apparatus after inner lead bonding in the conventional tape carrier package of FIG. 8 and FIG. 8 is a diagram for explaining the inner lead bonding. 7 and 8, 1 is a silicon chip, 2 is a polyimide tape, 3 is a solder resist,
4 is an inner lead, 8 is a device hole, 9 is a bump,
Reference numeral 10 is an alignment mark, 11 is a bonding tool, 12 is a bonding stage, and 13 is a silicon chip suction port of the bonding stage.

Next, the bonding stage 12 rises, the bonding tool 11 descends, and the tin-plated inner leads 4 are thermocompression bonded to the gold bumps on the silicon chip 1. This thermocompression bonding
It is carried out at 480 ° C. or higher, and the pressure bonding load is 20 g or more per bump. The pressing time is 0.8 seconds or more. After the pressure bonding, the bonding tool 11 moves up and the bonding stage 12 moves down to complete the bonding. The silicon chip 1 is bonded to the tape carrier and held via the inner leads 4.

The recognition of the tape carrier is unstable unlike the recognition of the silicon chip 1 because it uses the etched portion of the copper foil whose shape is likely to change. Further, the accuracy of the inner lead bond needs to be improved as the pitch interval is narrower, and is ± 7 μm even at a pitch of 70 μm.
It must be: At this time, if the alignment is not properly performed, the inner lead bonding apparatus is stopped and the alignment is not performed accurately, so that the inner lead bonding is not performed well.

A prior art alignment mark is shown in FIG.
There are shapes as shown in (a) to (c). When the bump pitch is about 100 μm, as shown in FIG. 7A, the alignment mark 1 having a protrusion on one side of the inner lead is formed.
There is 0a. However, when the bump pitch becomes a fine pitch of 70 to 80 μm, the inner lead width also becomes narrow, and in the alignment mark as shown in FIG.
Since the inner leads themselves are asymmetrical, if the bonding accuracy is poor, the inner leads will be twisted and bonded, resulting in large stress under the bumps, causing the inner leads to peel off or the bump base to be scooped out. In some cases, there was a problem in terms of quality and reliability.

Therefore, using the symmetrical alignment mark 10b as shown in FIG. 7B, the assembly can be performed without any problem. Although the alignment mark 10c shown in FIG. 7C is also present, since a space for alignment on the tape side is required, it is not possible to provide space for a device with a large number of outputs, and an alignment mark cannot be provided. So it's not used much. In this way, the conventional alignment mark shape is
The shape is not always suitable for fine pitch and multi-output.

Next, after the inner lead bonding, the silicon chip 1 is held by the inner leads 4, so the liquid resin 14 is drawn, potted in a predetermined area, and cured, as shown in FIG. The silicon chip 1 and the inner leads 4 are coated. FIG. 9 is a cross-sectional view of the tape carrier package after resin sealing. In FIG. 9, 5a and 5b indicate outer leads. The potting cure is performed at 100 ° C. or higher for several hours. After curing, mark and final test, and then tape carrier package is shipped in reel form.

Further, as shown in the plan view of FIG. 10 after the tape carrier package 15 serving as the liquid crystal driver is mounted on the liquid crystal panel 16, the tape carrier package 15 is mounted on an electronic component such as a liquid crystal panel by a reel. The tape carrier package in the state is punched out and cut into individual pieces, and then soldering or anisotropic conductive adhesive (ACF) is used.

[0018]

However, the alignment mark shape of the inner lead of the prior art is 70 μm as it is.
Fine pitch from m, for example bump pitch 40 to 5
When it is used for a tape carrier package of 0 μm, there arises a problem that the alignment accuracy is greatly reduced.

The shape shown in FIG. 7B is currently 70-
There is no problem with the bump pitch of 80 μm, but there is a problem that alignment becomes difficult when the pitch is further reduced. That is, when the bump pitch becomes finer, the space between the inner leads becomes narrower, and the bar connecting the inner leads in the alignment mark 10b becomes as shown in FIG. 11, and the intersection of the inner leads and the bar becomes. The corners are rounded, and the linear part in the X direction is almost gone. FIG. 11 is a diagram for explaining the problems of the conventional technique.

As a result, when recognizing the position in the pattern recognition area by the inner lead bonding apparatus, as shown in FIG.
The straight line portion in the X direction in 1 becomes difficult to recognize, alignment deviation occurs in the Y direction, and further it becomes impossible to recognize at all, and the inner lead bonding apparatus may stop. Then, when the inner lead bond device stops, the operator moves to the inner lead bond device, and the operator has to manually operate the inner lead bond device, which requires a lot of labor, and the tape carrier package can be successfully installed. It was difficult to manufacture.

Further, when the alignment accuracy is lowered, the inner leads cannot be joined to the center of the bumps, so that the inner leads stick out from the bumps and fall off. In some cases, the inner leads come into contact with the surface of the chip and the inner leads and the chip. There was a leak or short circuit between them. Even if the inner leads were not in contact with the chip, the inner leads would protrude from the bumps, reducing the contact area between the bumps and the inner leads, causing the inner leads to peel off from the bumps, which was a major problem in terms of quality and reliability. .

[0022]

According to a first aspect of the tape carrier package of the present invention, an inner lead is formed on an insulating film having a device hole so as to project into the device hole, and the inner lead and the semiconductor. In a tape carrier package to which a chip is connected, at least one alignment mark is provided at each of at least one pair of opposing corner portions of the device hole, and the alignment mark includes a plurality of inner leads and the inner leads. It is characterized by comprising one or a plurality of continuous bar portions and one or a plurality of convex portions formed on the side of the inner lead where the bar portion is not formed.

The tape carrier package of the present invention as defined in claim 2 is characterized in that the bar portions are formed at the tips of a plurality of inner leads serving as the alignment marks. It is a carrier package.

Further, in the tape carrier package of the present invention as defined in claim 3, at least one of the convex portions is formed on each of the plurality of inner leads serving as the alignment marks on the side where the bar portion is not formed. It is a tape carrier package of Claim 1 or Claim 2 characterized by the above-mentioned.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a plan view of a tape carrier package according to a first embodiment of the present invention after inner lead bonding, and FIGS. 2A to 2E show an inner lead bonding apparatus of the present invention. First to fifth in the pattern recognition area
FIG. 3, FIG. 4, FIG. 5 and FIG. 6 are views showing the shape of the alignment mark, and are plan views of the tape carrier packages of the second to fifth embodiments of the present invention after inner lead bonding. 1 to 6, 1 is a silicon chip, 2 is a polyimide tape, 3 is a solder resist, 4 is an inner lead, 5a is an input side outer lead, 5b is an output side outer lead, 6 is an alignment mark using the inner lead, 7 Indicates a pattern recognition area of the inner lead bonding apparatus, and 8 indicates a device hole. In the present embodiment, the X direction will be described as the X direction shown in FIG.

According to the present invention, the alignment mark 6 using the inner leads is formed in which the two inner leads are connected to the corners of the device hole 8 by the bar and the convex portion is provided on the outer side of the inner hole of the device hole 8. Is characterized by. The convex portion 6a has a length of, for example, 30 to 150 μm, and may be formed in a straight line with the bar portion 6b having a width of 50 to 100 μm, as shown in FIG.
As shown in (b), even if they are not formed on a straight line, the same effect can be obtained if the tip portion of the convex portion 6a and the bar portion 6b are within the pattern recognition area 7 of the inner lead bond device. The alignment mark 6 shown in FIGS. 2A and 2B has an asymmetrical shape, but since the bar portion 5b is provided, there is no problem as in the conventional case.

Further, as shown in FIG. 2C, a projection 6a having a length of, for example, 30 to 150 μm may be provided on each of the two inner leads on the side where the bar 6b is not formed. The length of the convex portion 6a is appropriately set so that the tip end portion is in the pattern recognition area 7. In addition, the protrusions 6 a may be formed so as to be present on the one side of the inner lead in the pattern recognition area 7.

Further, in the present invention, as shown in FIG. 2 (d), the alignment mark 6 has a bar portion 6b having a width of 50 to 100 μm, which is formed by connecting two inner leads, at the tip of the inner lead. It may have been done. At this time, the convex portion 6a may be provided on the side opposite to the side where the bar portion 6b of the inner lead is formed. In this case, more linear portions in the X direction can be taken.

Further, in the present invention, as shown in FIG. 2 (e), the alignment mark 6 has a width of 100 to 150 μm.
The width of the bar portion 6b having a through hole, or the width is 5
You may make it the shape which provided two or more bar parts 6b of 0-100 micrometers.

Further, in the present invention, the alignment mark 6 may be formed by combining the shapes of the above-mentioned convex portion 6a and bar portion 6b. Further, the number of inner leads in which the bar portions are connected is not limited to two.

By thus forming the alignment mark 6 in the shapes shown in FIGS. 2 (a) to 2 (e),
Many straight line portions in the X direction can be taken.

The alignment mark 6 is made of the same material as the other inner leads 4 and can be formed when the inner leads 4 are formed. Specifically, after forming the device hole 8 and the like on the polyimide tape 2 to which an adhesive has been applied with a mold, a copper foil is attached, and then a resist is applied and patterned into a predetermined shape. Next, the copper foil is etched using the patterned resist as a mask, the resist is removed, and then solder resist coating / curing is performed.
N plating and Sn plating cure are performed.

The inner leads serving as the alignment marks 6 may be used as signal lines of the silicon chip 1 by performing inner lead bonding, but may be used as dummy leads that are not used as signal lines.
It is better to provide a dummy pad on and to perform inner lead bonding to the dummy pad. This is because it is the inner lead of the end of the silicon chip 1 which is the corner of the device hole 8 where the stress is most likely to be generated due to external impact or external force.

Further, as shown in FIG. 1, two alignment marks 6 are provided at each of the four corners of the device hole 8, or
One is formed at each of the four corners of the device hole 8 as shown in FIGS. 3 to 6, or one at each of the two corners of the device hole 8 as shown in FIG. As described above, since one or two alignment marks 6 can be arranged at one corner, 2 to 8 alignment marks 6 can be formed for one silicon chip 1 in the present invention. It is preferable to form two pieces at each corner because the design margin can be increased.

Below, the chip size is 1.5 nm × 1
It is a long and narrow chip of 7.4 nm, and the bump pitch is 50 μm pitch on the output side and 80 to 100 μm pitch on the input side.
A case where a liquid crystal driver having 00 pins is mounted on a tape carrier having a three-layer structure composed of a polyimide tape, an adhesive and a copper foil will be described.

At this time, the width of the inner leads was etched to 30 μm, the tin plating of the inner leads was 0.25 μm thick, the alignment marks had the shape shown in FIG. 1, and a total of eight alignment marks were arranged at the four corners of the device hole 8. , Was provided as a dummy lead without being connected to the signal line of the chip, and inner lead bonding was performed on the dummy bump. In addition, in order to stabilize the inner lead cumulative pitch accuracy of the tape carrier,
Tape carrier 48 hours, 25 ℃, relative humidity 50%
The humidity was adjusted under the environment of RH. Further, in order to improve the accuracy of the inner lead bond, a device capable of multi-valued recognition was used as the inner lead bond device, and a CCD camera having 400,000 pixels was used.

Under such conditions, when the inner lead bonder was fully automated, the inner lead bonder did not stop, and the accuracy of the inner lead bond was 3σ in both the X and Y directions. It was ± 5 μm even if (σ represents a standard deviation) is taken into consideration. The final test failure after assembly of the tape carrier package was not caused by the inner lead bond, and a stable and high-quality tape carrier package could be manufactured.

[0039]

As described above in detail, by using the present invention, a tape carrier package corresponding to a fine pitch of 40 to 50 μm can be stably provided and the quality reliability can be greatly improved. Specifically, the alignment deviation that occurred suddenly at 10 μm almost disappeared, and the number of times that the inner lead bonding apparatus stopped due to alignment failure was 1% when the conventional alignment mark shape was used at a pitch of 50 μm. Although the inner lead bond device was stopped at a ratio of almost 40%, specifically, it stopped only at a ratio of 0.01%, which enabled stable production.

Therefore, the number of pins per chip of the liquid crystal driver can be increased, the number of liquid crystal drivers used in the liquid crystal panel can be reduced, and the cost of the liquid crystal panel can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a plan view of a tape carrier package according to a first embodiment of the present invention after inner lead bonding.

FIG. 2A is a diagram showing a shape of a first alignment mark in a pattern recognition area of the inner lead bonding apparatus according to the present invention, and FIG. 2B is a diagram showing a shape of the second alignment mark. FIG. 4C is a diagram showing the shape of the third alignment mark, and FIG.
It is a figure which shows the shape of the said alignment mark, and (e) is a figure which shows the shape of the same 5th alignment mark.

FIG. 3 is a plan view of the tape carrier package according to the second embodiment of the present invention after inner lead bonding.

FIG. 4 is a plan view of a tape carrier package according to a third embodiment of the present invention after inner lead bonding.

FIG. 5 is a plan view of a tape carrier package according to a fourth embodiment of the present invention after inner lead bonding.

FIG. 6 is a plan view of a tape carrier package according to a fifth embodiment of the present invention after inner lead bonding.

FIG. 7A is a plan view in a pattern recognition area of an inner lead bonding apparatus after inner lead bonding in a first conventional tape carrier package, and FIG. 7B is a plan view in a second conventional tape carrier package. It is a top view in the pattern recognition area of the inner lead bond device after the inner lead bond, (c) is a plan view in the pattern recognition area of the inner lead bond device after the inner lead bond in the third conventional tape carrier package. Is.

FIG. 8 is a diagram for explaining an inner lead bond.

FIG. 9 is a cross-sectional view of the tape carrier package after resin sealing.

FIG. 10 is a plan view after the liquid crystal driver is mounted on the liquid crystal panel.

FIG. 11 is a diagram for explaining a problem of the conventional technique.

[Explanation of symbols]

 1 Silicon Chip 2 Polyimide Tape 3 Solder Resist 4 Inner Lead 5a Input Outer Lead 5b Output Outer Lead 6 Alignment Mark Using Inner Lead 6a Convex 6b Bar 7 Inner Lead Bonding Device Pattern Recognition Area 8 Device Hole

Claims (3)

[Claims] 1. A tape carrier package in which an inner lead is formed on an insulating film having a device hole so as to project into the device hole, and the inner lead and a semiconductor chip are connected to each other. At least one alignment mark is provided on each of the opposite corner portions of the set, and the alignment mark has a plurality of inner leads, one or a plurality of bar portions connecting the inner leads, and the bar portion of the inner lead. A tape carrier package, comprising: one or a plurality of convex portions formed on the side not formed. 2. The tape carrier package according to claim 1, wherein the bar portions are formed at the tips of the plurality of inner leads that serve as the alignment marks. 3. The at least one convex portion is formed on each of the plurality of inner leads serving as the alignment mark on the side where the bar portion is not formed, and the at least one convex portion is formed. The listed tape carrier package.