JPH09282273A - Data transfer method and communication control unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication control unit for efficiently detecting a transaction error in split transfer. SOLUTION: This communication control unit(CCU) 17 connected to an IO bus 16 and a communication channel 3 is provided with a basic part 27 for performing the split transfer and an error detection part 58 constituted of an AC decoder 51, an ID decoder 52, a flag holding circuit 53 and AND gates 54-57. The error detection part 58 judges whether or not response signals received by the CCU 17 are previously requested signals and outputs signals for indicating incorrect reception in the case that they are not the requested signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer technique on a system bus and an IO bus, more specifically,
The present invention relates to an error detection technique in a split transfer system that transfers address information and data information alternately.

[0002]

2. Description of the Related Art At least two methods are known as data transfer methods on a system bus and an IO bus. The first method is an interlock transfer method. In this method, an address and data are transferred by occupying the bus once. The second method is a split transfer method. In this method, the bus is temporarily released between address transfer and data transfer.

Conventionally, in this split transfer system,
There is provided error detection means for detecting whether or not the reply signal in the reply transaction corresponds to the request signal in the preceding request transaction. The conventional error detecting means based on this split transfer method will be described with reference to FIG.

FIG. 6 shows an example of the block configuration of an error detecting means in a conventional bus interface adapter (hereinafter referred to as BIA). This BIA15 is
A bus conversion circuit 61 connected to the system bus 13 and the IO bus 16 is provided, and the bus conversion circuit 61 controls data transfer between the system bus 13 and the IO bus 16. System bus 13 and IO bus 16 are both A
C (access code) bus line and ADD / DAT
Includes (address / data) bus lines.

The error detection unit 66 includes an IO bus address holding circuit 62, an AC decoder 63, a comparison circuit 64, and an A
It is composed of an ND gate 65. The AC decoder 63 is
The response signal is identified. The comparison circuit 64 is AD
Address information and I included in the signal from the D / DAT bus
The I / O bus address held in the O bus address holding circuit 62 is compared to determine whether or not the response signal is for a communication control device (not shown) connected to the IO bus 16. In the AND gate 65, ADD / D
If the signal from the AT bus is in response to the request signal from the communication control device, it outputs OK, otherwise it outputs NG. The error detection unit 66 may be provided in the bus interface device 14 instead of being provided in the BIA 15.

[0006]

As described above, conventionally, the BIA 15 above the IO bus 16 is provided with the error detecting means. However, such an error detecting means can only determine whether or not the response signal is related to the subordinate IO bus address, but cannot determine whether or not the response signal is related to the local memory address in the requesting communication control device. . Further, even if the communication control device which is the request source is provided with an error detection means for detecting whether or not the response signal is related to the local memory address,
Since the comparison means of the split ID which is the local memory address is composed of the holding circuit and the comparison circuit of the multi-bit data string, the physical hardware amount becomes large. The amount of hardware also increases with an increase in the number of split transfer outstandings.

Therefore, an object of the present invention is to provide a data transfer method for efficiently confirming whether or not a response signal received by a communication control device is a signal based on a request signal transmitted by itself. Another object of the present invention is to provide a communication control device suitable for implementing the above data transfer method.

[0008]

A data transfer method provided by the present invention transmits a request signal for requesting data transmission to a data transmission terminal and request target data sent in response to the request signal. A data transfer method in a communication control device, comprising: a data transfer means for receiving a response signal, the data transfer means including at least the request signal with identification information for specifying the request signal. And a step of holding the identification information together with a request signal to which the response signal is previously transmitted based on specific information that can be collated with the identification information included in the response signal when the response signal is received. And a step of determining whether or not the data has been returned according to the above.

Further, the communication control device provided by the present invention is
Transmitting means for generating and transmitting a request signal requesting transmission of required data to the data transmitting terminal, and receiving means for receiving a response signal including required data transmitted from the data transmitting terminal in response to the request signal. And a determination unit that determines whether or not the received response signal is a signal based on the previously transmitted request signal.

In the communication control device having the above-mentioned configuration, the transmitting means includes, for example, identification information adding means for adding identification information for specifying the request signal to the request signal, and the determining means includes: Holding means for holding the identification information added to the request signal transmitted to the data transmission terminal, and the response signal received and the identification information held in the holding means are collated to determine according to the collation result. Determination means for outputting information.

[0011]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention. In this computer system, FNP (Front End Network Processo)
r) 1 is a host computer 2 as an example of an external terminal
And the communication line 3.

In the FNP 1, a central processing unit (hereinafter CPU) 11 and a main memory device (hereinafter MEM) 12 are connected to a system bus 13. The system bus 13 has a bus interface unit (BIU) 14
Has a bus interface adapter (BIA) 15
However, an IO bus (input / output bus) 16 is connected to each BIA 15. Further, a plurality of communication control units (hereinafter, CCU) 17 and online adapters (hereinafter, OLA) 18 are connected to the IO bus 16.

The OLA 18 is connected to the host computer 2, and each CCU 17 is connected to a communication line 3 such as a public line or a communication line network. BIA15 is IO
Data transfer between the bus 16 and the system bus 13, and I
It monitors the timeout of transactions on the O-bus 16. In the computer system according to the present embodiment, one of the BIA 15 and the BIU 14 has
An error detection unit 66 according to the related art shown in FIG.

FIG. 2 is a block diagram of the CCU 17 according to this embodiment. In the basic unit 27 that performs basic communication control of the CCU 17, the IO bus interface 21
, The micro CPU 23, the local memory 24, and the serial / parallel conversion circuit 25 are respectively connected to the internal bus 22.
A line transceiver / receiver circuit 26 is connected to the serial / parallel conversion circuit 25. The line transceiver / receiver circuit 26 is the communication line 3
It is connected to the. The other end of the IO bus interface 21 is connected to the IO bus 16. The serial / parallel conversion circuit 25 performs serial / parallel conversion of communication data.

The IO bus 16 has an ADD / DAT (address / data) signal, an AC (access code) signal, and various control signals (B_REQ signal, C_SEL signal, AC).
It includes a bus line for inputting / outputting a K signal). A
DD / DAT bus line signal is 32 bits (4 bytes)
In width, the AC bus line signal determines the type of transaction and the number of bytes transferred. The table in FIG. 3 shows more detailed contents of these bus line signals.

When the bus is activated, the CCU 17 transmits a B_REQ signal as a bus use right acquisition request. BIA1
As a result of the arbitration, 5 uses B_REQ_A as the bus use right.
Transmit the CK signal. At this time, the CCU 17 becomes the bus master and the first bus cycle is started.

When the CCU 17 is a slave (subordinate),
BIA15 becomes the master. In this case, the first bus cycle is started by outputting the C_SEL signal as the card selection signal of the CCU 17. One bus cycle is handshaked and divided by the ACK signal output from the slave side.

FIGS. 4A and 4B are timing charts showing an example of the timing of the split transaction. Here, the CCU 17 sets the MEM address to [A
An example of reading 16 bytes of data from the [ _MEM ] address is shown. FIG. 4A shows signals on each bus line in the request transaction. In the specific information adding means at the time of transmitting the request signal, the CCU 17 serves as a master, the MEM address of the read destination is the transfer destination address, and the address of the local memory 24 of the storage destination which is the specific information for specifying the request signal is the data D _LM as
Transfer to IA15. After that, the CCU 17 once releases the IO bus 16. FIG. 4B shows a reply transaction. In this case, the BIA 15 becomes the master, and data transfer is started with the previously transferred address of the local memory 24 as the transfer destination address.

FIG. 5 is a block diagram showing the configuration of the error detection unit provided in the CCU 17 according to this embodiment and providing the discrimination means. The error detection unit 58 is composed of an AC decoder 51, an ID decoder 52, a flag holding circuit 53, and AND gates 54 to 57.

The AC decoder 51 decodes an access code which indicates a transaction type whether the transfer on the IO bus 16 is a request transaction or a reply transaction. The ID decoder 52 uses the split local ID as the transfer destination local memory 2
Decode the address of 4. That is, the data part is decoded at the time of the request transaction, and the address part is decoded at the time of the reply transaction. The flag holding circuit 53 holds the same address as the address of the transfer destination local memory 24, and sets a flag when the request transaction is activated. Then, if the flag is set when the reply transaction is received, it is cleared.

Thus, when the reply transaction is received while the flag is set, it is determined as normal reception, and when the reply transaction is received in the clear state, it is determined as illegal reception. In addition, even if the reply transaction is received but the split IDs do not match, it is determined that the reception is illegal. As a result, it is possible to detect the case where a reply transaction is received even though the request transaction is not activated, or even the legitimacy of the address of the transfer destination local memory 24 when the reply transaction is received for the request.

Further, when the number of outstandings or the number of areas of the transfer destination local memory 24 is increased, it can be dealt with only by adding the flag holding circuit 53 and the condition of the ID decoder 52.

In this embodiment, the BIA 15 or the BIU 14 is further provided with the error detecting section 66 for detecting an error in the IO address of the reply transaction, so that an error in the split transfer can be widely detected. In particular, it is possible to significantly reduce the amount of hardware as compared with the method of holding the split ID and comparing it when the reply transaction is received.

[0024]

As is apparent from the above description, according to the present invention, the circuit configuration required for detecting an error related to split transfer does not become complicated and large in size as the number of transfers increases. The split transfer error can be detected almost comprehensively and economically and efficiently.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a computer system according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a communication control device according to the present embodiment.

FIG. 3 is a table showing more detailed contents of bus line signals according to the present embodiment.

FIG. 4 is a configuration diagram of an error detection unit of the communication control device according to the present embodiment.

FIG. 5A is a diagram showing each bus line signal in a request transaction according to the present embodiment, and FIG.
FIG. 3 is a diagram showing each bus line signal in a reply transaction according to the present embodiment.

FIG. 6 is a block configuration diagram of an error detection unit provided in a BIA according to a conventional technique.

[Explanation of symbols]

 1 FNP 2 Host Computer 3 Communication Line 11 CPU 12 MEM 13 System Bus 14 BIU 15 BIA 16 IO Bus 17 CCU 18 OLA 21 IO Bus Interface 22 Internal Bus 23 Micro CPU 24 Local Memory 25 Serial / Parallel Conversion Circuit 26 Line Transceiver / Receiver Circuit 27 Basic unit of CCU 51, 63 AC decoder 52 ID decoder 53 Flag holding circuit 58, 66 Error detection unit 61 Bus conversion circuit 62 IO bus address holding circuit 64 Comparison circuit 54-57, 65 AND gate

[Procedure amendment]

[Submission date] June 13, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Change

[Correction contents]

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a computer system according to an embodiment of the present invention.

FIG. 2 is a block configuration diagram of a communication control device according to the present embodiment.

Chart showing more detailed contents of the bus line signals according to FIG. 3 embodiment.

FIG. 4A is a request transaction according to the present embodiment.
Diagram showing each bus line signal in the operation, (b)
In the reply transaction according to the present embodiment
The figure which showed each bus-line signal.

FIG. 5 is an error detection unit of the communication control device according to the present embodiment .
Configuration diagram of.

FIG. 6 is a block configuration diagram of an error detection unit provided in a BIA according to a conventional technique.

[Explanation of Codes] 1 FNP 2 Host computer 3 Communication line 11 CPU 12 MEM 13 System bus 14 BIU 15 BIA 16 IO bus 17 CCU 18 OLA 21 IO bus interface 22 Internal bus 23 Micro CPU 24 Local memory 25 Serial / parallel conversion circuit 26 Line Transceiver / Receiver Circuit 27 Basic Unit of CCU 51, 63 AC Decoder 52 ID Decoder 53 Flag Holding Circuit 58, 66 Error Detection Unit 61 Bus Conversion Circuit 62 IO Bus Address Holding Circuit 64 Comparison Circuit 54-57, 65 AND Gate

Claims (3)

[Claims] 1. A data transfer means for transmitting a request signal for requesting data transmission to a data transmitting terminal, and for receiving a response signal including request target data returned in response to the request signal. A data transfer method in a communication control device, wherein the data transfer means stores at least the identification information for identifying the request signal in the request signal and holds the identification information. When a response signal is received, whether or not the response signal is returned in response to the previously transmitted request signal based on the identification information that can be collated with the identification information included in the response signal A data transfer method comprising: performing a determining step. 2. A transmitting means for generating and transmitting a request signal for requesting transmission of required data to the data transmitting terminal, and a response signal including the required data transmitted from the data transmitting terminal in response to the request signal. A communication control device, comprising: a receiving unit that receives the received response signal; and a determination unit that determines whether the received response signal is a signal based on the previously transmitted request signal. 3. The transmitting means includes identification information adding means for adding to the request signal identification information for specifying the request signal, and the determining means transmits to the data transmitting terminal. Holding means for holding the identification information added to the request signal, a determination means for collating the received response signal and the identification information retained in the holding means, and outputting the determination information according to the collation result, The communication control device according to claim 2, further comprising: