CN112836453B - SAS controller frame buffer area structure design method - Google Patents
SAS controller frame buffer area structure design method Download PDFInfo
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- CN112836453B CN112836453B CN202110241041.XA CN202110241041A CN112836453B CN 112836453 B CN112836453 B CN 112836453B CN 202110241041 A CN202110241041 A CN 202110241041A CN 112836453 B CN112836453 B CN 112836453B
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Abstract
The invention provides a method for designing a frame buffer area structure of an SAS controller, which comprises the following steps: the structural design of an asymmetric buffer area is adopted in the two directions of sending and receiving; dividing frame transmit and receive buffers into fixed-format slots of a predefined size; setting a state word, an equipment description word, a frame header, data and a separator segment at each slot position of a frame receiving buffer zone; setting a control descriptor, data and a separator segment at each slot position of a frame sending buffer; when the SAS controller receives a data frame, writing the analyzed content of the OAF frame into an equipment description word of a frame receiving buffer area, and writing frame abnormal information into a status word; and when the SAS controller transmits the data frame, reading the control descriptor of the corresponding storage slot in the frame transmission buffer area, and generating the OAF frame according to the control descriptor field. The invention effectively supports multi-disk and multi-I/O concurrent data communication under SMP and SSP protocol types, and supports the high-efficiency management of the SAS controller to the multi-disk equipment and the diagnosis of various exceptions in the link.
Description
Technical Field
The invention belongs to the technical field of disk connection, and particularly relates to a method for designing a frame buffer area structure of an SAS controller.
Background
Sas (serial Attached scsi) is a high-speed serial interface, which uses a point-to-point transmission mode, embeds a data/command checking unit, has strong error correction capability, supports hot plug, has the characteristics of small pin number, high data transmission rate, high reliability, good compatibility and the like, and is widely used in the industry for a main I/O interface between a storage device and a host at present.
In order to complete high-speed transmission of end-to-end data, the SAS standard protocol defines different protocol stack layers to realize data encapsulation, encoding and conversion of high-speed interface physical signals. FIG. 1 depicts a typical controller implementation in the prior art that supports SAS standard protocols and consists essentially of the following components:
the physical layer L1 completes the functions of 8 b-10 b coding and decoding, BMC (Bi-phase Mark Code) coding and decoding, OOB signal generation and detection, data boundary synchronization and the like, and realizes the establishment of an end-to-end physical link and the negotiation of transmission rate;
the link layer L2, which creates various primitive and address frames to realize the identification, connection management, rate matching, clock compensation, transmission layer data CRC generation and check, data scrambling and descrambling of the end-to-end equipment;
the port layer L3 is responsible for the selection of physical ports, the application of connection and the scheduling of SAS frame transmission according to the request of the transmission layer data;
a transmission layer L4, encapsulating the application layer data into SAS frame with specific format according to protocol in the sending direction, and analyzing the received far-end SAS frame in the receiving direction;
a frame buffer L5 for buffering the data sent by the application layer and the data analyzed by the transmission layer;
DMA unit L6, which is responsible for data transfer between the host system memory unit and the frame buffer storage of the SAS controller;
bus interface unit L7, a bus interface between the DMA unit and the host system memory unit, such as an AXI or AHB interface.
SAS physical links may operate at physical rates defined by protocols such as 1.5Gbps, 3.0Gbps, 6.0Gbps, and 12.0Gbps at different times depending on connection configuration and end device characteristics. A typical protocol stack core unit generally works at a corresponding frequency of a physical link in an equal proportion according to a bit width of serial-to-parallel conversion of a physical layer. Taking 40-bit-wide parallel data as an example, typical operating clock frequencies of the kernel unit of the protocol stack are 37.5MHz, 75MHz, 150MHz and 300 MHz. In fig. 1, the operating clock frequencies of the DMA unit and the bus interface unit are generally in a consistent or specific proportional relationship with the memory unit, the bus, and the central processing unit of the host system. Therefore, at the same time, there may be significant differences in the operating frequency and phase of the DMA unit and the protocol stack core clocks, which significantly affect data communications of the SAS.
A typical frame buffer area unit adopts a double-port SRAM design, an A port and a B port can work at different clock frequencies, the difference of the clock frequencies and the phases between a DMA unit and a protocol stack kernel unit can be effectively isolated, the SAS protocol stack kernel is supported to work at different clock frequencies, and the speed requirements of various physical links are met. However, the existing SAS Protocol does not define a frame buffer unit structure to support data efficient communication of SSP (Serial SCSI Protocol, a sub-Protocol of the SAS standard) and SMP (Serial Management Protocol, a sub-Protocol of the SAS standard) Protocol types. Therefore, it is necessary to design a frame buffer structure facing SAS specific sub-protocol by combining features of SAS standard protocol and application scenario.
Disclosure of Invention
The invention aims to provide a method for designing a frame buffer area structure of an SAS controller, which is used for supporting SSP and SMP protocol type data communication under an SAS scene. The method for designing the frame buffer area structure of the SAS controller comprises the following steps:
adopting an asymmetric structure design in the two directions of sending and receiving of the frame buffer area;
dividing a frame transmission buffer and a frame reception buffer into storage slots of a predefined size and a fixed format;
setting a status word, a device description word, a frame header, buffer data and a separator segment in each storage slot of the frame receiving buffer;
setting a control descriptor, buffer data and a delimiter segment in each storage slot of the frame transmission buffer;
when the SAS controller receives a data frame, the analyzed content of the OAF frame is written into an equipment description field of the frame receiving buffer area, and frame abnormal information is written into the state field;
when the SAS controller sends a data frame, the control descriptor field of the corresponding storage slot in the frame sending buffer area is read, and an OAF frame is generated according to the control descriptor field.
Preferably, the status word is used to describe status information of a frame received by the protocol stack processing unit, and further includes a frame type, a frame length, and a plurality of exception description bits.
Preferably, the frame type includes an SSP frame or an SMP frame.
Preferably, the device description word is used to describe information related to a connection request OAF frame at a transmitting end, and further includes a connection rate, a connection request identifier, and a protocol type.
Preferably, a protocol stack kernel module of the SAS controller generates an OAF frame to request a connection according to the control descriptor.
Preferably, the control descriptor comprises a frame type, a target device SAS address, a source port transfer tag, a target port transfer tag, a data offset, a linked list DMA descriptor address, a connection request rate, a protocol type, and a connection request identification.
Preferably, the linked list DMA descriptor address is used to describe the storage location of the data in the current storage slot of the frame send buffer at the host system.
Preferably, if an SSP frame sending exception occurs, the host system performs exception handling according to the storage location identified by the linked list DMA descriptor address.
Preferably, a frame end flag bit is further set in each of the slots of the frame reception buffer and the frame transmission buffer for indicating an end of the current frame.
Preferably, a parity bit is further provided in each slot of the frame receiving buffer and the frame transmitting buffer for storing a parity result of the buffered data of the corresponding location in the frame buffer.
Compared with the prior art, the invention has the following advantages:
the method for designing the frame buffer area structure of the SAS controller effectively supports multi-disk and multi-I/O concurrent data communication under SMP and SSP protocol types, and supports the high-efficiency management of the SAS controller on multi-SAS disk equipment and the diagnosis of various exceptions in a link.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings needed to be used in the description of the embodiments or the prior art, wherein:
FIG. 1 shows a schematic diagram of a controller implementation supporting SAS standard protocols in accordance with the prior art.
Fig. 2 shows a timing diagram of a SAS standard protocol according to the prior art.
FIG. 3 is a schematic diagram of a SAS controller receive buffer structure in accordance with the present invention.
Fig. 4 shows a schematic diagram of a detailed structure of a status word in a receive buffer structure of a SAS controller according to fig. 3.
Fig. 5 is a schematic diagram illustrating a detailed structure of a device description word in a receive buffer structure of the SAS controller according to fig. 3.
FIG. 6 is a schematic diagram of a SAS controller transmit buffer structure in accordance with the present invention.
FIG. 7 is a diagram illustrating a detailed structure of a control descriptor for a transmit buffer structure according to the SAS controller of FIG. 6.
FIG. 8 is a flowchart illustrating an exemplary processing method of a protocol stack kernel when a SAS controller receives SAS device data frames in accordance with one embodiment of the present invention.
FIG. 9 is a flowchart of an exemplary processing method of a protocol stack core when a SAS controller transmits a data frame in accordance with one embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In a typical SAS data storage topology, a SAS controller supports concurrent control management of multiple disk devices through one or more levels of Expander(s) expansion. According to the SAS standard protocol shown in fig. 2, before the SAS controller or the SAS disk device performs SSP protocol data transmission, the link layer first sends an oaf (openaddress frame) frame to request for establishing a connection with a specified protocol and a specified rate. And the receiving terminal equipment responds to the Open Accept primitive, and after the connection is successfully established, the requesting equipment sends the SAS frame and waits for response handshake. In order to realize time-sharing multiplexing of physical links between the controller and the plurality of SAS devices and improve the utilization efficiency of the links, the two devices exchange DONE and CLOSE primitives to CLOSE connection after completing SAS frame transmission, and release the links.
According to the SAS standard protocol, the contents of the OAF frame include primary information such as the SAS protocol type, Connection request Rate (Connection Rate), Connection request Tag (Initiator Connection Tag), SAS address of the destination device, SAS address of the source device, and the like. In addition to carrying Data IU (Payload of SSP) of an application layer, a frame header content of a transport layer SSP frame (Serial SCSI Protocol) includes main Information such as a frame type, a destination device SAS address hash, a source device SAS address hash, a retransmission Control (TLR Control), a source port transmission flag (InitiatorPort transmission Tag), a target port transmission flag (TargetPort transmission Tag), and a Data Offset (Data).
Therefore, in the frame buffer design facing the SAS protocol, the invention combines a plurality of characteristics such as the transmission and the reception of the connection request frame OAF, the transmission and the reception of the SSP frame, the transmission and the reception of the SMP frame and the interleaving communication of a plurality of SAS devices. The invention fully considers the typical application scene of the SAS, aims to improve the transmission efficiency of the system and reasonably utilize the storage space of the frame buffer area, and adopts an asymmetric frame buffer area design structure in the transmitting and receiving directions of the SAS controller.
FIG. 3 depicts the SAS controller receive buffer structure of the present invention, the entire frame receive buffer is divided into a plurality of fixed-size slots, each slot including specific fields as illustrated below:
segment S1 is a status word with a length of 1 DWORD, and is used to describe the status information of the SSP frame or SMP frame received by the protocol stack processing unit, including the frame type (SSP or SMP), error type, IU effective length, etc.;
segment S2 is a device description word, 1 DWORD, and is used to describe the relevant information of the sending-end device connection request OAF frame, including the connection request rate, the protocol type, the connection request flag, and the like;
segment S3 is a frame header, 24 DWORDs, and for the SSP protocol, it stores SSP frame header information defined by the SAS standard protocol; for the SMP protocol, it is unused as a reserved field;
segment S4 is data, 256 DWORDs, for storing IU information of SSP frame, or complete content information of SMP frame;
segment S5 is an end of frame marker bit, with 1 bit for each DWORD in the buffer. Because the length of the IU frame or the SMP frame of the SSP frame is not fixed, and the frame length description field is not included in the frame, the frame tail mark bit is '1', and the end of the current SSP frame or SMP frame is indicated;
the segment S6 is a parity check bit, each DWORD corresponds to 1 bit and is used for storing the parity check result of one DWORD (bit 0-31) data at the corresponding position of the frame buffer area and ensuring the correctness of the frame buffer area data;
segment S7 is a separator, 1 DWORD, specifically encoded for isolation between the frame storage slots within the receive buffer.
The detailed description of the status word structure of the segment S1 is shown in fig. 4, and the specific fields are described as follows:
the field F1 is Frame Type, i.e. Frame Type, has a length of 8 bits, and is used to describe the Type of the Frame in the current slot, and according to the SAS standard protocol, the specific definition is as follows:
01H: SSP Data frame;
05H: an SSP XFER _ RDY frame;
06H: SSP Command frame;
07H: SSP Response frame;
16H, 16H: SSP Task frame;
40H: an SMP Request frame;
41H: SMP Response frames;
and others: an invalid frame;
the field F2 is Response Length Error, i.e., SSP Response frame Length Error;
the field F3 is Zero IU Error, i.e. IU information Zero length Error;
field F3 is CRC Error, i.e., SSP or SMP frame CRC (cyclic redundancy check) check Error;
the field F5 is a Frame Type Error, i.e., an invalid Frame Type Error;
the field F6 is Short Error, i.e., an insufficient frame length Error;
the field F7 is Long Error, i.e. the frame length is over-Long Error;
field F8 is No EOF, end of frame marker loss error;
the field F9 is XRDY Length Error, namely SSP XFER frame Length abnormity;
the field F10 is the frame length.
The detailed description of the structure of the device description word of the segment S2 is shown in fig. 5, and the specific fields are described as follows:
the field F1 is Protocol type, and the value 00h represents SMP Protocol; the value of 01h represents the SSP protocol;
the field F2 is the Connection Rate, i.e., the Connection request Rate. According to the SAS standard protocol, the following is specifically defined:
08h：1.5Gbps
09h：3.0Gbps
0Ah：6.0Gbps
0Bh：12Gbps
and others: retention
Domain F3: the Connection Tag, i.e., the Connection request flag, is used to store a unique Connection identifier assigned to each SAS device within the topology.
FIG. 6 depicts the SAS controller transmit buffer structure of the present invention, similar to the receive buffer, the entire frame transmit buffer is also divided into multiple fixed-size slots. By dividing the buffer into fixed size and format slots, the processing logic of the protocol stack kernel unit and the DMA unit is simplified, and the processing efficiency is accelerated. For a single slot of the transmit buffer, specific fields are further included as follows:
segment S1 is a control descriptor, 32 DWORDs in length, and is used to describe information such as frame type, protocol type, destination SAS device address, etc. in the current buffer slot. The protocol stack kernel module generates an OAF frame request connection according to the control descriptor and generates SMP and SSP frame header information;
segment S2 is data, 256 DWORDs, for storing IU information of SSP frames, or the complete content of SMP frames;
the segment S3 is a parity check bit, each DWORD corresponds to 1 bit and is used for storing the parity check result of one DWORD (bit 0-31) data at the corresponding position of the frame buffer area and ensuring the correctness of the data in the storage unit of the frame buffer area;
segment S4 is a frame end flag bit, each DWORD corresponds to 1 bit, and since the IU of the SSP frame or the SMP frame length is not fixed, and the frame length description field is not included inside the frame, the frame end flag bit is "1", indicating the end of the current SSP frame or SMP frame;
segment S5 is a separator, 1 DWORD, specifically encoded for isolation between the frame storage slots within the receive buffer.
The detailed description of the segment S1 control descriptor structure is as shown in fig. 7, and the specific fields are as follows:
the field F1 is Frame Type, which is used to describe the Type of the Frame in the current slot, and the specific Type is the same as the description of the Frame Type in fig. 4;
the field F2 is Destination SAS Address, namely the Destination equipment SAS Address;
the field F3 is TLR Control, namely retransmission Control, is only effective to SSP protocol, and is used as a reserved field for SMP protocol and is not used;
the field F4 is an InitiatorPort Transfer Tag, namely a source port transmission mark, and when a protocol stack kernel generates a standard SSP frame header, an I/O request of the SAS controller is identified according to the information; for SMP protocol, it is not used as reserved field;
the domain F5 is a Target Port Transfer Tag, namely a Target Port transmission mark, and when a protocol stack kernel generates a standard SSP frame header, a primary transmission request of an SAS device end is identified according to the information; for SMP protocol, it is not used as reserved field;
the field F6 is Data Offset, namely IU Data Offset, when the protocol stack kernel generates a standard SSP frame header, a Data Offset field is generated according to the information; for SMP protocol, it is not used as reserved field;
a field F7 is IU Length, i.e., the effective Length of the data segment S2, and is used to describe the IU information Length of the SSP frame, or the total Length of the SMP frame;
the field F8 is an SGDMA Descriptor Address, namely a linked list DMA Descriptor Address, and is used for describing the storage position of the DMA Descriptor corresponding to the data segment S2 of the current slot position of the buffer zone in the host system;
a field F9 is SGDMA Descriptor Remaining Length, i.e. the offset of the starting address of the Descriptor data of the linked list DMA; in the case of a physical link state change or contention, if a scenario of SSP Data frame transmission failure probabilistically occurs, the fields F8 and F9 identify the storage location of the currently transmitted failed frame in the host system, providing a basis for host system error handling and breakpoint retransmission;
the field F10 is Protocol, i.e. Protocol type, where 00h denotes SMP Protocol; 01h denotes SSP protocol;
the field F11 is a Connection Rate, that is, a Connection request Rate, and is specifically defined as the field F2 described above with reference to fig. 5;
domain F12 assigns a Connection Tag, i.e., Connection request label, to each SAS device in the storage topology a unique Connection id.
Based on the above design structure of the receive and transmit frame buffers, according to an embodiment of the present invention, referring to fig. 8, from the perspective of receiving data frames of an SAS device from an SAS controller, an exemplary processing flow of a protocol stack kernel after adopting the design structure of the receive buffer of the present invention is as follows.
Step S1: a protocol stack link layer receives a connection request frame OAF sent by SAS equipment;
step S2: the protocol stack kernel checks whether the frame receiving buffer has a free slot for storing the SAS frame. If the frame buffer has a free slot, executing step S4; otherwise, executing step S3;
step S3: the link layer sends an OPEN _ REJECT (RETRY) primitive to temporarily reject the connection request of the SAS device; and proceeds to step S8;
step S4: the protocol stack link layer replies an OPEN _ ACCEPT primitive to establish the connection between the SAS controller and the SAS equipment; analyzing the content of the OAF frame, writing the Protocol type Protocol, the Connection Rate and the Connection Tag information of the Connection request into the device description words of the slot corresponding to the frame buffer, namely respectively writing the device description words into a field F1, a field F2 and a field F3 of the FIG. 5;
step S5: the protocol stack kernel receives an SSP data frame of the SAS equipment, and the transmission layer writes 24 DWORDs of an SSP data frame header into a frame header section of a frame buffer zone; writing the frame IU information into the data segment, and setting a frame tail mark bit at the end point of the IU information; simultaneously, performing parity check calculation and setting a parity check bit of a frame buffer area;
step S6: checking the integrity and correctness of SSP data frame by protocol stack kernel transmission layer, writing frame type, IU length and frame error information into the status word of receiving buffer area; simultaneously, performing parity check calculation and setting a parity check bit of a frame buffer area;
step S7: the protocol stack kernel informs the DMA receiving unit that the data frame reaches the receiving buffer area;
step S8: the protocol stack kernel completes one receive transaction.
According to another embodiment of the present invention, referring to fig. 9, an exemplary processing flow of the protocol stack kernel after adopting the design structure of the transmission buffer according to the present invention from the perspective of transmitting data frames from the SAS controller is as follows.
Step S1: the protocol stack kernel detects that the sending buffer is not empty, namely, data waiting for sending exist;
step S2: the Protocol stack kernel reads the control descriptor of the corresponding slot position, and generates an OAF frame according to the Protocol, the Connection Rate, the Connection Tag, the Destination SAS Address and the SAS Address of the SAS controller in the descriptor information;
step S3: the protocol stack link layer sends an OAF frame and requests SAS equipment to establish connection;
step S4: the link layer receives the SAS device response, and if the connection establishment is successful, the step S5 is performed; otherwise, if the connection is failed to be established, the step S7 is directly performed;
step S5: the protocol stack transmission layer generates a Frame header of an SSP Data Frame according to information such as Frame Type, Initiator Port Transfer Tag, Target Port Transfer Tag, Data Offset, TLR Control, SAS Address and the like in the Control descriptor information, and transmits the Frame header of the SSP Data Frame downwards to the link layer; reading Data in a frame buffer area according to IU Length in the control descriptor information, transmitting the Data serving as the IU information of the SSP Data frame to a link layer downwards, and finally transmitting the Data to SAS equipment;
step S6: after the protocol stack link layer sends an SSP Data frame, the SAS device is waited to return handshake information. If the transmission fails, go to step S7; if the transmission is successful, go directly to step S8;
step S7: the SAS equipment returns that SSP Data frame reception fails, the SAS controller reports an abnormal state, and returns information such as SG DMA Descriptor Address and SG DMA Descriptor Data Offset in the control Descriptor, so as to help the host system to implement rollback processing of abnormal Data;
step S8: the protocol stack kernel completes one send transaction.
It will be appreciated by those skilled in the art that the names of the frame buffer structures described in the above embodiments are merely examples. The core concept of the invention is not limited to specific data fields. One skilled in the art can define any data structure to implement the functions of the frame buffer as desired. The design method of the invention is also suitable for the scenes of narrow ports and wide ports, multi-disk and multi-I/O defined in the SAS protocol.
The invention provides a frame buffer structure design method facing to the SAS standard protocol, which effectively supports multi-disk and multi-I/O concurrent data communication under SMP and SSP two protocol types and supports an SAS controller to efficiently manage multi-SAS disk equipment. The invention introduces the control descriptor field into the frame sending buffer area to assist the protocol stack kernel to rapidly generate the OAF frame, thereby improving the speed of establishing connection between the SAS controller and the SAS equipment, and sending the linked list DMA information of the control descriptor field of the buffer area under the condition of abnormity in the frame sending process, and helping the SAS controller to complete the rapid rollback of abnormal data; the status description word in the frame receiving buffer provides the feasibility of recording frame abnormality by the protocol stack, so that the SAS controller realizes diagnosis of various abnormalities in the link.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for designing a frame buffer structure of an SAS controller is characterized by comprising the following steps:
adopting an asymmetric structure design in the two directions of sending and receiving of the frame buffer area;
dividing a frame transmission buffer and a frame reception buffer into storage slots of a predefined size and a fixed format;
setting a status word, a device description word, a frame header, buffer data and a delimiter field in each storage slot of the frame receiving buffer;
setting a control descriptor, buffer data and a delimiter field in each slot of the frame transmission buffer;
when the SAS controller receives a data frame, the analyzed content of the OAF frame is written into an equipment description word field of the frame receiving buffer area, and frame abnormal information is written into the status word field;
when the SAS controller sends a data frame, the control descriptor field of the corresponding storage slot in the frame sending buffer area is read, and an OAF frame is generated according to the control descriptor field.
2. The SAS controller frame buffer configuration design method of claim 1 wherein the status word is used to describe status information of frames received by a protocol stack processing unit and further comprises a frame type, a frame length, and a plurality of exception description bits.
3. The SAS controller frame buffer configuration design method of claim 2, wherein the frame type comprises an SSP frame or an SMP frame.
4. The SAS controller frame buffer configuration design method of claim 1, wherein:
the device description word is used for describing relevant information of a connection request OAF frame generated by a sending end, and further comprises a connection rate, a connection request identification and a protocol type.
5. The method of claim 1, wherein a protocol stack kernel module of the SAS controller generates an OAF frame from the control descriptor to request a connection.
6. The SAS controller frame buffer configuration design method of claim 5,
wherein the control descriptor includes a frame type, a target device SAS address, a source port transfer tag, a target port transfer tag, a data offset, a linked list DMA descriptor address, a connection request rate, a protocol type, and a connection request identification.
7. The SAS controller frame buffer configuration design method of claim 6, wherein said linked list DMA descriptor address is used to describe the storage location of the data in the current storage slot of said frame transmit buffer at the host system.
8. The SAS controller frame buffer configuration design method of claim 7 wherein, if an SSP frame send exception occurs, the host system performs exception handling based on the memory location identified by the linked list DMA descriptor address.
9. The method of claim 1 wherein a frame tail flag bit is further set in each slot of the frame receive buffer and the frame transmit buffer to indicate the end of the current frame.
10. The method of claim 1, wherein a parity bit is further provided in each slot of the frame receive buffer and the frame transmit buffer for storing a parity result of the buffered data at the corresponding location in the frame buffer.
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| US6031843A (en) * | 1996-11-21 | 2000-02-29 | Alcatel Data Networks Inc. | Digital communications switching fabric |
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